2Gb - 128M x 16 DDR2 SDRAM · The DDR2 SDRAM uses a double data rate architecture to achieve...

MYX4DDR2128M16PK*Revision 1.5 - 03/27/2015

*Advanced information. Subject to change without notice.

1

2Gb DDR2 SDRAMMYX4DDR2128M16PK*

Form #: CSI-D-685 Document 006

2Gb - 128M x 16 DDR2 SDRAM

Features

• Tin-leadballmetallurgy

• VDD=1.8V±0.1V,VDDQ=1.8V±0.1V

• JEDEC-standard1.8VI/O(SSTL_18-compatible)

• Differentialdatastrobe(DQS,DQS#)option

• 4n-bitprefetcharchitecture

• Duplicateoutputstrobe

• DLLtoalignDQandDQStransitionswithCK

• 8internalbanksforconcurrentoperation

• ProgrammableCASlatency(CL)

• PostedCASadditivelatency(AL)

• WRITElatency=READlatency-1tCK

• Programmableburstlengths:4or8

• Adjustabledata-outputdrivestrength

• 64ms,8192-cyclerefresh

• On-dietermination(ODT)

• Industrialtemperature(IT)option

• SupportsJEDECclockjitterspecification

Options Code

• Configuration

� 128Megx16 128M16(16Megx16x8banks)

• FBGApackage(Sn63/Pb37) BG

� 84-ballFBGA(9mmx12.5mm) PK

• Timing–cycletime

� 2.5ns@CL=5(DDR2-800) -25E

• Operatingtemperature

� Commercial(0°C≤ TC≤+85°C) None

� Industrial(–40°C≤TC≤+95°C; IT–40°C≤TA≤+85°C)

Table 1: Key Timing Parameters

Speed Grade

Data Rate (MT/s)tRC (ns)

CL=3 CL=4 CL=5 CL=6 CL=7

-25E 400 533 800 800 N/A 55

Table 2: Addressing

Parameter 128 Meg x 16

Configuration 16 Meg x 16 x 8 banks

Refresh count 8K

Row address A[13:0] (16K)

Bank address BA[2:0] (8)

Column address A[9:0] (1K)



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Contents1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . .3

2 Ball Assignments and Descriptions . . . . . . . . . . . . . . . .4

3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . .63.1 Industrial Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.3 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Mode Register (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . .104.1 Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.4 DLL RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.5 Write Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.6 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.7 CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Extended Mode Register (EMR) . . . . . . . . . . . . . . . . . .145.1 DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2 Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3 DQS# Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4 Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . 16

5.5 On-Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . 17

5.6 Off-Chip Driver (OCD) Impedance Calibration . . . . . . . . 17

5.7 Posted CAS Additive Latency (AL) . . . . . . . . . . . . . . . . 17

6 Extended Mode Register 2 (EMR2) . . . . . . . . . . . . . . . .18

7 Extended Mode Register 3 (EMR3) . . . . . . . . . . . . . . . .19

8 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208.1 Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.2 DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.3 NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . 21

8.4 LOAD MODE (LM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.5 ACTIVATE COMMAND . . . . . . . . . . . . . . . . . . . . . . . . 22

8.6 ACTIVATE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . 22

8 .7 READ COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.8 READ OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.9 WRITE COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.10 WRITE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8 .11 PRECHARGE COMMAND . . . . . . . . . . . . . . . . . . . . . . 26

8.12 PRECHARGE OPERATION . . . . . . . . . . . . . . . . . . . . . . 27

8.13 REFRESH COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.14 SELF REFRESH COMMAND . . . . . . . . . . . . . . . . . . . . 27

9 ElectricalSpecifications . . . . . . . . . . . . . . . . . . . . . . . .289.1 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9.2 Temperature and Thermal Impedance . . . . . . . . . . . . . 29

9.3 FBGA Package Capacitance . . . . . . . . . . . . . . . . . . . . 31

9 .4 IDD Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9.5 AC Timing Operating Specifications . . . . . . . . . . . . . . . 33

10 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

11 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .38



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1 Functional Block Diagram

TheDDR2SDRAMisahigh-speedCMOS,dynamicrandomaccessmemory.ItisinternallyconfiguredasamultibankDRAM.

Figure 1: Functional Block Diagram – 128 Meg x 16Figure 5: Functional Block Diagram – 128 Meg x 16

Bank 5Bank 6

Bank 7

Bank 4

Bank 7

Bank 4Bank 5

Bank 6

14 Row-address

MUX

Controllogic

Column-addresscounter/

latch

Moderegisters

10

A[13:0],BA[2:0]

14

Addressregister

256(x64)

16,384

Columndecoder

Bank 0

Memory array(16,384 x 256 x 64)

Bank 0row-

addresslatchand

decoder

16,384

Sense amplifier

Bankcontrol

logic

16

Bank 1Bank 2

Bank 3

14

8

3

2

Refreshcounter

16

1616

4

64

64

64

CK out

DATA

UDQS, UDQS#LDQS, LDQS#

CK, CK#

CK, CK#COL0, COL1

COL0, COL1

CK in

DRVRS

DLL

MUX

DQSgenerator

16

16

16

16

16

UDQS, UDQS#LDQS, LDQS#

4

Readlatch

WRITEFIFOand

drivers

Data

16

16

16

1664

2

2

2

2Mask

2

2

2

228

16

16

2

Bank 1Bank 2

Bank 3

Inputregisters

UDM, LDM

DQ[15:0]

VDDQ

R1

R1

R2

R2

sw1 sw2

VSSQ

sw1 sw2ODT controlRAS#

CAS#

CK

CS#

WE#

CK#

Com

man

dde

code

CKE

ODT

I/O gatingDM mask logic

16

sw3

R3

R3

sw3

R1

R1

R2

R2

sw1 sw2

R3

R3

sw3

R1

R1

R2

R2

sw1 sw2

R3

R3

sw3

RCVRS

2Gb: x4, x8, x16 DDR2 SDRAMFunctional Block Diagrams

PDF: 09005aef824f87b62Gb_DDR2.pdf – Rev. H 10/11 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice.

� 2006 Micron Technology, Inc. All rights reserved.



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2 Ball Assignments and Descriptions

Figure 2: 84-Ball FBGA – x16 Ball Assignments (Top View)Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View)

1 2 3 4 6 7 8 95

VDD

DQ14

VDDQ

DQ12

VDD

DQ6

VDDQ

DQ4

VDDL

BA2

VSS

VDD

NC

VSSQ

DQ9

VSSQ

NC

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10

A3

A7

A12

VSS

UDM

VDDQ

DQ11

VSS

LDM

VDDQ

DQ3

VSS

WE#

BA1

A1

A5

A9

RFU

VSSQ

UDQS

VDDQ

DQ10

VSSQ

LDQS

VDDQ

DQ2

VSSDL

RAS#

CAS#

A2

A6

A11

RFU

VDDQ

DQ15

VDDQ

DQ13

VDDQ

DQ7

VDDQ

DQ5

VDD

ODT

VDD

VSS

UDQS#/NU

VSSQ

DQ8

VSSQ

LDQS#/NU

VSSQ

DQ0

VSSQ

CK

CK#

CS#

A0

A4

A8

A13

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

2Gb: x4, x8, x16 DDR2 SDRAMBall Assignments and Descriptions





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Table 3: FBGA 84-Ball – x16 Descriptions

Symbol Type Description

A[13:0] (x16) Input

Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command.

BA[2:0] InputBank address inputs: BA[2:0] define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command.

CK, CK# InputClock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.

CKE Input

Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides precharge power-down and SELF REFRESH operation (all banks idle), or ACTIVATE power-down (row active in any bank). CKE is synchronous for power-down entry, power-down exit, output disable, and for self refresh entry. CKE is asynchronous for SELF REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during self refresh. CKE is an SSTL_18 input but will detect a LVCMOS LOW level once VDD is applied during first power-up. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper SELF REFRESH operation, VREF must be maintained.

CS# InputChip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered high. CS# provides for external bank selection on systems with multiple ranks. CS# is considered part of the command code.

LDM, UDM (DM) InputInput data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled HIGH during a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to match that of DQ and DQS balls. LDM is DM for lower byte DQ[7:0] and UDM is DM for upper byte DQ[15:8].

ODT Input

On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls: DQ[15:0], LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input will be ignored if disabled via the LOAD MODE command.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered.

DQ[15:0] (x16) I/O Data input/output: Bidirectional data bus for 128 Meg x 16.

DQS, DQS# I/OData strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command.

LDQS, LDQS# I/OData strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE command.

UDQS, UDQS# I/OData strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE command.

VDD Supply Power supply: 1.8V ±0.1V

VDDQ Supply DQ power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity.

VDDL Supply DLL power supply: 1.8V ±0.1V.

VREF Supply SSTL_18 reference voltage.



6



Symbol Type Description

VSS Supply Ground.

VSSDL Supply DLL ground: Isolated on the device from VSS and VSSQ .

VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.

NC - No connect: These balls should be left unconnected.

NF - No function

NU - Not used

NU - Not used

RFU - Reserved for future use: Row address bits A14 (R3), A15 (R7)

3 Functional Description

TheDDR2SDRAMusesadoubledataratearchitecturetoachievehigh-speedoperation.Thedoubledataratearchitectureisessentiallya4n-prefetcharchitecture,withaninterfacedesignedtotransfertwodatawordsperclockcycleattheI/Oballs.AsinglereadorwriteaccessfortheDDR2SDRAMeffectivelyconsistsofasingle4n-bit-wide,one-clock-cycledatatransferattheinternalDRAMcoreandfourcorrespondingn-bitwide,one-half-clock-cycledatatransfersattheI/Oballs.

Abidirectionaldatastrobe(DQS,DQS#)istransmittedexternally,alongwithdata,foruseindatacaptureatthereceiver.DQSisastrobetransmittedbytheDDR2SDRAMduringREADsandbythememorycontrollerduringWRITEs.DQSisedge-alignedwithdataforREADsandcenter-alignedwithdataforWRITEs.Thex16offeringhastwodatastrobes,oneforthelowerbyte(LDQS,LDQS#)andonefortheupperbyte(UDQS,UDQS#).

TheDDR2SDRAMoperates froma differential clock (CK andCK#); the crossing ofCKgoingHIGHandCK#goingLOWwillbereferredtoasthepositiveedgeofCK.Commands(addressandcontrolsignals)areregisteredateverypositiveedgeofCK.Inputdata isregisteredonbothedgesofDQS,andoutputdata isreferencedtobothedgesofDQSaswellastobothedgesofCK.

Read andwrite accesses to the DDR2 SDRAM are burst-oriented; accesses start at a selected locationandcontinueforaprogrammednumberof locations inaprogrammedsequence.AccessesbeginwiththeregistrationofanACTIVATEcommand,whichisthenfollowedbyaREADorWRITEcommand.TheaddressbitsregisteredcoincidentwiththeACTIVATEcommandareusedtoselectthebankandrowtobeaccessed.TheaddressbitsregisteredcoincidentwiththeREADorWRITEcommandareusedtoselectthebankandthestartingcolumnlocationfortheburstaccess.

TheDDR2SDRAMprovidesforprogrammablereadorwriteburst lengthsof fouroreight locations.DDR2SDRAMsupportsinterruptingaburstreadofeightwithanotherreadoraburstwriteofeightwithanotherwrite.Anautoprechargefunctionmaybeenabledtoprovideaself-timedrowprechargethatisinitiatedattheendoftheburstaccess.



7



AswithstandardDDRSDRAM, thepipelined,multibankarchitectureofDDR2SDRAMenablesconcurrentoperation,therebyprovidinghigh,effectivebandwidthbyhidingrowprechargeandactivationtime.

Aselfrefreshmodeisprovided,alongwithapower-saving,power-downmode.

AllinputsarecompatiblewiththeJEDECstandardforSSTL_18.Allfulldrive-strengthoutputsareSSTL_18-compatible.

3 .1 Industrial Temperature

The industrial temperature (IT) option, if offered, has two simultaneous requirements: ambient temperaturesurroundingthedevicecannotbelessthan-40°Corgreaterthan85°C,andthecasetemperaturecannotbelessthan-40°Corgreaterthan95°C.JEDECspecificationsrequiretherefreshratetodoublewhenTCexceeds85°C; thisalsorequiresuseof thehigh-temperatureself refreshoption.Additionally,ODTresistance, input/outputimpedanceandIDDvaluesmustbederatedwhenTCis<0°Cor>85°C.

3 .2 General Notes

• ThefunctionalityandthetimingspecificationsdiscussedinthisdatasheetarefortheDLL-enabledmodeofoperation.

• Throughoutthedatasheet,thevariousfiguresandtextrefertoDQsas“DQ.”TheDQtermistobeinterpretedasanyandallDQcollectively,unlessspecificallystatedotherwise.Additionally,thex16isdividedinto2bytes:thelowerbyteandtheupperbyte.Forthelowerbyte(DQ[7:0]),DMreferstoLDMandDQSreferstoLDQS.Fortheupperbyte(DQ[15:8]),DMreferstoUDMandDQSreferstoUDQS.

• Ax16device’sDQbusiscomprisedoftwobytes.Ifonlyoneofthebytesneedstobeused,usethelowerbytefordatatransfersandterminatetheupperbyteasnoted:

� ConnectUDQStogroundvia1kΩ*resistor

� ConnectUDQS#toVDDvia1kΩ*resistor

� ConnectUDMtoVDDvia1kΩ*resistor

� ConnectDQ[15:8]individuallytoeitherVSSorVDDvia1kΩ*resistors,orfloatDQ[15:8].

*IfODTisused,1kΩresistorshouldbechangedto4xthatoftheselectedODT.

• Completefunctionalityisdescribedthroughoutthedocument,andanypageordiagrammayhavebeensimplifiedtoconveyatopicandmaynotbeinclusiveofallrequirements.

• Anyspecificrequirementtakesprecedenceoverageneralstatement.



8



3 .3 Initialization

DDR2SDRAMmustbepoweredupandinitializedinapredefinedmanner.Operationalproceduresotherthanthosespecifiedmay result inundefinedoperation.Figure3 illustrates,and thenotesoutline, thesequencerequiredforpower-upandinitialization.

Figure 3: DDR2 Power-Up and Initialization

Initialization

Figure 43: DDR2 Power-Up and Initialization

DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in unde-fined operation. Figure 43 illustrates, and the notes outline, the sequence required for power-up and initialization.

tVTD1

CKE

Rtt

Power-up: VDD and stable clock (CK, CK#)

T = 200μs (MIN)3

High-Z

DM15

DQS15 High-Z

Address16

CK

CK#

tCL

VTT1

VREF

VDDQ

Command NOP3 PRE

T0 Ta0

Don’t care

tCL

tCK

VDD

ODT

DQ15 High-Z

Tb0

200 cycles of CK are required before a READ command can be issued

MR withDLL RESET

tRFC

LM8 PRE9LM7 REF10 REF10 LM11

Tg0 Th0 Ti0 Tj0

MR withoutDLL RESET

EMR withOCD default

Tk0 Tl0 Tm0Te0 Tf0

EMR(2) EMR(3)

tMRD

LM6LM5

A10 = 1

tRPA

Tc0 Td0

SSTL_18 low level

2

Valid14

Valid

Indicates a Break in Time Scale

LM12

EMR withOCD exit

LM13

Normaloperation

��

Code Code A10 = 1Code Code Code Code Code

tMRD tMRD tMRD tMRDtRPA tRFC

VDDL

tMRD tMRD

EMR

T = 400ns (MIN)4

LVCMOSlow level2

2G

b: x

4, x

8, x

16

DD

R2

SD

RA

MIn

itializa

tion

PDF: 09005aef824f87b

62G

b_D

DR

2.pd

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10/11 EN88

Micro

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Notes:

1. Applyingpower;ifCKEismaintainedbelow0.2×VDDQ,outputsremaindisabled.ToguaranteeRTT(ODTresistance)isoff,VREFmustbevalidandalowlevelmustbeappliedtotheODTball(allotherinputsmaybeundefined;I/OsandoutputsmustbelessthanVDDQduringvoltageramptimetoavoidDDR2SDRAMdevicelatch-up).VTTisnotapplieddirectlytothedevice;however,tVTDshouldbe≥0toavoiddevicelatch-up.Atleastoneofthefollowingtwosetsofconditions(AorB)mustbemettoobtainastablesupplystate(stablesupplydefinedasVDD,VDDL,VDDQ,VREF,andVTTarebetweentheirminimumandmaximumvaluesasstatedinTable8(page29):



9



A. Singlepowersource:TheVDDvoltagerampfrom300mVtoVDD,minmusttakenolongerthan200ms;duringtheVDDvoltageramp,|VDD-VDDQ|≤0.3V.Oncesupplyvoltagerampingiscomplete(whenVDDQcrossesVDD,min),Table8(page29)specificationsapply.

� VDD,VDDL,andVDDQaredrivenfromasinglepowerconverteroutput

� VTTislimitedto0.95VMAX

� VREFtracksVDDQ/2;VREFmustbewithin±0.3VwithrespecttoVDDQ/2duringsupplyramptime;doesnotneedtobesatisfiedwhenrampingpowerdown

� VDDQ≥VREFatalltimes

B. Multiplepowersources:VDD≥VDDL≥VDDQmustbemaintainedduringsupplyvoltageramping,forbothACandDClevels,untilsupplyvoltagerampingcompletes(VDDQcrossesVDD,min).Oncesupplyvoltagerampingiscomplete,Table8(page29)specificationsapply.

� ApplyVDDandVDDLbeforeoratthesametimeasVDDQ;VDD/VDDLvoltageramptimemustbe≤200msfromwhenVDDrampsfrom300mVtoVDD,min

� ApplyVDDQbeforeoratthesametimeasVTT;theVDDQvoltageramptimefromwhenVDD,minisachievedtowhenVDDQ,minisachievedmustbe≤500ms;whileVDDisramping,currentcanbesuppliedfromVDDthroughthedevicetoVDDQ

� VREFmusttrackVDDQ/2;VREFmustbewithin±0.3VwithrespecttoVDDQ/2duringsupplyramptime;VDDQ≥VREFmustbemetatalltimes;doesnotneedtobesatisfiedwhenrampingpowerdown

� ApplyVTT;theVTTvoltageramptimefromwhenVDDQ,minisachievedtowhenVTT,minisachievedmustbenogreaterthan500ms

2. CKErequiresLVCMOSinputlevelspriortostateT0toensureDQsareHigh-Zduringdevicepower-uppriortoVREFbeingstable.AfterstateT0,CKEisrequiredtohaveSSTL_18inputlevels.OnceCKEtransitionstoahighlevel,itmuststayHIGHforthedurationoftheinitializationsequence.

3. Foraminimumof200μsafterstablepowerandclock(CK,CK#),applyNOPorDESELECTcommands,thentakeCKEHIGH.

4. Waitaminimumof400nsthenissueaPRECHARGEALLcommand.

5. IssueaLOADMODEcommandtotheEMR(2).ToissueanEMR(2)command,provideLOWtoBA0,andprovideHIGHtoBA1;setregisterE7to“0”or“1”toselectappropriateselfrefreshrate;remainingEMR(2)bitsmustbe“0”(see“ExtendedModeRegister2(EMR2)”onpage18forallEMR(2)requirements).

6. IssueaLOADMODEcommandtotheEMR(3).ToissueanEMR(3)command,provideHIGHtoBA0andBA1;remainingEMR(3)bitsmustbe“0.”See“ExtendedModeRegister3(EMR3)”onpage19forallEMR(3)requirements.

7. IssueaLOADMODEcommandtotheEMRtoenableDLL.ToissueaDLLENABLEcommand,provideLOWtoBA1andA0;provideHIGHtoBA0;bitsE7,E8,andE9canbesetto“0”or“1;”Microssrecommendssettingthemto“0;”remainingEMRbitsmustbe“0.”See“ExtendedModeRegister(EMR)”onpage14forallEMRrequirements.

8. IssueaLOADMODEcommandtotheMRforDLLRESET.200cyclesofclockinputisrequiredtolocktheDLL.ToissueaDLLRESET,provideHIGHtoA8andprovideLOWtoBA1andBA0;CKEmustbe



10



HIGHtheentiretimetheDLLisresetting;remainingMRbitsmustbe“0.”See“ModeRegister(MR)”onpage10forallMRrequirements.

9. IssuePRECHARGEALLcommand

10. IssuetwoormoreREFRESHcommands.

11. IssueaLOADMODEcommandtotheMRwithLOWtoA8toinitializedeviceoperation(thatis,toprogramoperatingparameterswithoutresettingtheDLL).ToaccesstheMR,setBA0andBA1LOW;remainingMRbitsmustbesettodesiredsettings.See“ModeRegister(MR)”onpage10forallMRrequirements.

12. IssueaLOADMODEcommandtotheEMRtoenableOCDdefaultbysettingbitsE7,E8,andE9to“1,”andthensettingallotherdesiredparameters.ToaccesstheEMR,setBA0HIGHandBA1LOW.See“ExtendedModeRegister(EMR)”onpage14forallEMRrequirements.

13. IssueaLOADMODEcommandtotheEMRtoenableOCDexitbysettingbitsE7,E8,andE9to“0,”andthensettingallotherdesiredparameters.Toaccesstheextendedmoderegisters,EMR,setBA0HIGHandBA1LOWforallEMRrequirements.

14. TheDDR2SDRAMisnowinitializedandreadyfornormaloperation200clockcyclesaftertheDLLRESETatTf0.

15. DMrepresentsUDMandLDM;DQSrepresentsUDQS,UDQS#,LDQS,LDQS#.DQrepresentsDQ[15:0].

16. A10=PRECHARGEALL,CODE=desiredvaluesformoderegisters(bankaddressesarerequiredtobedecoded).

4 Mode Register (MR)

Themode register is used to define the specificmode of operation of theDDR2SDRAM. This definitionincludestheselectionofaburstlength,bursttype,CASlatency,operatingmode,DLLRESET,writerecovery,andpower-downmode,asshown inFigure4 (page11).Contentsof themoderegistercanbealteredbyre-executingtheLOADMODE(LM)command.IftheuserchoosestomodifyonlyasubsetoftheMRvariables,allvariablesmustbeprogrammedwhenthecommandisissued.

TheMRisprogrammedviatheLMcommandandwillretainthestoredinformationuntilitisprogrammedagainoruntilthedevicelosespower(exceptforbitM8,whichisself-clearing).Reprogrammingthemoderegisterwillnotalterthecontentsofthememoryarray,provideditisperformedcorrectly.

TheLMcommandcanonlybeissued(orreissued)whenallbanksareintheprechargedstate(idlestate)andnoburstsareinprogress.ThecontrollermustwaitthespecifiedtimetMRDbeforeinitiatinganysubsequentoperationssuchasanACTIVATEcommand.Violatingeitheroftheserequirementswillresultinanunspecifiedoperation.



11



4 .1 Burst Length

BurstlengthisdefinedbybitsM0–M2,asshowninFigure4.ReadandwriteaccessestotheDDR2SDRAMareburst-oriented,withtheburstlengthbeingprogrammabletoeitherfouroreight.TheburstlengthdeterminesthemaximumnumberofcolumnlocationsthatcanbeaccessedforagivenREADorWRITEcommand.

WhenaREADorWRITEcommandisissued,ablockofcolumnsequaltotheburstlengthiseffectivelyselected.Allaccessesforthatbursttakeplacewithinthisblock,meaningthattheburstwillwrapwithintheblockifaboundaryisreached.TheblockisuniquelyselectedbyA2–AiwhenBL=4andbyA3–AiwhenBL=8(whereAiisthemostsignificantcolumnaddressbitforagivenconfiguration).Theremaining(leastsignificant)addressbit(s)is(are)usedtoselectthestartinglocationwithintheblock.Theprogrammedburstlengthappliestobothreadandwritebursts.

Figure 4: MR Definition

Burst Length

Burst length is defined by bits M0–M2, as shown in Figure 36. Read and write accessesto the DDR2 SDRAM are burst-oriented, with the burst length being programmable toeither four or eight. The burst length determines the maximum number of column loca-tions that can be accessed for a given READ or WRITE command.

When a READ or WRITE command is issued, a block of columns equal to the burstlength is effectively selected. All accesses for that burst take place within this block,meaning that the burst will wrap within the block if a boundary is reached. The block isuniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the mostsignificant column address bit for a given configuration). The remaining (least signifi-cant) address bit(s) is (are) used to select the starting location within the block. The pro-grammed burst length applies to both read and write bursts.

Figure 36: MR Definition

Burst LengthCAS# BTPD

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Mode Register (Mx)

Address Bus

9 7 6 5 4 38 2 1 0

A10A12 A11BA0BA1

101112n

0 0 14

Burst Length

Reserved

Reserved

4

8

Reserved

Reserved

Reserved

Reserved

M0

0

1

0

1

0

1

0

1

M1

0

0

1

1

0

0

1

1

M2

0

0

0

0

1

1

1

1

0

1

Burst Type

Sequential

Interleaved

M3

CAS Latency (CL)

Reserved

Reserved

Reserved

3

4

5

6

7

M4

0

1

0

1

0

1

0

1

M5

0

0

1

1

0

0

1

1

M6

0

0

0

0

1

1

1

1

0

1

Mode

Normal

Test

M7

15

DLL TM

0

1

DLL Reset

No

Yes

M8

Write Recovery

Reserved

2

3

4

5

6

7

8

M9

0

1

0

1

0

1

0

1

M10

0

0

1

1

0

0

1

1

M11

0

0

0

0

1

1

1

1

WR

An2

MR

M14

0

1

0

1

Mode Register Definition

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)


M15

0

0

1

1

M12 0

1

PD Mode

Fast exit(normal)

Slow exit(low power)

Latency

16

BA21

Notes: 1. M16 (BA2) is only applicable for densities 1Gb, reserved for future use, and must beprogrammed to “0.”

2. Mode bits (Mn) with corresponding address balls (An) greater than M12 (A12) are re-served for future use and must be programmed to “0.”

3. Not all listed WR and CL options are supported in any individual speed grade.

2Gb: x4, x8, x16 DDR2 SDRAMMode Register (MR)



Notes:

1. M16(BA2)isonlyapplicablefordensities≥1Gb,reservedforfutureuse,andmustbeprogrammedto“0.”

2. Modebits(Mn)withcorrespondingaddressballs(An)greaterthanM12(A12)arereservedforfutureuseandmustbeprogrammedto“0.”

3. NotalllistedWRandCLoptionsaresupportedinanyindividualspeedgrade.



12



4 .2 Burst Type

Accesseswithinagivenburstmaybeprogrammedtobeeithersequentialor interleaved.ThebursttypeisselectedviabitM3,asshowninFigure4.Theorderingofaccesseswithinaburstisdeterminedbytheburstlength,thebursttype,andthestartingcolumnaddress,asshowninTable4.DDR2SDRAMsupports4-bitburstmodeand8-bitburstmodeonly.For8-bitburstmode,full interleavedaddressorderingissupported;however,sequentialaddressorderingisnibble-based.

Table 4: Burst Definition

Burst LengthStarting Column Address

(A2, A1, A0)

Order of Accesses Within a Burst

Burst Type = Sequential Burst Type = Interleaved

4

0 0 0, 1, 2, 3 0, 1, 2, 3

0 1 1, 2, 3, 0 1, 0, 3, 2

1 0 2, 3, 0, 1 2, 3, 0, 1

1 1 3, 0, 1, 2 3, 2, 1, 0

8

0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7

0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6

0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5

0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4

1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3

1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2

1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1

1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0

4 .3 Operating Mode

ThenormaloperatingmodeisselectedbyissuingacommandwithbitM7setto“0,”andallotherbitssettothedesiredvalues,asshowninFigure4(page11).WhenbitM7is“1,”nootherbitsofthemoderegisterareprogrammed.ProgrammingbitM7to“1”placestheDDR2SDRAMintoatestmodethatisonlyusedbythemanufacturerandshouldnotbeused.NooperationorfunctionalityisguaranteedifM7bitis“1.”



13



4 .4 DLL RESET

DLLRESET isdefinedbybitM8,asshown inFigure4 (page11).ProgrammingbitM8to“1”willactivatetheDLLRESETfunction.BitM8isself-clearing,meaningitreturnsbacktoavalueof“0”aftertheDLLRESETfunctionhasbeenissued.

AnytimetheDLLRESETfunctionisused,200clockcyclesmustoccurbeforeaREADcommandcanbeissuedtoallowtimefortheinternalclocktobesynchronizedwiththeexternalclock.FailingtowaitforsynchronizationtooccurmayresultinaviolationofthetACortDQSCKparameters.

4 .5 Write Recovery

Write recovery (WR) time isdefinedbybitsM9–M11, as shown inFigure4 (page11). TheWR register isusedbytheDDR2SDRAMduringWRITEwithautoprechargeoperation.DuringWRITEwithautoprechargeoperation,theDDR2SDRAMdelaystheinternalautoprechargeoperationbyWRclocks(programmedinbitsM9–M11)fromthelastdataburst.

WRvaluesof2,3,4,5,6,7,or8clocksmaybeusedforprogrammingbitsM9–M11.TheuserisrequiredtoprogramthevalueofWR,whichiscalculatedbydividingtWR(innanoseconds)bytCK(innanoseconds)androundingupanonintegervaluetothenextinteger;WR(cycles)=tWR(ns)/tCK(ns).Reservedstatesshouldnotbeusedasanunknownoperationorincompatibilitywithfutureversionsmayresult.

4 .6 Power-Down Mode

Activepower-down(PD)modeisdefinedbybitM12,asshowninFigure4(page11).PDmodeenablestheusertodeterminetheactivepower-downmode,whichdeterminesperformanceversuspowersavings.PDmodebitM12doesnotapplytoprechargePDmode.

WhenbitM12=0,standardactivePDmode,or“fast-exit”activePDmode,isenabled.ThetXARDparameterisusedforfast-exitactivePDexittiming.TheDLLisexpectedtobeenabledandrunningduringthismode.

WhenbitM12=1,alower-poweractivePDmode,or“slow-exit”activePDmode,isenabled.ThetXARDSparameterisusedforslow-exitactivePDexittiming.TheDLLcanbeenabledbut“frozen”duringactivePDmodebecausetheexit-to-READcommandtimingisrelaxed.ThepowerdifferenceexpectedbetweenIDD3PnormalandIDD3PlowpowermodeisdefinedintheDDR2IDDSpecificationsandConditionstable.

4 .7 CAS Latency (CL)

TheCAS latency (CL) isdefinedbybitsM4–M6,asshown inFigure4 (page11).CL is thedelay, inclockcycles,betweentheregistrationofaREADcommandandtheavailabilityofthefirstbitofoutputdata.TheCLcanbesetto3,4,5,6,or7clocks,dependingonthespeedgradeoptionbeingused.



14



DDR2SDRAMdoesnotsupportanyhalf-clocklatencies.Reservedstatesshouldnotbeusedasanunknownoperationotherwiseincompatibilitywithfutureversionsmayresult.

DDR2SDRAMalsosupportsafeaturecalledpostedCASadditivelatency(AL).ThisfeatureallowstheREADcommandtobe issuedpriorto tRCD(MIN)bydelayingthe internalcommandtotheDDR2SDRAMbyALclocks.TheALfeatureisdescribedinfurtherdetailin“PostedCASAdditiveLatency(AL)”onpage17.

ExamplesofCL=3andCL=4areshowninFigure5;bothassumeAL=0.IfaREADcommandisregisteredatclockedgen,andtheCLismclocks,thedatawillbeavailablenominallycoincidentwithclockedgen+m(thisassumesAL=0).

Figure 5: CL

CAS Latency (CL)

The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 36 (page 78). CL isthe delay, in clock cycles, between the registration of a READ command and the availa-bility of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, dependingon the speed grade option being used.

DDR2 SDRAM does not support any half-clock latencies. Reserved states should not beused as an unknown operation otherwise incompatibility with future versions may re-sult.

DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea-ture allows the READ command to be issued prior to tRCD (MIN) by delaying the inter-nal command to the DDR2 SDRAM by AL clocks. The AL feature is described in furtherdetail in Posted CAS Additive Latency (AL) (page 84).

Examples of CL = 3 and CL = 4 are shown in Figure 37; both assume AL = 0. If a READcommand is registered at clock edge n, and the CL is m clocks, the data will be availablenominally coincident with clock edge n + m (this assumes AL = 0).

Figure 37: CL

DO n + 3

DO n + 2

DO n + 1

CK

CK#

Command

DQ

DQS, DQS#

CL = 3 (AL = 0)

READ

T0 T1 T2

Don’t careTransitioning data

NOP NOP NOP

DO n

T3 T4 T5

NOP NOP

T6

NOP

DO n + 3

DO n + 2

DO n + 1

CK

CK#

Command

DQ

DQS, DQS#

CL = 4 (AL = 0)

READ

T0 T1 T2

NOP NOP NOP

DO n

T3 T4 T5

NOP NOP

T6

NOP

Notes: 1. BL = 4.2. Posted CAS# additive latency (AL) = 0.3. Shown with nominal tAC, tDQSCK, and tDQSQ.

2Gb: x4, x8, x16 DDR2 SDRAMMode Register (MR)



Notes:

1. BL=4.

2. PostedCAS#additivelatency(AL)=0.

3. ShownwithnominaltAC,tDQSCK,andtDQSQ.

5 Extended Mode Register (EMR)

The extended mode register controls functions beyond those controlled by the mode register; theseadditional functions are DLL enable/disable, output drive strength, on-die termination (ODT), postedAL, off-chip driver impedance calibration (OCD), DQS# enable/disable, RDQS/RDQS# enable/disable,and output disable/enable. These functions are controlled via the bits shown in Figure 6. The EMR isprogrammedviatheLMcommandandwillretainthestoredinformationuntil it isprogrammedagainorthe



15



devicelosespower.ReprogrammingtheEMRwillnotalterthecontentsofthememoryarray,providedit isperformedcorrectly.

TheEMRmustbeloadedwhenallbanksareidleandnoburstsareinprogress,andthecontrollermustwaitthespecifiedtimetMRDbeforeinitiatinganysubsequentoperation.Violatingeitheroftheserequirementscouldresultinanunspecifiedoperation.

Figure 6: EMR Definition

Extended Mode Register (EMR)The extended mode register controls functions beyond those controlled by the moderegister; these additional functions are DLL enable/disable, output drive strength, on-die termination (ODT), posted AL, off-chip driver impedance calibration (OCD), DQS#enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These func-tions are controlled via the bits shown in Figure 38. The EMR is programmed via the LMcommand and will retain the stored information until it is programmed again or the de-vice loses power. Reprogramming the EMR will not alter the contents of the memory ar-ray, provided it is performed correctly.

The EMR must be loaded when all banks are idle and no bursts are in progress, and thecontroller must wait the specified time tMRD before initiating any subsequent opera-tion. Violating either of these requirements could result in an unspecified operation.

Figure 38: EMR Definition

DLLPosted CAS# RTTOut

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended mode

register (Ex)

Address bus

9 7 6 5 4 38 2 1 0

A10A12BA0BA1

101112n

0

14

E1

0

1

Output Drive Strength

Full

Reduced

Posted CAS# Additive Latency (AL) 3

0

1

2

3

4

5

6

Reserved

E3

0

1

0

1

0

1

0

1

E4

0

0

1

1

0

0

1

1

E5

0

0

0

0

1

1

1

1

0

1

DLL Enable

Enable (normal)

Disable (test/debug)

E0

15

E11

0

1

RDQS Enable

No

Yes

OCD Program

An2

ODSRTTDQS#

E10

0

1

DQS# Enable

Enable

Disable

RDQS

RTT (Nominal)

RTT disabled

75�150�50�

E2

0

1

0

1

E6

0

0

1

1

0

1

Outputs

Enabled

Disabled

E12

0

1

0

1

Mode Register Set

Mode register (MR)




E15

0

0

1

1

E14

MRS

BA21

160

OCD Operation 4

OCD exit

Reserved

Reserved

Reserved

Enable OCD defaults

E7

0

1

0

0

1

E8

0

0

1

0

1

E9

0

0

0

1

1

Notes: 1. E16 (BA2) is only applicable for densities 1Gb, reserved for future use, and must be pro-grammed to “0.”

2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-served for future use and must be programmed to “0.”

3. Not all listed AL options are supported in any individual speed grade.4. As detailed in the Initialization (page 88) section notes, during initialization of the

OCD operation, all three bits must be set to “1” for the OCD default state, then set to“0” before initialization is finished.

2Gb: x4, x8, x16 DDR2 SDRAMExtended Mode Register (EMR)



Notes:

1. E16(BA2)isonlyapplicablefordensities≥1Gb,reservedforfutureuse,andmustbeprogrammedto“0.”

2. Modebits(En)withcorrespondingaddressballs(An)greaterthanE12(A12)arereservedforfutureuseandmustbeprogrammedto“0.”

3. NotalllistedALoptionsaresupportedinanyindividualspeedgrade.

4. DuringinitializationoftheOCDoperation,allthreebitsmustbesetto“1”fortheOCDdefaultstate,thensetto“0”beforeinitializationisfinished.



16



5 .1 DLL Enable/Disable

TheDLLmaybeenabledordisabledbyprogrammingbitE0duringtheLMcommand,asshowninFigure6(page15). These specifications are applicablewhen theDLL is enabled for normal operation.DLLenableisrequiredduringpower-upinitializationanduponreturningtonormaloperationafterhavingdisabledtheDLLforthepurposeofdebuggingorevaluation.EnablingtheDLLshouldalwaysbefollowedbyresettingtheDLLusingtheLMcommand.

TheDLLisautomaticallydisabledwhenenteringSELFREFRESHoperationandisautomaticallyre-enabledandresetuponexitofSELFREFRESHoperation.

AnytimetheDLLisenabled(andsubsequentlyreset),200clockcyclesmustoccurbeforeaREADcommandcanbe issued toallow time for the internalclock tosynchronizewith theexternalclock.Failing towait forsynchronizationtooccurmayresultinaviolationofthetACortDQSCKparameters.

AnytimetheDLLisdisabledandthedeviceisoperatedbelow25MHz,anyAUTOREFRESHcommandshouldbefollowedbyaPRECHARGEALLcommand.

5 .2 Output Drive Strength

TheoutputdrivestrengthisdefinedbybitE1,asshowninFigure6(page15).ThenormaldrivestrengthforalloutputsisspecifiedtobeSSTL_18.ProgrammingbitE1=0selectsnormal(fullstrength)drivestrengthforalloutputs.Selectingareduceddrivestrengthoption(E1=1)willreducealloutputstoapproximately45to60percentoftheSSTL_18drivestrength.Thisoptionisintendedforthesupportoflighterloadand/orpoint-topointenvironments.

5 .3 DQS# Enable/Disable

TheDQS#ballisenabledbybitE10.WhenE10=0,DQS#isthecomplementofthedifferentialdatastrobepairDQS/DQS#.Whendisabled(E10=1),DQSisusedinasingleendedmodeandtheDQS#ballisdisabled.Whendisabled,DQS#shouldbeleftfloating;however,itmaybetiedtogroundviaa20Ωto10kΩresistor.Thisfunctionisalsousedtoenable/disableRDQS#.IfRDQSisenabled(E11=1)andDQS#isenabled(E10=0),thenbothDQS#andRDQS#willbeenabled.RDQSisnotavailableonthisdevice.

5 .4 Output Enable/Disable

TheOUTPUTENABLEfunction isdefinedbybitE12,asshown inFigure6 (page15).Whenenabled(E12=0),alloutputs(DQ,DQS,DQS#)functionnormally.Whendisabled(E12=1),alloutputs(DQ,DQS,DQS#)aredisabled,thusremovingoutputbuffercurrent.TheoutputdisablefeatureisintendedtobeusedduringIDDcharacterizationofreadcurrent.



17



5 .5 On-Die Termination (ODT)

ODTeffectiveresistance,RTT(EFF),isdefinedbybitsE2andE6oftheEMR,asshowninFigure6(page15).TheODTfeatureisdesignedtoimprovesignalintegrityofthememorychannelbyallowingtheDDR2SDRAMcontrollertoindependentlyturnon/offODTforanyoralldevices.RTTeffectiveresistancevaluesof50Ω,75Ωand510ΩareselectableandapplytoeachDQ,DQS/DQS#,UDQS/UDQS#,LDQS/LDQS#,DM,andUDM/LDMsignals.Bits(E6,E2)determinewhatODTresistanceisenabledbyturningon/off“sw1,”“sw2,”or“sw3.”TheODTeffectiveresistancevalueisselectedbyenablingswitch“sw1,”whichenablesallR1valuesthatare150Ωeach,enablinganeffectiveresistanceof75OΩ(RTT2[EFF]=R2/2).Similarly, if “sw2” isenabled,allR2valuesthatare300Ωeach,enableaneffectiveODTresistanceof150Ω(RTT2[EFF]=R2/2).Switch“sw3”enablesR1valuesof100Ω,enablingeffectiveresistanceof50Ω.Reservedstatesshouldnotbeused,asanunknownoperationorincompatibilitywithfutureversionsmayresult.

TheODTcontrolballisusedtodeterminewhenRTT(EFF)isturnedonandoff,assumingODThasbeenenabledviabitsE2andE6oftheEMR.TheODTfeatureandODTinputballareonlyusedduringactive,activepower-down(bothfast-exitandslow-exitmodes),andprechargepower-downmodesofoperation.

ODTmustbeturnedoffprior toenteringself refreshmode.Duringpower-upand initializationof theDDR2SDRAM,ODTshouldbedisableduntiltheEMRcommandisissued.ThiswillenabletheODTfeature,atwhichpointtheODTballwilldeterminetheRTT(EFF)value.AnytimetheEMRenablestheODTfunction,ODTmaynotbedrivenHIGHuntileightclocksaftertheEMRhasbeenenabled.

5 .6 Off-Chip Driver (OCD) Impedance Calibration

TheOFF-CHIPDRIVERfunctionisanoptionalDDR2JEDECfeaturenotsupportedbyMicrossandtherebymustbesettothedefaultstate.EnablingOCDbeyondthedefaultsettingswillaltertheI/OdrivecharacteristicsandthetimingandoutputI/Ospecificationswillnolongerbevalid.

5 .7 Posted CAS Additive Latency (AL)

PostedCASadditivelatency(AL)issupportedtomakethecommandanddatabusefficientforsustainablebandwidthsinDDR2SDRAM.BitsE3–E5definethevalueofAL,asshowninFigure6(page15).BitsE3–E5allowtheusertoprogramtheDDR2SDRAMwithanALof0,1,2,3,4,5,or6clocks.Reservedstatesshouldnotbeusedasanunknownoperationorincompatibilitywithfutureversionsmayresult.

Inthisoperation,theDDR2SDRAMallowsaREADorWRITEcommandtobeissuedpriortotRCD(MIN)withtherequirementthatAL≤tRCD(MIN).AtypicalapplicationusingthisfeaturewouldsetAL=tRCD(MIN)-1×tCK.TheREADorWRITEcommandisheldforthetimeoftheALbeforeitisissuedinternallytotheDDR2SDRAMdevice.RLiscontrolledbythesumofALandCL;RL=AL+CL.WRITElatency(WL)isequaltoRLminusoneclock;WL=AL+CL-1×tCK.



18



6 Extended Mode Register 2 (EMR2)

Theextendedmoderegister2(EMR2)controlsfunctionsbeyondthosecontrolledbythemoderegister.CurrentlyallbitsinEMR2arereserved,exceptforE7,whichisusedincommercialorhigh-temperatureoperations,asshowninFigure7.TheEMR2isprogrammedviatheLMcommandandwillretainthestoredinformationuntilitisprogrammedagainoruntilthedevicelosespower.ReprogrammingtheEMRwillnotalterthecontentsofthememoryarray,provideditisperformedcorrectly.

BitE7(A7)mustbeprogrammedas“1”toprovideafasterrefreshrateonITandATdevicesifTCexceeds85°C.

EMR2mustbeloadedwhenallbanksareidleandnoburstsareinprogress,andthecontrollermustwaitthespecifiedtimetMRDbefore initiatinganysubsequentoperation.Violatingeitheroftheserequirementscouldresultinanunspecifiedoperation.

Figure 7: EMR2 Definition

Extended Mode Register 2 (EMR2)The extended mode register 2 (EMR2) controls functions beyond those controlled bythe mode register. Currently all bits in EMR2 are reserved, except for E7, which is usedin commercial or high-temperature operations, as shown in Figure 41. The EMR2 is pro-grammed via the LM command and will retain the stored information until it is pro-grammed again or until the device loses power. Reprogramming the EMR will not alterthe contents of the memory array, provided it is performed correctly.

Bit E7 (A7) must be programmed as “1” to provide a faster refresh rate on IT and AT de-vices if TC exceeds 85°C.

EMR2 must be loaded when all banks are idle and no bursts are in progress, and thecontroller must wait the specified time tMRD before initiating any subsequent opera-tion. Violating either of these requirements could result in an unspecified operation.


A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended mode

register (Ex)

Address bus

9 7 6 5 4 38 2 1 0

A10A12 A11BA0BA1

101112n

0

1415

An2

E14

0

1

0

1

Mode Register Set

Mode register (MR)




E15

0

0

1

1

MRS 0 0 0 0 0 SRT 0 0 0 0 0 0 0

BA21

160

E7

0

1

SRT Enable

1X refresh rate (0°C to 85°C)

2X refresh rate (>85°C)

Notes: 1. E16 (BA2) is only applicable for densities 1Gb, reserved for future use, and must be pro-grammed to “0.”


2Gb: x4, x8, x16 DDR2 SDRAMExtended Mode Register 2 (EMR2)



Notes:

1. E16(BA2)isonlyapplicablefordensities≥1Gb,reservedforfutureuse,andmustbeprogrammedto“0.”




19



7 Extended Mode Register 3 (EMR3)

Theextendedmoderegister3(EMR3)controlsfunctionsbeyondthosecontrolledbythemoderegister.CurrentlyallbitsinEMR3arereserved,asshowninFigure8.TheEMR3isprogrammedviatheLMcommandandwillretainthestoredinformationuntilitisprogrammedagainoruntilthedevicelosespower.ReprogrammingtheEMRwillnotalterthecontentsofthememoryarray,provideditisperformedcorrectly.

EMR3mustbeloadedwhenallbanksareidleandnoburstsareinprogress,andthecontrollermustwaitthespecifiedtimetMRDbefore initiatinganysubsequentoperation.Violatingeitheroftheserequirementscouldresultinanunspecifiedoperation.


Extended Mode Register 3 (EMR3)The extended mode register 3 (EMR3) controls functions beyond those controlled bythe mode register. Currently all bits in EMR3 are reserved, as shown in Figure 42. TheEMR3 is programmed via the LM command and will retain the stored information untilit is programmed again or until the device loses power. Reprogramming the EMR willnot alter the contents of the memory array, provided it is performed correctly.

EMR3 must be loaded when all banks are idle and no bursts are in progress, and thecontroller must wait the specified time tMRD before initiating any subsequent opera-tion. Violating either of these requirements could result in an unspecified operation.


E14

0

1

0

1

Mode Register Set

Mode register (MR)




E15

0

0

1

1

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended mode

register (Ex)

Address bus

9 7 6 5 4 38 2 1 0

A10A12 A11BA0BA1

101112n

0

1415

An2

MRS 0 0 0 0 0 0 0 0 0 0 0 0 0

BA21

16

0

Notes: 1. E16 (BA2) is only applicable for densities 1Gb, is reserved for future use, and must beprogrammed to “0.”


2Gb: x4, x8, x16 DDR2 SDRAMExtended Mode Register 3 (EMR3)



Notes:

1. E16(BA2)isonlyapplicablefordensities≥1Gb,isreservedforfutureuse,andmustbeprogrammedto“0.”




20



8 Commands

8 .1 Truth Tables

ThefollowingtablesprovideaquickreferenceofavailableDDR2SDRAMcommands,includingCKEpower-downmodesandbank-to-bankcommands.

Table 5: Truth Table - DDR2 Commands

Notes1-3applytotheentiretable.

Function

CKE

CS# RAS# CAS# WE#BA2– BA0

An–A11 A10 A9–A0 NotesPrevious Cycle

Current Cycle

LOAD MODE H H L L L L BA OP code 4, 6

REFRESH H H L L L H X X X X

SELF REFRESH entry H L L L L H X X X X

SELF REFRESH exit L HH X X X X

X X X 4, 7L H H H

Single bank PRECHARGE H H L L H L BA X L X 6

All banks PRECHARGE H H L L H L X X H X

Bank ACTIVATE H H L L H H BA Row address 4

WRITE H H L H L L BA Column address L Column address 4, 5, 6, 8

WRITE with auto precharge H H L H L L BA Column address H Column address 4, 5, 6, 8

READ H H L H L H BA Column address L Column address 4, 5, 6, 8

READ with auto precharge H H L H L H BA Column address H Column address 4, 5, 6, 8

NO OPERATION H X L H H H X X X X

Device DESELECT H X H X X X X X X X

Power-down entry H LH X X X

X X X X 9L H H H



21



Function

CKE

CS# RAS# CAS# WE#BA2– BA0

An–A11 A10 A9–A0 NotesPrevious Cycle

Current Cycle

Power-down exit L HH X X X

X X X X 9L H H H

Notes:

1. AllDDR2SDRAMcommandsaredefinedbystatesofCS#,RAS#,CAS#,WE#,andCKEattherisingedgeoftheclock.

2. ThestateofODTdoesnotaffectthestatesdescribedinthistable.TheODTfunctionisnotavailableduringselfrefresh.

3. “X”means“HorL”(butadefinedlogiclevel)forvalidIDDmeasurements.

4. BA2isonlyapplicablefordensities≥1Gb.

5. Annisthemostsignificantaddressbitforagivendensityandconfiguration.Somelargeraddressbitsmaybe“Don’tCare”duringcolumnaddressing,dependingondensityandconfiguration.

6. Bankaddresses(BA)determinewhichbankistobeoperatedupon.BAduringaLOADMODEcommandselectswhichmoderegisterisprogrammed.

7. SELFREFRESHexitisasynchronous.

8. BurstreadsorwritesatBL=4cannotbeterminatedorinterrupted.

9. Thepower-downmodedoesnotperformanyREFRESHoperations.Thedurationofpower-downislimitedbytherefreshrequirementsoutlinedintheACparametricsection.

8 .2 DESELECT

TheDESELECTfunction(CS#HIGH)preventsnewcommandsfrombeingexecutedbytheDDR2SDRAM.TheDDR2SDRAMiseffectivelydeselected.Operationsalreadyinprogressarenotaffected.DESELECTisalsoreferredtoasCOMMANDINHIBIT.

8 .3 NO OPERATION (NOP)

TheNOOPERATION(NOP)commandisusedtoinstructtheselectedDDR2SDRAMtoperformaNOP(CS#isLOW;RAS#,CAS#,andWEareHIGH).Thispreventsunwantedcommandsfrombeingregisteredduringidleorwaitstates.Operationsalreadyinprogressarenotaffected.



22



8 .4 LOAD MODE (LM)

Themoderegistersareloadedviabankaddressandaddressinputs.Thebankaddressballsdeterminewhichmoderegisterwillbeprogrammed.See“ModeRegister(MR)”onpage10.TheLMcommandcanonlybeissuedwhenallbanksareidle,andasubsequentexecutablecommandcannotbeissueduntiltMRDismet.

8 .5 ACTIVATE COMMAND

TheACTIVATEcommandisusedtoopen(oractivate)arowinaparticularbankforasubsequentaccess.Thevalueonthebankaddressinputsdeterminesthebank,andtheaddressinputsselecttherow.Thisrowremainsactive(oropen)foraccessesuntilaprechargecommandisissuedtothatbank.Aprechargecommandmustbeissuedbeforeopeningadifferentrowinthesamebank.

8 .6 ACTIVATE OPERATION

BeforeanyREADorWRITEcommandscanbe issued toabankwithin theDDR2SDRAM,a row in thatbankmustbeopened(activated),evenwhenadditivelatencyisused.ThisisaccomplishedviatheACTIVATEcommand,whichselectsboththebankandtherowtobeactivated.

AfterarowisopenedwithanACTIVATEcommand,aREADorWRITEcommandmaybeissuedtothatrowsubjecttothetRCDspecification.tRCD(MIN)shouldbedividedbytheclockperiodandroundeduptothenextwholenumbertodeterminetheearliestclockedgeaftertheACTIVATEcommandonwhichaREADorWRITEcommandcanbeentered.Thesameprocedureisusedtoconvertotherspecificationlimitsfromtimeunitstoclockcycles.Forexample,atRCD(MIN)specificationof20nswitha266MHzclock(tCK=3.75ns)resultsin5.3clocks,roundedupto6.

Figure 9: Example: Meeting tRRD (MIN) and tRCD (MIN)

ACTIVATEBefore any READ or WRITE commands can be issued to a bank within the DDR2SDRAM, a row in that bank must be opened (activated), even when additive latency isused. This is accomplished via the ACTIVATE command, which selects both the bankand the row to be activated.

After a row is opened with an ACTIVATE command, a READ or WRITE command maybe issued to that row subject to the tRCD specification. tRCD (MIN) should be dividedby the clock period and rounded up to the next whole number to determine the earliestclock edge after the ACTIVATE command on which a READ or WRITE command can beentered. The same procedure is used to convert other specification limits from timeunits to clock cycles. For example, a tRCD (MIN) specification of 20ns with a 266 MHzclock (tCK = 3.75ns) results in 5.3 clocks, rounded up to 6. This is shown in Figure 44,which covers any case where 5 < tRCD (MIN)/tCK 6. Figure 44 also shows the case fortRRD where 2 < tRRD (MIN)/tCK 3.

Figure 44: Example: Meeting tRRD (MIN) and tRCD (MIN)

Command

Don’t Care

T1T0 T2 T3 T4 T5 T6 T7

tRRD tRRD

Row Row Col

Bank x Bank y

Row

Bank z Bank y

NOPACT NOP NOPACT NOP NOP RD/WR

tRCD

CK#

Address

Bank address

CK

T8 T9

NOP NOP

A subsequent ACTIVATE command to a different row in the same bank can only be is-sued after the previous active row has been closed (precharged). The minimum time in-terval between successive ACTIVATE commands to the same bank is defined by tRC.

A subsequent ACTIVATE command to another bank can be issued while the first bank isbeing accessed, which results in a reduction of total row-access overhead. The mini-mum time interval between successive ACTIVATE commands to different banks is de-fined by tRRD.

DDR2 devices with 8 banks (1Gb or larger) have an additional requirement: tFAW. Thisrequires no more than four ACTIVATE commands may be issued in any given tFAW(MIN) period, as shown in Figure 45 (page 92).

2Gb: x4, x8, x16 DDR2 SDRAMACTIVATE





23



AsubsequentACTIVATEcommandtoadifferentrowinthesamebankcanonlybeissuedafterthepreviousactiverowhasbeenclosed(precharged).TheminimumtimeintervalbetweensuccessiveACTIVATEcommandstothesamebankisdefinedbytRC.

AsubsequentACTIVATEcommandtoanotherbankcanbe issuedwhile thefirstbank isbeingaccessed,which results ina reductionof total row-accessoverhead.Theminimum time intervalbetweensuccessiveACTIVATEcommandstodifferentbanksisdefinedbytRRD.

DDR2deviceswith8banks(1Gborlarger)haveanadditionalrequirement:tFAW.ThisrequiresnomorethanfourACTIVATEcommandsmaybeissuedinanygiventFAW(MIN)period

8 .7 READ COMMAND

TheREADcommandisusedtoinitiateaburstreadaccesstoanactiverow.Thevalueonthebankaddressinputsdeterminethebank,andtheaddressprovidedonaddressinputsA0–Ai(whereAiisthemostsignificantcolumnaddressbit foragivenconfiguration) selects thestartingcolumn location.Thevalueon inputA10determineswhetherornotautoprecharge isused. If autoprecharge isselected, the rowbeingaccessedwillbeprechargedattheendofthereadburst;ifautoprechargeisnotselected,therowwillremainopenforsubsequentaccesses.

DDR2SDRAMalsosupports theALfeature,whichallowsaREADorWRITEcommandtobe issuedpriortotRCD(MIN)bydelayingtheactualregistrationoftheREAD/WRITEcommandtotheinternaldevicebyALclockcycles.

8 .8 READ OPERATION

READburstsareinitiatedwithaREADcommand.ThestartingcolumnandbankaddressesareprovidedwiththeREADcommand,andautoprechargeiseitherenabledordisabledforthatburstaccess.Ifautoprechargeisenabled,therowbeingaccessedisautomaticallyprechargedatthecompletionoftheburst.Ifautoprechargeisdisabled,therowwillbeleftopenafterthecompletionoftheburst.

DuringREAD bursts, the valid data-out element from the starting column addresswill be available READlatency(RL)clockslater.RLisdefinedasthesumofALandCL:RL=AL+CL.ThevalueforALandCLareprogrammableviatheMRandEMRcommands,respectively.Eachsubsequentdata-outelementwillbevalidnominallyatthenextpositiveornegativeclockedge(atthenextcrossingofCKandCK#).Figure10(page24)showsanexampleofRLbasedondifferentALandCLsettings.

DQS/DQS#isdrivenbytheDDR2SDRAMalongwithoutputdata.TheinitialLOWstateonDQSandtheHIGHstateonDQS#areknownasthereadpreamble(tRPRE).TheLOWstateonDQSandtheHIGHstateonDQS#coincidentwiththelastdata-outelementareknownasthereadpostamble(tRPST).

Uponcompletionofaburst,assumingnoothercommandshavebeeninitiated,theDQwillgoHigh-Z.



24



DatafromanyREADburstmaybeconcatenatedwithdatafromasubsequentREADcommandtoprovideacontinuousflowofdata.Thefirstdataelementfromthenewburstfollowsthelastelementofacompletedburst.ThenewREADcommandshouldbe issuedxcyclesafterthefirstREADcommand,wherexequalsBL/2cycles.

DDR2SDRAMdoesnotallowinterruptingortruncatingofanyREADburstusingBL=4operations.OncetheBL=4READcommandisregistered, itmustbeallowedtocompletetheentireREADburst.However,aREAD (withautoprechargedisabled)usingBL=8operationmaybe interruptedand truncatedonly byanotherREADburstaslongastheinterruptionoccursona4-bitboundaryduetothe4nprefetcharchitectureofDDR2SDRAM.

DatafromanyREADburstmustbecompletedbeforeasubsequentWRITEburstisallowed.

Figure 10: READ LatencyFigure 46: READ Latency

READ NOP NOP NOP NOP NOP

Bank a,Col n

CK

CK#

Command

Address

DQ

DQS, DQS#

DOn

DOn

T0 T1 T2 T3 T4n T5nT4 T5

CK

CK#

Command READ NOP NOP NOP NOP NOP

Address Bank a,Col n

RL = 3 (AL = 0, CL = 3)

DQ

DQS, DQS#

DOn


CK

CK#

Command READ NOP NOP NOP NOP NOP

Address Bank a,Col n

RL = 4 (AL = 0, CL = 4)

DQ

DQS, DQS#


AL = 1 CL = 3

RL = 4 (AL = 1 + CL = 3)

Don’t CareTransitioning Data

Notes: 1. DO n = data-out from column n.2. BL = 4.3. Three subsequent elements of data-out appear in the programmed order following

DO n.4. Shown with nominal tAC, tDQSCK, and tDQSQ.

2Gb: x4, x8, x16 DDR2 SDRAMREAD



Notes:

1. DOn=data-outfromcolumnn.

2. BL=4.

3. Threesubsequentelementsofdata-outappearintheprogrammedorderfollowingDOn.

4. ShownwithnominaltAC,tDQSCK,andtDQSQ.

8 .9 WRITE COMMAND

TheWRITEcommandisusedtoinitiateaburstwriteaccesstoanactiverow.Thevalueonthebankselectinputsselectsthebank,andtheaddressprovidedoninputsA0–Ai(whereAiisthemostsignificantcolumnaddressbitforagivenconfiguration)selectsthestartingcolumnlocation.ThevalueoninputA10determineswhetherornotautoprechargeisused.Ifautoprechargeisselected,therowbeingaccessedwillbeprechargedattheendoftheWRITEburst;ifautoprechargeisnotselected,therowwillremainopenforsubsequentaccesses.

DDR2SDRAMalsosupports theALfeature,whichallowsaREADorWRITEcommandtobe issuedpriortotRCD(MIN)bydelayingtheactualregistrationoftheREAD/WRITEcommandtotheinternaldevicebyALclockcycles.



25



InputdataappearingontheDQiswrittentothememoryarraysubjecttotheDMinputlogiclevelappearingcoincidentwith thedata. IfagivenDMsignal is registeredLOW, thecorrespondingdatawillbewritten tomemory;iftheDMsignalisregisteredHIGH,thecorrespondingdatainputswillbeignored,andaWRITEwillnotbeexecutedtothatbyte/columnlocation.

8 .10 WRITE OPERATION

WRITEburstsare initiatedwithaWRITEcommand.DDR2SDRAMusesWLequal toRLminusoneclockcycle(WL=RL-1CK)(see“READCOMMAND”onpage23).ThestartingcolumnandbankaddressesareprovidedwiththeWRITEcommand,andautoprechargeiseitherenabledordisabledforthataccess.Ifautoprechargeisenabled,therowbeingaccessedisprechargedatthecompletionoftheburst.

DuringWRITEbursts,thefirstvaliddata-inelementwillberegisteredonthefirstrisingedgeofDQSfollowingtheWRITEcommand,andsubsequentdataelementswillberegisteredonsuccessiveedgesofDQS.TheLOWstateonDQSbetweentheWRITEcommandandthefirstrisingedgeisknownasthewritepreamble;theLOWstateonDQSfollowingthelastdata-inelementisknownasthewritepostamble.

The time between theWRITE command and the first risingDQS edge isWL±tDQSS. SubsequentDQSpositiverisingedgesaretimed,relativetotheassociatedclockedge,as±tDQSS.tDQSSisspecifiedwitharelativelywiderange(25%ofoneclockcycle).AlloftheWRITEdiagramsshowthenominalcase,andwherethetwoextremecases(tDQSS[MIN]andtDQSS[MAX])mightnotbeintuitive,theyhavealsobeenincluded.Uponcompletionofaburst,assumingnoothercommandshavebeeninitiated,theDQwillremainHigh-Zandanyadditionalinputdatawillbeignored.

DataforanyWRITEburstmaybeconcatenatedwithasubsequentWRITEcommandtoprovidecontinuousflowofinputdata.Thefirstdataelementfromthenewburstisappliedafterthelastelementofacompletedburst. The new WRITE command should be issued x cycles after the first WRITE command, where xequalsBL/2.

DDR2SDRAMsupportsconcurrentautoprechargeoptions,asshowninTable6(page26).

DDR2SDRAMdoesnotallowinterruptingortruncatinganyWRITEburstusingBL=4operation.OncetheBL=4WRITEcommandisregistered,itmustbeallowedtocompletetheentireWRITEburstcycle.However,aWRITEBL=8operation(withautoprechargedisabled)mightbeinterruptedandtruncatedonlybyanotherWRITEburstas longas the interruptionoccursona4-bitboundarydue to the4n-prefetcharchitectureofDDR2SDRAM.WRITEburstBL=8operationsmaynotbeinterruptedortruncatedwithanycommandexceptanotherWRITEcommand.

DataforanyWRITEburstmaybefollowedbyasubsequentREADcommand.ThenumberofclockcyclesrequiredtomeettWTRiseither2ortWTR/tCK,whicheverisgreater.DataforanyWRITEburstmaybefollowedbyasubsequentPRECHARGEcommand.tWRmustbemet.tWRstartsattheendofthedataburst,regardlessofthedatamaskcondition.



26



Table 6: WRITE Using Concurrent Auto Precharge

From Command (Bank n) To Command (Bank m) Minimum Delay (with Concurrent Auto Precharge) Units

WRITE with auto precharge

READ or READ with auto precharge (CL - 1) + (BL/2) + tWTR

tCKWRITE or WRITE with auto precharge (BL/2)

PRECHARGE or ACTIVATE 1

Figure 11: Write BurstFigure 58: Write Burst

DQS, DQS#

tDQSS (MAX)

tDQSS (NOM)

tDQSS (MIN)

DM

DQ

CK

CK#

Command WRITE NOP NOP

Address Bank a,Col b

NOP NOP

T0 T1 T2 T3T2n T4T3n

DQS, DQS#

5

DM

DQ

DQS, DQS#

DM

DQ DIb

DIb

DIb

Don’t CareTransitioning Data

tDQSS5

WL ± tDQSS

WL - tDQSS tDQSS5

WL + tDQSS

Notes: 1. Subsequent rising DQS signals must align to the clock within tDQSS.2. DI b = data-in for column b.3. Three subsequent elements of data-in are applied in the programmed order following

DI b.4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.5. A10 is LOW with the WRITE command (auto precharge is disabled).

2Gb: x4, x8, x16 DDR2 SDRAMWRITE



Notes:

1. SubsequentrisingDQSsignalsmustaligntotheclockwithintDQSS.

2. DIb=data-inforcolumnb.

3. Threesubsequentelementsofdata-inareappliedintheprogrammedorderfollowingDIb.

4. ShownwithBL=4,AL=0,CL=3;thus,WL=2.

5. A10isLOWwiththeWRITEcommand(autoprechargeisdisabled).

8 .11 PRECHARGE COMMAND

ThePRECHARGEcommandisusedtodeactivatetheopenrowinaparticularbankortheopenrowinallbanks.Thebank(s)willbeavailableforasubsequentrowactivationaspecifiedtime(tRP)afterthePRECHARGEcommandisissued,exceptinthecaseofconcurrentautoprecharge,whereaREADorWRITEcommandtoadifferentbankisallowedaslongasitdoesnotinterruptthedatatransferinthecurrentbankanddoesnotviolateanyother timingparameters.Afterabankhasbeenprecharged, it is in the idlestateandmustbeactivatedpriortoanyREADorWRITEcommandsbeingissuedtothatbank.APRECHARGEcommandis



27



allowedifthereisnoopenrowinthatbank(idlestate)orifthepreviouslyopenrowisalreadyintheprocessofprecharging.However,theprechargeperiodwillbedeterminedbythelastPRECHARGEcommandissuedtothebank.

8 .12 PRECHARGE OPERATION

PrechargecanbeinitiatedbyeitheramanualPRECHARGEcommandorbyanautoprechargeinconjunctionwitheitheraREADorWRITEcommand.Prechargewilldeactivatetheopenrowinaparticularbankortheopenrowinallbanks.ThePRECHARGEoperationisshowninthepreviousREADandWRITEoperationsections.

During amanual PRECHARGE command, the A10 input determineswhether one or all banks are to beprecharged.Inthecasewhereonlyonebankistobeprecharged,bankaddressinputsdeterminethebanktobeprecharged.Whenallbanksaretobeprecharged,thebankaddressinputsaretreatedas“Don’tCare.”

Onceabankhasbeenprecharged,itisintheidlestateandmustbeactivatedpriortoanyREADorWRITEcommandsbeing issued to that bank.When a single-bankPRECHARGEcommand is issued, tRP timingapplies.WhenthePRECHARGE(ALL)commandisissued,tRPAtimingapplies,regardlessofthenumberofbanksopened.

8 .13 REFRESH COMMAND

REFRESH isusedduringnormaloperationof theDDR2SDRAMand is analogous toCAS#-before-RAS#(CBR)REFRESH.AllbanksmustbeintheidlemodepriortoissuingaREFRESHcommand.Thiscommandisnonpersistent,soitmustbeissuedeachtimearefreshisrequired.Theaddressingisgeneratedbytheinternalrefreshcontroller.Thismakestheaddressbitsa“Don’tCare”duringaREFRESHcommand.

Thecommercial temperatureDDR2SDRAM requiresREFRESHcycles at an average interval of 7.8125μs(MAX)andallrowsinallbanksmustberefreshedatleastonceevery64ms.TherefreshperiodbeginswhentheREFRESHcommandisregisteredandendstRFC(MIN)later.Theaverageintervalmustbereducedto3.9μs(MAX)whenTCexceeds85°C.

8 .14 SELF REFRESH COMMAND

TheSELFREFRESHcommandcanbeusedtoretaindataintheDDR2SDRAM,eveniftherestofthesystemispowereddown.Whenintheselfrefreshmode,theDDR2SDRAMretainsdatawithoutexternalclocking.Allpowersupply inputs(includingVREF)mustbemaintainedatvalid levelsuponentry/exitandduringSELFREFRESHoperation.

TheSELFREFRESHcommandisinitiatedwhenCKEisLOW.ThedifferentialclockshouldremainstableandmeettCKEspecificationsatleast1×tCKafterenteringselfrefreshmode.Theprocedureforexitingselfrefreshrequiresasequenceofcommands.First,thedifferentialclockmustbestableandmeettCKspecificationsat



28



least1×tCKpriortoCKEgoingbacktoHIGH.OnceCKEisHIGH(tCKE[MIN]hasbeensatisfiedwiththreeclockregistrations),theDDR2SDRAMmusthaveNOPorDESELECTcommandsissuedfortXSNR.AsimplealgorithmformeetingbothrefreshandDLLrequirementsisusedtoapplyNOPorDESELECTcommandsfor200clockcyclesbeforeapplyinganyothercommand.

9 Electrical Specifications

9 .1 Absolute Ratings

Stressesgreaterthanthoselistedmaycausepermanentdamagetothedevice.Thisisastressratingonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsoutsidethoseindicatedintheoperationalsectionsof this specification isnot implied.Exposure toabsolutemaximum ratingconditions forextendedperiodsmayaffectreliability.

Table 7: Absolute Maximum DC Ratings

Parameter Symbol Min Max Units Notes

VDD supply voltage relative to VSS VDD -1 .0 2 .3 V 1

VDDQ supply voltage relative to VSSQ VDDQ -0 .5 2 .3 V 1, 2

VDDL supply voltage relative to VSSL VDDL -0 .5 2 .3 V 1

Voltage on any ball relative to VSS VIN, VOUT -0 .5 2 .3 V 3

Input leakage current; any input 0V ≤ VIN ≤ VDD; all other balls not under test = 0V) II -5 5 μA

Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ and ODT disabled IOZ -5 5 μA

VREF leakage current; VREF = valid VREF level IVREF -2 2 μA

Notes:

1. VDD,VDDQ,andVDDLmustbewithin300mVofeachotheratalltimes;thisisnotrequiredwhenpowerisrampingdown.

2. VREF≤0.6xVDDQ;however,VREFmaybe≥VDDQprovidedthatVREF≤300mV.

3. VoltageonanyI/OmaynotexceedvoltageonVDDQ.



29



9.1.1 AC and DC Operating Conditions

Table 8: Recommended DC Operating Conditions (SSTL_18)

AllvoltagesreferencedtoVSS.

Parameter Symbol Min Nom Max Units Notes

Supply voltage VDD 1 .7 1 .8 1 .9 V 1, 2

VDDL supply voltage VDDL 1 .7 1 .8 1 .9 V 2, 3

I/O supply voltage VDDQ 1 .7 1 .8 1 .9 V 2, 3

I/O reference voltage VREF(DC) 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V 4

I/O termination voltage (system) VTT VREF(DC) - 40 VREF(DC) VREF(DC) + 40 mV 5

Notes:

1. VDDandVDDQmusttrackeachother.VDDQmustbe≤VDD.

2. VSSQ=VSSL=VSS.

3. VDDQtrackswithVDD;VDDLtrackswithVDD.

4. VREFisexpectedtoequalVDDQ/2ofthetransmittingdeviceandtotrackvariationsintheDClevelofthesame.Peak-to-peaknoise(noncommonmode)onVREFmaynotexceed±1percentoftheDCvalue.Peak-to-peakACnoiseonVREFmaynotexceed±2percentofVREF(DC).ThismeasurementistobetakenatthenearestVREFbypasscapacitor.

5. VTTisnotapplieddirectlytothedevice.VTTisasystemsupplyforsignalterminationresistors,isexpectedtobesetequaltoVREF,andmusttrackvariationsintheDClevelofVREF.

9 .2 Temperature and Thermal Impedance

It is imperative that theDDR2SDRAMdevice’s temperaturespecifications,shown inTable9 (page30),bemaintained inordertoensurethe junctiontemperature is intheproperoperatingrangetomeetdatasheetspecifications.Animportantstepinmaintainingtheproperjunctiontemperatureisusingthedevice’sthermalimpedances correctly. The thermal impedances are listed in Table 10 (page 31) for the applicable andavailabledierevisionandpackages.



30



Table 9: Temperature Limits


Storage temperature TSTG -55 150 °C 1

Operating temperature – commercial TC 0 85 °C 2, 3

Operating temperature – industrialTC -40 95 °C 2, 3, 4

TAMB -40 85 °C 4, 5

Notes:

1. MAXstoragecasetemperatureTSTGismeasuredinthecenterofthepackage,asshowninFigure12.

2. MAXoperatingcasetemperatureTCismeasuredinthecenterofthepackage,asshowninFigure12.

3. DevicefunctionalityisnotguaranteedifthedeviceexceedsmaximumTCduringoperation.

4. Bothtemperaturespecificationsmustbesatisfied.

5. Operatingambienttemperaturesurroundingthepackage.

Figure 12: Example Temperature Test Point Location

Table 6: Temperature Limits


Storage temperature TSTG –55 150 °C 1

Operating temperature – commercial TC 0 85 °C 2, 3

Operating temperature – industrial TC –40 95 °C 2, 3, 4

TAMB –40 85 °C 4, 5

Notes: 1. MAX storage case temperature TSTG is measured in the center of the package, as shownin Figure 12. This case temperature limit is allowed to be exceeded briefly during pack-age reflow, as noted in Micron technical note TN-00-15, “Recommended Soldering Pa-rameters.”

2. MAX operating case temperature TC is measured in the center of the package, as shownin Figure 12.

3. Device functionality is not guaranteed if the device exceeds maximum TC during opera-tion.

4. Both temperature specifications must be satisfied.5. Operating ambient temperature surrounding the package.

Figure 12: Example Temperature Test Point Location

Width (W)0.5 (W)

Length (L)

0.5 (L)

Test point

Lmm x Wmm FBGA

2Gb: x4, x8, x16 DDR2 SDRAMElectrical Specifications – Absolute Ratings





31



Table 10: Thermal Impedance

Package SubstrateJA (°C/W)

Airflow = 0m/sJA (°C/W)

Airflow = 1m/sJA (°C/W)

Airflow = 2m/sJB (°C/W) JC (°C/W)

84-ball2-layer 60 .0 43 .5 37 .9 26 .0

4 .14-layer 43 .2 34 .7 31 .5 25 .5

Note:

1. Thermalresistancedataisbasedonanumberofsamplesfrommultiplelotsandshouldbeviewedasatypicalnumber.

9 .3 FBGA Package Capacitance

Table 11: Input Capacitance


Input capacitance: CK, CK# CCK 1 .0 2 .0 pF 1

Delta input capacitance: CK, CK# CDCK – 0 .25 pF 2, 3

Input capacitance: BA[2:0], A[14:0] (A[13:0] on x16), CS#, RAS#, CAS#, WE#, CKE, ODT CI 1 .0 2 .0 pF 1

Delta input capacitance: Address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE, ODT CDI – 0 .25 pF 2, 3

Input/output capacitance: DQ, DQS, DM, NF CIO 2 .5 4 .0 pF 1, 4

Delta input/output capacitance: DQ, DQS, DM, NF CDIO – 0 .5 pF 2, 3

Notes:

1. Thisparameterissampled.VDD=1.8V±0.1V,VDDQ=1.8V±0.1V,VREF=VSS,f=100MHz,TC=25°C,VOUT(DC)=VDDQ/2,VOUT(peak-to-peak)=0.1V.DMinputisgroupedwithI/Oballs,reflectingthefactthattheyarematchedinloading.

2. Thecapacitanceperballgroupwillnotdifferbymorethanthismaximumamountforanygivendevice.

3. ΔCarenotpass/failparameters;theyaretargets.

4. ReduceMAXlimitby0.25pFforspeeddevices.



32



9 .4 IDD Parameters

Table 12: IDD Parameters

Parameter/Condition Symbol -25E Units

Operating one bank active-precharge current: tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching

IDD0 90 mA

Operating one bank active-read-precharge current: Iout = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W

IDD1 105 mA

Precharge power-down current: All banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating

IDD2P 12 mA

Precharge quiet standby current: All banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating

IDD2Q 45 mA

Precharge standby current: All banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching

IDD2N 50 mA

Active power-down current: All banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating

IDD3P(FAST) 25mA

IDD3P(SLOW) 14

Active standby current: All banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching

IDD3N 50 mA

Operating burst write current: All banks open, continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching

IDD4W 190 mA

Operating burst read current: All banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching

IDD4R 190 mA

Burst refresh current: tCK = tCK (IDD); refresh command at every tRFC (IDD) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching

IDD5 170 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating

IDD6 12mA

IDD6L 8

Operating bank interleave read current: All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching.

IDD7 280 mA

Notes:

1. IDDspecificationsaretestedafterthedeviceisproperlyinitialized.0°C≤TC≤+85°C.

2. VDD=+1.8V±0.1V,VDDQ=+1.8V±0.1V,VDDL=+1.8V±0.1V,VREF=VDDQ/2.

3. IDDparametersarespecifiedwithODTdisabled.

4. DatabusconsistsofDQ,DM,DQS,DQS#,LDQS,LDQS#,UDQS,andUDQS#.IDDvaluesmustbemetwithallcombinationsofEMRbits10and11.



33



5. IDD1,IDD4R,andIDD7requireA12inEMR1tobeenabledduringtesting.

6. ThefollowingIDDvaluesmustbederated(IDDlimitsincrease)onIT-optiondeviceswhenoperatedoutsideoftherange0°C≤TC≤+85°C:

• WhenTC≤0°CIDD2PandIDD3P(SLOW)mustbederatedby4%;IDD4RandIDD5Wmustbederatedby2%;andIDD6andIDD7mustbederatedby7%.

• WhenTC≥85°CIDD0,IDD1,IDD2N,IDD2Q,IDD3N,IDD3P(FAST),IDD4R,IDD4W,andIDD5Wmustbederatedby2%;IDD2Pmustbederatedby20%;IDD3Pslowmustbederatedby30%;andIDD6mustbederatedby80%(IDD6willincreasebythisamountifTC<85°Candthe2xrefreshoptionisstillenabled).

9 .5 ACTimingOperatingSpecifications

Table 13: AC Operating Specifications and Conditions

Notallspeedgradeslistedmaybesupportedforthisdevice;refertothetitlepageforspeedssupported;Notes1-5applytotheentiretable;VDDQ=1.8V±0.1V,VDD=1.8V±0.1V

AC Characteristics -25EUnits

Parameter Symbol Min Max

Clock

Clock cycle time

CL = 6 tCK (avg) 2 .5 8 .0ns

CL = 5 tCK (avg) 2 .5 8 .0

CK high-level width tCH (avg) 0 .48 0 .52 tCK

CK low-level width tCL (avg) 0 .48 0 .52 tCK

Half clock period tHP MIN = lesser of tCH and tCL MAX = n/a ps

Absolute tCK tCK (abs)MIN = tCK (AVG) MIN + tJITper (MIN)

MAX = tCK (AVG) MAX + tJITper (MAX)ps

Absolute CK high-level width tCH (abs)MIN = tCK (AVG) MIN × tCH (AVG) MIN + tJITdty (MIN)

MAX = tCK (AVG) MAX × tCH (AVG) MAX + tJITdty (MAX)ps

Absolute CK low-level width tCL (abs)MIN = tCK (AVG) MIN × tCL (AVG) MIN + tJITdty (MIN)

MAX = tCK (AVG) MAX × tCL (AVG) MAX + tJITdty (MAX)ps

Clock Jitter

Period jitter tJITper -100 100 ps

Half period tJITdty -100 100 ps

Cycle to cycle tJITcc 200 ps

Cumulative error, 2 cycles tERR2per -150 150 ps



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Cumulative error, 6–10 cycles tERR6-10per -300 300 ps

Cumulative error, 11–50 cycles tERR11-50per -450 450 ps

Data Strobe Out

DQS output access time from CK/CK# tDQSCK -350 350 ps

DQS read preamble tRPRE MIN = 0.9 × tCK; MAX = 1.1 × tCK tCK

DQS read postamble tRPST MIN = 0.4 × tCK; MAX = 0.6 × tCK tCK

CK/CK# to DQS Low-Z tLZ1 MIN = tAC (MIN); MAX = tAC (MAX) ps

Data Strobe In

DQS rising edge to CK rising edge tDQSS MIN = –0.25 × tCK; MAX = 0.25 × tCK tCK

DQS input-high pulse width tDQSH MIN = 0.35 × tCK; MAX = n/a tCK

DQS input-low pulse width tDQSL MIN = 0.35 × tCK; MAX = n/a tCK

DQS falling to CK rising: setup time tDSS MIN = 0.2 × tCK; MAX = n/a tCK

DQS falling from CK rising: hold time tDSH MIN = 0.2 × tCK; MAX = n/a tCK

Write preamble setup time tWPRES MIN = 0; MAX = n/a ps

DQS write preamble tWPRE MIN = 0.35 × tCK; MAX = n/a tCK

DQS write postamble tWPST MIN = 0.4 × tCK; MAX = 0.6 × tCK tCK

WRITE command to first DQS transition – MIN = WL - tDQSS; MAX = WL + tDQSS tCK

Data Out

DQ output access time from CK/CK# tAC -400 400 ps

DQS–DQ skew, DQS to last DQ valid, per group, per access

tDQSQ – 200 ps

DQ hold from next DQS strobe tQHS – 300 ps

DQ–DQS hold, DQS to first DQ not valid tQH MIN = tHP - tQHS; MAX = n/a ps

CK/CK# to DQ, DQS High-Z tHZ MIN = n/a; MAX = tAC (MAX) ps

CK/CK# to DQ Low-Z tLZ2 MIN = 2 × tAC (MIN); MAX = tAC (MAX) ps

Data valid output window DVW MIN = tQH - tDQSQ; MAX = n/a ns



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Data In

DQ and DM input setup time to DQS tDSb 50 – ps

DQ and DM input hold time to DQS tDHb 125 – ps

DQ and DM input setup time to DQS tDSa 250 – ps

DQ and DM input hold time to DQS tDHa 250 – ps

DQ and DM input pulse width tDIPW MIN = 0.35 × tCK; MAX = n/a tCK

Command and Address

Input setup time tISb 175 – ps

Input hold time tIHb 250 – ps

Input setup time tISa 375 – ps

Input hold time tIHa 375 – ps

Input pulse width tIPW 0 .6 – tCK

ACTIVATE-to- ACTIVATE delay, same bank tRC 55 – ns

ACTIVATE-to-READ or WRITE delay tRCD 12 .5 – ns

ACTIVATE-to-PRECHARGE delay tRAS 40 70K ns

PRECHARGE period tRP 12 .5 – ns

PRECHARGE ALL period <1Gb<1Gb tRPA 12 .5 – ns

≥1Gb tRPA 15 – ns

ACTIVATE-to-ACTIVATE delay different bank tRRD 10 – ns

4-bank activate period (≥1Gb) tFAW 45 – ns

Internal READ-to-PRECHARGE delay tRTP 7 .5 – ns

CAS#-to-CAS# delay tCCD 2 – tCK

Write recovery time tWR 15 – ns

Write AP recovery + precharge time tDAL tWR + tRP – ns

Internal WRITE-to-READ delay tWTR 7 .5 – ns

LOAD MODE cycle time tMRD 2 - tCK



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Refresh

REFRESH- to- ACTIVATE or to -REFRESH interval tRFC 195 – –

Average periodic refresh (commercial) tREFI – 7 .8 μs

Average periodic refresh (industrial) tREFIIT – 3 .9 μs

Average periodic refresh (automotive) tREFIAT – 3 .9 μs

CKE LOW to CK, CK# uncertainty tDELAY MIN limit = tIS + tCK + tIH; MAX limit = n/a ns

Self Refresh

Exit SELF REFRESH to onREAD command tXSNR MIN limit = tRFC (MIN) + 10; MAX limit = n/a ns

Exit SELF REFRESH to READ command tXSRD MIN limit = 200; MAX limit = n/a tCK

Exit SELF REFRESH timing reference tISXR MIN limit = tIS; MAX limit = n/a ps

Power Down

Exit active power- down to READ command

MR12 = 0tXARD

2 – tCK

MR12 = 1 8 - AL – tCK

Exit precharge power-down and active power-down to any nonREAD command

tXP 2 – tCK

CKE MIN HIGH/LOW time tCKE MIN = 3; MAX = n/a tCK

ODT

ODT to power- down entry latency tANPD 3 – tCK

ODT power-down exit latency tAXPD 8 – tCK

ODT turn-on delay tAOND 2 tCK

ODT turn-off delay tAOFD 2 .5 tCK

ODT turn-on tAON tAC (MIN) tAC (MAX) + 600 ps

ODT turn-off tAOF tAC (MIN) tAC (MAX) + 600 ps

ODT turn-on (power-down mode) tAONPD tAC (MIN) + 2000 2 × tCK + tAC (MAX) + 1000 ps

ODT turn-off (power-down mode) tAOFPD tAC (MIN) + 2000 2 .5 × tCK + tAC (MAX) + 1000 ps

ODT enable from MRS command tMOD 12 N/A ns



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10 Package

Figure 13: 84-Ball FBGA Package (9mm x 12.5mm) – x16

Ball A1 ID

Seatingplane

0.8 ±0.05

0.12 A A

12.5 ±0.1

0.8 TYP

1.2 MAX

11.2 CTR

Ball A1 ID

0.8 TYP

9 ±0.1

0.25 MIN6.4 CTR

9 8 7 3 2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

1.8 CTRNonconductive overmold

0.155

Notes: 1. All dimensions are in millimeters.



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11 Ordering Information

Table 14: Ordering Information

Part Number Data Rate (Mbps) Device Grade

MYX4DDR2128M16PK-25EIT 800 Industrial

MYX4DDR2128M16PK-25E 800 Commercial

PleasecontactaMicrosssalesrepresentativeforIBISorthermalmodelsatsales@micross.com.



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Document Title

128M16 DDR2 SDRAM - 84-Ball FBGA Package (9mm x 12.5mm) – x16

Revision History

Revision # History Release Date Status

1 .0 Initial Release September 2014 Preliminary

1 .1 Page 1: Title changed from “125M16 DDR2 SDRAM - 84 PBGA” to “2 GB - 128M x 16 DDR2 SDRAM”

October 3, 2014 Preliminary

Page 1: Removed “-x16” from “FBGA package (Sn63/Pb37) in Options/Markings blue box

Page 1 (blue box): Changed “Marking” to “Code”

Page 1 (Table 1 & blue box); Page 38 (Table 14): Removed -25 speed grade; added -187E

Page 38 (Table 14): Removed “CL” column

1 .2 Added ECN # October 20, 2014 Preliminary

1 .3 Page 32 (Table 12): Added column for -187E October 21, 2014 Preliminary

Page 33 (Table 13): Removed column for -25; Added column for -187E; Added CL = 7 Clock Cycle Time parameter

Page 38 (Table 14): Changed part numbers with -187IT and -187 to -187EIT and -187E

1 .4 Removed -25E and -3 speed grades October 31, 2014 Preliminary

1 .5 Removed -187E speed grade; added -25E speed grade March 27, 2015 Preliminary

Page 1 (Table 1): Changed tRC (ns) from 54 to 55

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