2_Computers.ppt

1

Assignment 1

2

Heart Murmurs

3

Heart Operation

4

Heart Cycle

5

Phonogram

http://www.wilkes.med.ucla.edu/intro.html

6

UNIX

7

UNIX Concept?

User

Users

Hardware

UNIX kernel

Shell

She

ll

Shell

Shell

8

UNIX Concept

System Calls

vi

UNIX kernel

Hardware

open() close()

read()

write()

Chm

od()

ksh

csh

a.out cpp

9

UNIX Structure

I/O Manager

I/O Manager

Central KernelCentral Kernel

File Manager

File Manager

System Calls

Network ManagerNetwork Manager

Buffer CacheBuffer Cache

HardwareHardware

10

UNIX Services

I/O Manager

I/O Manager

Central KernelCentral Kernel

File Manager

File Manager

System Calls

Network ManagerNetwork Manager

Buffer CacheBuffer Cache

HardwareHardware

Process Management

Virtual Memory Machine

Communications

Programmatic InterfaceMemory

Management

File System Management

System Initialization

Fault, trap, interruption,

exception handling

I/O Device Drivers

11

Kernel Source Code

• usr/src/uts/machine (eg. MIPS)

../boot boot

../os process management code

../sys C-language include files

../fs file management systems

../io I/O management subsystem

12

Kernel Source Code

• usr/src/uts/machine

../disp low level process switching

../exec reading and starting executables

.. /vm memory, virtual memory

../debug kernel debugging system

../ml machine-dependent code

../master.d describe system configuration

13

UNIX Look-alikes

• AIX IBM

• HP-UX Hewlett-Packard

• OSF/1 Open Software Foundation

• Ultrix DEC

• IRIX SGI

• UTS Amdahl

• Solaris Sun

14

Computer System Structures

Chapter 2

15

Computer System

Disk Controller

Disk Controller

System Bus

Display

CPU

VideoVideo Printer Controller

Printer Controller

Memory ControllerMemory

Controller

Keypad

ExpansionExpansion

RAM

16

PC Computer

17

Bootstrap• Stored in ROM (read-only memory)

• Initializes CPU registers, memory, controllers

• Loads operating system

18

System Operation• I/O devices, CPU execute concurrently

• CPU generally controls data on bus

• Device controller for each device type

• Local buffer for each device controller

• I/O is from device to local controller

• Device controller informs CPU that it has finished its operation, by an Interrupt

19

Computer System

Disk Controller

Disk Controller

System Bus

Display

CPU

VideoVideo Printer Controller

Printer Controller


Controller

Keypad

ExpansionExpansion

CPU-contro

lled

One per

device

type

Concurrent execution Local b

ufferI/O

Flow

Interrupt

20

Interrupts

Operating System

Operating System

ISRISR

Device Controller

Device Controller

• Hardware interrupt

21

Interrupts

Operating System

Operating System

ISRISR

• Software interrupt

User Code

• System call

• Error traps

22

Interrupts

Operating System

Operating System

User CodeUser Code

Interrupt HandlerInterrupt Handler

Interrupt Vector

Interrupt Vector

Pr 1Pr 1

… …

Pr nPr n

Pr n+1Pr n+1

Pr 0Pr 0

System Stack

User Code

• Return address stored on system stack

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“Data In” Interrupt Sequence

1. Save address of interrupted instruction

2. Transfer control to Interrupt Service Routine

3. ISR saves contents of required registers

4. ISR checks for error conditions on data input

5. ISR takes input, store in buffer

6. ISR sets flag to indicate new data

7. ISR restores contents of saved registers

8. Control back to interrupted instruction

24

Read Request

Disk Controller

Disk ControllerCPU


Controller

Synchronous I/O:

• CPU requests read, waits

• Disk controller sends interrupt when done

Loop: jmp Loop

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Read Request

Disk Controller

Disk ControllerCPU


Controller

Asynchronous I/O:

• CPU requests read, does something else

• Disk controller sends interrupt when done

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Task 1Task 1

File: zzz File: zzz

Op: Write Op: Write

Device Status Queued

Keyboard Idle 0

Mouse Idle 0

Disk Busy 2

Printer Busy 1

Device Status Table

Task 1Task 1

File: xxx File: xxx

Op: Read Op: Read

Add: 43026 Add: 43026

Len: 20000 Len: 20000

Task 2Task 2

File: yyy File: yyy

Op: Write Op: Write

Add: 03458 Add: 03458

Len: 500 Len: 500

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Direct Memory Access (DMA)

Disk Controller

Disk ControllerCPU


Controller

• CPU initiates, does something else

• One interrupt per block of data

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Data Storage

Disk Controller

Disk ControllerCPU


Controller

RegistersRegisters

CacheCache

DRAMDRAM Magnetic DiskMagnetic Disk

Magnetic TapeMagnetic Tape

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Operand 1Operand 1

… …

Operand nOperand n

Operand n+1Operand n+1

von Neuman Architecture

Instruction Register

AccumulatorAccumulator

MQ RegisterMQ Register

Register nRegister n

Register n+1Register n+1

Processor

InstructionInstruction

Random Access Memory

… …

… …

… …

… …

Other Registers

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I/O Architecture

Printer Controller

Printer Controller

CPU MemoryMemoryMemory-mapped I/O

Mapped to device controller registers

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I/O Architecture

Printer Controller

Printer ControllerCPU

Data Register

Data Register

Control RegisterControl Register

1

2

1. Load data byte

2. Set ready bit

3

4

I/O Port

3. Data byte to device

4. Clear ready bit

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I/O Architecture

Printer Controller


Data Register

Data Register


6

5

5. Poll for cleared bit

6. Send next byte

I/O Port

Programmed I/O

33

I/O Architecture

Printer Controller


Data Register

Data Register


6

5

5. Interrupt CPU

6. Send next byte

I/O Port

Interrupt-driven I/O

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Magnetic Disks

35

Storage Hierarchy

RegistersRegisters

CacheCache

Main MemoryMain Memory

Electronic DiskElectronic Disk

Magnetic DiskMagnetic Disk

Optical DiskOptical Disk

Magnetic TapesMagnetic Tapes

volatile

nonvolatile

$

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Instruction Cache

Instruction Register

Instruct 1Instruct 1

… …

Instruct nInstruct n

Instruct n+1Instruct n+1

… …

… …

… …

… …

Main Memory

InstructionInstruction

Instruction Cache

37

Memory as Disk Cache

Instruct 1Instruct 1

… …

Instruct nInstruct n

Instruct n+1Instruct n+1

… …

… …

… …

… …

Main Memory

Instruction Cache Hard Drive

38

Disk Backup System

OO OO

OO OO

OO OO

OO OO

Tape Jukebox

Hard Drive

Weekly rotation

Off-site

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Cache Coherency

CPU2CPU2

CacheCache

CPU3CPU3

CacheCache

CPU1CPU1

CacheCache

CPU4CPU4

CacheCache

… …

… …

… …

Main Memory

A’

A

A

A

A

40

Hardware Protection

Operating System

Operating System

Job 1Job 1

Job 2Job 2

Job 3Job 3

Job 4Job 4

• Illegal instructions

• Address out of range

Trap and terminate job

41

Operating Modes

Operating System

Operating System

Job 1Job 1

Job 2Job 2

Job 3Job 3

Job 4Job 4

• Monitor Mode– System mode– Supervisor mode– Privileged mode– Privileged instructions

• User mode

Mode bit

Hardware

42

I/O Protection

User CodeUser Code Operating System

Operating System

I/O DeviceI/O Device

43

Memory Protection

User CodeUser Code Operating System

Operating System

Interrupt Service

Routines

Interrupt Service

Routines

Interrupt Vector

Interrupt Vector

44

Memory Protection

User CodeUser Code

Base Register

Base Register

LimitRegister

LimitRegister

45

CPU Protection

User CodeUser Code

CPUCPU

Countdown Timer

Countdown Timer

Time• Interrupt long jobs

46

CPU Protection

User CodeUser Code

CPUCPU

Countdown Timer

Countdown Timer

Time• Time slices for time sharing

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Local Area Networks

• Bluetooth 1 Mb/s

• Ethernet– 10BaseT– 100BaseT– 100 Gb/s

• Twisted pair

• Fiber optic

48

Wide Area Networks

RR

RR

RR

CPCP

RR

CPCP

CPCP

RR

• Routers

• Communication Processors

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