295 60229 Verilog Tutorial1

8/20/2019 295 60229 Verilog Tutorial1

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Hardware Description Language (HDL)

What is the need for Hardware Description

Language?Model, Represent, And Siulate Digital HardwareHardware !oncurrenc"

#arallel Acti$it" %low

Seantics for Signal &alue And 'ie

Special !onstructs And Seantics dge 'ransitions

#ropagation Dela"s

'iing !hecs


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&R+L- HDL

.asic /nit 0 A odule

Module Descries the functionalit" of the design

States the input and output ports

2aple3 A !oputer %unctionalit"3 #erfor user de4ned coputations

+5 #orts3 6e"oard, Mouse, Monitor, #rinter


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Module

-eneral de4nition

module odule8nae ( port8list)9

port declarations9

:

$ariale declaration9:

description of eha$ior

endmodule

2aple

module HalfAdder (A, ., Su!arr")9

input A, .9

output Su, !arr"9

assign Su ; A < .955< denotes =R

assign !arr" ; A > .9

55 > denotes AD

endmodule


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Le2ical !on$entions

Comments

55 Single line coent5 Another single line coent 5

5 .egins ultiBline (loc) coent

All te2t within is ignored

Line elow ends ultiBline coent5

Number

decial, he2, octal, inar"

unsiCed decial forsiCe ase for

include underlines, ,B String

E nclose etween Fuotes on a single lineE


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Le2ical !on$entions (cont)

Identifer

A Ia C

J K

/nderscore

Strings are liited to 1J*@ chars

%irst char of identi4er ust not e a digit

Keywords3 See te2t

Operators3 See te2t

Verilog is case sensitive


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Description St"les

Structural3 Logic is descried in ters of &erilog

gate priiti$es 2aple3

not n1(sel8n, sel)9and a1(sel8, , sel8)9

and a*(sel8a, a, sel)9or o1(out, sel8, sel8a)9

sel

aout

sel_n

sel_b

sel_a

n1 a1

a2

o1


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Description St"les (cont)

ata!ow3 Specif" output signals in ters of input

signals 2aple3

assign out ; (sel > a) N (Osel > )9

sel

a

outsel_n

sel_b

sel_a


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Description St"les (cont)

"e#avioral3 Algorithicall" specif" the eha$ior

of the design 2aple3

if (select ;; J) egin

out ; 9

end

else if (select ;; 1) egin

out ; a9

end

a

sel

out.lac .o2

*21 M/=


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Structural Modeling

2ecution3 !oncurrent

%orat (#riiti$e -ates)3and

-*(!arr", A, .)9

%irst paraeter (!arr") 0 utput

ther +nputs (A, .) B +nputs


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DataQow Modeling

/ses continuous assignent stateent

%orat3 assign dela" net ; e2pression9 2aple3 assign su ; a < 9

elay3 'ie duration etween assignent froRHS to LHS

All continuous assignent stateents e2ecuteconcurrentl"

rder of the stateent does not ipact the design


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DataQow Modeling (cont)

Dela" can e introduced

2aple3 assign T* su ; a < 9 UT*V indicates * tieBunits

o dela" speci4ed 3 J (default)

Associate tieBunit with ph"sical tie tiescale tieBunit5tieBprecision

2aple3 tiescale 1ns51JJ ps

'iescale

tiescale 1ns51JJps 1 'ie unit ; 1 ns

'ie precision is 1JJps (J1 ns)

1JG1*ns is interpreted as 1JGns


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2aple3

tiescale 1ns51JJps

module HalfAdder (A, ., Su, !arr")9

input A, .9

output Su, !arr"9assign T7 Su ; A < .9

assign T !arr" ; A > .9

endmodule


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.eha$ioral Modeling

$%ample&

module u28*21(a, , sel, out)9

input a, a, sel9

output out9

alwa"s X(a or or sel)

egin

if (sel ;; 1)

out ; a9

else out ; 9

endendmodule

Sensiti$it" List


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.eha$ioral Modeling (cont)

alwa"s stateent 3 SeFuential .loc

SeFuential .loc3 All stateents within the locare e2ecuted seFuentiall"

When is it e2ecuted?

ccurrence of an e$ent in the sensiti$it" list $ent3 !hange in the logical $alue

Stateents with a SeFuential .loc3 #roceduralAssignents

Dela" in #rocedural Assignents +nterBStateent Dela"

+ntraBStateent Dela"


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.eha$ioral Modeling (cont)

+nterBAssignent Dela"

2aple3Su ; A .9Dela"ed assignent


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#rocedural !onstructs

'wo #rocedural !onstructs

initial Stateent alwa"s Stateent

initial Stateent 3 2ecutes onl" once

alwa"s Stateent 3 2ecutes in a loop

2aple3

:initial egin Su ; J9

!arr" ; J9end:

:alwa"s X(A or .) egin Su ; A < .9

!arr" ; A > .9end:


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$ent !ontrol

$ent !ontrol

dge 'riggered $ent !ontrol Le$el 'riggered $ent !ontrol

dge 'riggered $ent !ontrol

X (posedge !L6) 55#ositi$e dge of !L6

!urr8State ; e2t8state9

Le$el 'riggered $ent !ontrol

X (A or .) 55change in $alues of A or .

ut ; A > .9


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Loop Stateents

Loop Stateents

RepeatWhile

%or

Repeat Loop 2aple3

repeat (!ount)

su ; su G9

+f condition is a 2 or C it is treated as J


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Loop Stateents (cont)

While Loop

2aple3while (!ount Y 1J) egin

su ; su G9

!ount ; !ount 19

end

+f condition is a 2 or C it is treated as J

%or Loop 2aple3

for (!ount ; J9 !ount Y 1J9 !ount ; !ount 1) egin

su ; su G9

end


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!onditional Stateents

if Stateent

%orat3if (condition)

procedural8stateent

else if (condition)

procedural8stateentelse

procedural8stateent

2aple3

if (!l) Z ; J9

else

Z ; D9


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!onditional Stateents (cont)

!ase Stateent

2aple 13case (=)

*[JJ3 \ ; A .9

*[J13 \ ; A 0 .9

*[1J3 \ ; A 5 .9

endcase

2aple *3

case (7[1J1 YY *)

7[1JJ3 A ; . !9

@[J1JJ3 A ; . 0 !9

G[1J1JJ3 A ; . 5 !9 55'his stateent ise2ecuted

endcase


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!onditional Stateents (cont)

&ariants of case Stateents3

case2 and caseC

caseC 0 C is considered as a don[t care

case2 0 oth 2 and C are considered as don[t cares

2aple3

caseC (=)

*[1C3 A ; . !9

*[113 A ; . 5 !9endcase


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Data '"pes

et '"pes3 #h"sical !onnection etween structural

eleents Register '"pe3 Represents an astract storage

eleent

Default &alues et '"pes 3 C

Register '"pe 3 2

et '"pes3 wire, tri, wor, trior, wand, triand,

suppl"J, suppl"1

Register '"pes 3 reg, integer, tie, real, realtie


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Data '"pes

et '"pe3 Wire

wire s 3 ls wire1, wire*, : 2aple

wire Reset9 55 A 1Bit wire

wire 3J !lear9 55 A Bit wire

Register '"pe3 Reg

reg s 3 ls reg1, reg*, :

2aple

reg 73 J cla9 55 A @Bit registerreg cla9 55 A 1Bit register


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Restrictions on Data '"pes

Data %low and Structural Modeling

!an use onl" wire data t"pe !annot use reg data t"pe

.eha$ioral Modeling !an use onl" reg data t"pe (within initial and alwa"s

constructs)

!annot use wire data t"pe


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Meories

An arra" of registers

reg s 3 ls eor"1 upper 3 lower 9

2aple

reg J 3 7 e J 3 7 9

55 An arra" of @ @Bit registersreg e J 3 @ 9

55 An arra" of G 1Bit registers


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!opiler Directi$es

de4ne 0 (Siilar to Tde4ne in !) used to de4ne

gloal paraeter 2aple3

de4ne ./S8W+D'H 1

reg ./S8W+D'H B 1 3 J S"ste8.us9

undef 0 Reo$es the pre$iousl" de4ned directi$e

2aple3

de4ne ./S8W+D'H 1

: reg ./S8W+D'H B 1 3 J S"ste8.us9

:

undef ./S8W+D'H


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!opiler Directi$es (cont)

include 0 used to include another 4le

2apleinclude U5fulladder$V


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S"ste 'ass

Displa" tass

]displa" 3 Displa"s the entire list at the tie whenstateent is encountered

]onitor 3 Whene$er there is a change in an"arguent, displa"s the entire list at end of tie step

Siulation !ontrol 'as ]4nish 3 aes the siulator to e2it

]stop 3 suspends the siulation

'ie ]tie3 gi$es the siulation


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'"pe of #ort !onnections

!onnection " #osition

parent8od


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'"pe of #ort !onnections (cont)

!onnection " ae

parent8od


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pt" #ort !onnections

+f an input port of an instantiated odule is ept",

the port is set to a $alue of C (high ipedance)module child8od(+n1, +n*, ut1, ut*) module parent8od(::) input +n19input +n*9 child8od od(A, ,\1, \*)9output ut19 55pt" +nput

output ut*9 endmodule 55eha$ior relating +n1 and +n* to ut1

endmodule

+f an output port of an instantiated odule is left

ept", the port is considered to e unused module parent8od(::) child8od od(A, ., \1, )9 55pt" utputendmodule


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'est .ench

tiescale 1ns51JJpsmodule 'op9

reg #A, #.9wire #Su, #!arr"9

HalfAdder -1(#A, #., #Su, #!arr")9

initial egin3 LA.L reg *3J i9 for (i;J9 iY@9 i;i1) egin ^#A, #._ ; i9 TG ]displa" (U#A;` #.;` #Su;` #!arr";`V, #A, #., #Su,

#!arr")9 end 55 forend 55 initial

endmodule

'est .ench

DesignModule

Appl" +nputs

ser$e utputs


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'est .ench B -enerating Stiulus

2aple3 A seFuence of

$alues

initial egin

!loc ; J9

TGJ !loc ; 19 T7J !loc ; J9

T*J !loc ; 19

end


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'est .ench B -enerating !loc

Repetiti$e Signals (cloc)

!loc

A Siple Solution3

wire !loc9assign T1J !loc ; O !loc

!aution3

+nitial $alue of !loc (wire datat"pe) ; C

OC ; 2 and O2 ; 2


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'est .ench B -enerating !loc (cont)

+nitialiCe the !loc signal

initial egin

!loc ; J9

end !aution3 !loc is of data t"pe wire, cannot e used in an

initial stateent

Solution3reg !loc9

:

initial egin

!loc ; J9

end:

alwa"s egin

T1J !loc ; O !loc9

d

fore$er loop canalso e used togenerate cloc

295 60229 Verilog Tutorial1

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