27 th May 2004Daniel Bowerman1 Dan Bowerman Imperial College 27 th May 2004 Status of the Calice...

27th May 2004 Daniel Bowerman 1

Dan BowermanImperial College

27th May 2004

Status of the Calice Electromagnetic Calorimeter


Prototype Overview

62 mm62

mm

200mm

360mm

360mm

•30 layers of variable thickness Tungsten•Active silicon layers interleved•Front end chip and readout on PCB board•Signals sent to DAQ

•Tungsten layers wrapped in Carbon Fibre•8.5 mm for PCB & Silicon layer

•6x6 1x1cm2 silicon pads•Connected to PCB with conductive glue

•PCB contains VFE electronics•14 layers, 2.1mm thick•Analogue signals sent to DAQ


Silicon Wafers

62 mm

62 m

m

4” High resistive wafer :4” High resistive wafer : 5 K5 K cm cm

Thickness :Thickness : 525 microns525 microns 3 % 3 %

TileTile sideside :: 62.0 mm 62.0 mm includingincluding GuardGuard ringring

In Silicon ~80 e-h pairs / micron In Silicon ~80 e-h pairs / micron 42000 42000 ee-- /MiP /MiP

Capacitance :Capacitance : ~21 pF~21 pF

Leakage current :Leakage current : 5 – 20 nA5 – 20 nA

Full depletion bias :Full depletion bias : ~150 V~150 V

Nominal operating bias :Nominal operating bias : 250 V250 V

Each Wafer: Matrix of 6 x 6 pixel of 1 cm2

Require 270 active wafers for the Prototype150 to be produced by Institute of Nuclear Physics – Moscow State UniversityFirst test production: February 2003, 130 wafers produced already

150 to be produced by Institute of Physics, Academy of Sciences of Czech Republic,PragueFirst test production: March 2004, 15 produced already, full production by end of June

Both sets of Wafers are of high quality


Very Front End Electronics

AmpOPA

OPA

MUX out Gain=1

MUX out Gain=10

1 channel•Preamp with 16 gains

(gain selected offline)

•CR-RC shaper (~200ns), track and hold

•18 channels in, one Multiplexed output

Each chip serves 18 channels, 2 chips per wafer

Linearity: ± 0.2 %

Range: ~600 MIPS

Crosstalk < 0.2%3 generations of improving productionNumbers quoted refer to V2V3 produced, and being tested

VFE consists of


Production & TestingMounting/gluing the wafers

Using a frame oftungsten wires

6 active silicon wafers

12 VFE chips

2 calibration switch chips

Line BuffersTo DAQ

•PCB designed in LAL-Orsay, made in Korea (KNU)

•60 Required for Prototype, ready in July

•An automatic device is use to deposit the conductive glue : EPO-TEK® EE129-4 •Gluing and placement ( 0.1 mm) of 270 wafers with 6×6 pads, 10 000 points of glue•About 10 000 points of glue.

•Production line set up at LLR


Production & Testing•Must validate assembly, mounting and performance of each PCB

•Dedicated DAQ system to test individual PCBs

•Use in conjunction with Cosmic test bench, or 90Sr β decay

ScintillatorPlane

ScintillatorPlane

VFE-PCB

Daq board and

control signals

to VFE PCB

Interconexion Panel

Triggergenerator


First tests with prototype PCB

Sr90 source trigger read 6 channelsOnly ONEwith signal

5Noise

MIP

output ADC

Noise

“external” signal

-0,025

-0,02

-0,015

-0,01

-0,005

0

0,005

0,01

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Channel

DA

Q o

utpu

t (V

)

Base line Signal Signal with pedestal correction

-Theoretic result : 4.97mV -Measured : 5.05mV

-Theoretic result : 4.97mV -Measured : 5.05mV

1 MIP injected in channel 10 with Calibration chip and measurement made on 100 points

“internal” signal


Prototype DAQ •Use custom VME readout board•Based on CMS tracker front-end board (FED)•Uses several FPGA’s for main controls•Dual 16-bit ADCs (500 kHz) and 16-bit DAC•On-board buffer memory 8 Mbytes. 1.6k event buffer, no data reduction

•Prototype design completed last summer

•Two prototype boards fabricated in November•Noise ~ 1ADC count•Linear to 0.01%•Gains uniform to 1%

Further tests, final production ~ July


Full Chain - Cosmics• Now attach PCB to Prototype DAQ board – Full Detector Chain

• Use track interpolation from scintillators to select events•Clear cosmic MIP peak seen, ~45 ADC counts above pedestal

•MIP = 200 keV; calibrates ADC so 1 count = 4.4 keV

•32k full range ~ 700 MIPs; requirement > 600 MIPs

•Noise per channel ~ 9 ADC counts = 40 keV

•MIP:noise ~ 5:1; requirement > 4:1

•Expect 7.5:1 from initial tests with new VFE chip

•Selecting events with at least one pad > 40 ADC counts (4σ cut)

•Clearly highlights the active 66 cm2 silicon wafer

•Can survey wafer positions, and cross-check readout positions


Full Chain - Cosmics

•Example of Cosmic Event

•Passes through scintillators

•Extrapolated through silicon

•Appears as clear signal above background

Scintillator

Scintillator

WaferX-Z

plane

Y-Zplane


Future Technology R&D

Pad

Silicon wafer

PCB

Aluminium

Cooling tube Cooling tubeVFE chip1.3 mm

1.0 mm

0.5 mm

Thermal contact

gluing for electrical contact

AC coupling elements ?

power linecommand linesignal out

Pad

Silicon wafer

PCB

Aluminium

Cooling tube Cooling tubeVFE chip1.3 mm

1.0 mm

0.5 mm

Thermal contact

gluing for electrical contact

AC coupling elements ?

power linecommand linesignal out

Prototype design is not realistic as:-Industry cannot build 1.6 m PCB; tendancy is for smaller PCBs-High line capacitance very noisy-Large number of lines crosstalk issue and many PCB layers

R&D for the full scale detector is also progressing

Possible solution: VFE Chip mounted near wafers

-1 chip per wafer-Low power issue-Cooling issues-Temperature distribution in module?-Fake signal due to e.m. showers in chip

Simulation Thermal dissipation withinternal cooling at the border with liquid flow

Two chips produced this year, simulation underway, cooling prototype and test bench being developed.Future DAQ ideas also being investigated

Big Issue: Funding mechanism for this R&D not established


Prototype Status and Timelines

Items Status Comments Tungsten plates Funded and produced Good production, no problem so far Structure with carbon fiber Funded, first structure produced,

second and third in production

Wafer sample 1 Produced by MSU, funded by IN2P3

Small problem of size not within tolerance; will delay mounting

Wafer sample 2 First test batch produced at Prague in April 2004

First batch of 15 wafers received

PCB for testing Version KNU-1 Fill the requirement PCB for prototype Version KNU-2 in test Would be the prototype version VFE chip Designed, produced Calibration DAQ Tested and running Ready for assembly validation and

calibration Full prototype DAQ Under test at the LLR cosmic

test bench Board prototypes produced , firmware in development. Production this summer

Support table Funded, designed at LAL-Orsay In construction

Prototype components status:

All elements of the prototype are at or are close to scheduleAll wafers/PCB’s tested by October 2004Plan for low energy electron test beam at DESY before the end of the yearHigh energy electron/hadron test beams with HCAL at FNAL/IHEP next year


Conclusions•Great deal of progress in the past 18 months

•All prototype components in production and at or close to schedule

•Performance of individual components at or better than required

•Complete detector chain in place and tested

•Captured Cosmics and β decays

•Good Signal to Noise

•Extensive testing to ensure quality of prototype components

•Preparing for Test Beam at DESY by the end of the year

•Full ECAL & HCAL hadron test beam next year


Ecal concepte+e–ZH, Z at s=500 GeV

HCALCOIL

ECAL

•Jet Energy resolution is key to LC detector performance

•Energy Flow technique gives best Jet Energy resolution

•Requires tracking calorimetry to resolve individual particles

•Tracking Calorimeter requires high granularity/segmentation

•Ecal : Si-W sampling calorimeter, 40 layers, 1x1 cm2 pads, 32 M channels, 24X0 in 20 cm

•Require Testbeam – Monte Carlo tuning to accurately determine possible jet resolution

27 th May 2004Daniel Bowerman1 Dan Bowerman Imperial College 27 th May 2004 Status of the Calice...

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