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IKI20210Pengantar Organisasi Komputer

Kuliah Minggu ke-4b: Bahasa Rakitan MIPS I

diadaptasikan dari materi kuliahCS61C/2000 & CS152/1997 2000/1997 UCB

27 September 2002

Bobby Nazief (nazief@cs.ui.ac.id)Johny Moningka (moningka@cs.ui.ac.id)

bahan kuliah: http://www.cs.ui.ac.id/~iki20210/

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Administratif:

° Tugas PR: hari ini!

° Jadwal Lab: daftarkan segera!

• Rabu & Kamis

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Review:

AVR Assembler & AVR Studio

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Bahasa Rakitan MIPS I

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Salient features of MIPS I•32-bit fixed format inst (3 formats)

•32 32-bit GPR (R0 contains zero) and 32 FP registers (and HI LO)

•partitioned by software convention

•3-address, reg-reg arithmetic instr.

•Single address mode for load/store: base+displacement

–no memory indirection, scaled

–16-bit immediate plus LUI

•Simple branch conditions

• compare against zero or two registers for =,°

• no integer condition codes

•Delayed branch

•execute instruction after the branch (or jump) even if

the branch is taken (Compiler can fill a delayed branch with

useful work about 50% of the time)

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MIPS I Registers° Programmable storage

• 2^32 x bytes of memory

• 31 x 32-bit GPRs (R0 = 0)

• 32 x 32-bit FP regs (paired DP)

• HI, LO, PC0r0

r1°°°r31PClohi

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MIPS Addressing Modes/Instruction Formats

op rs rt rd

immed

register

Register (direct)

op rs rt

register

Base+index

+

Memory

immedop rs rtImmediate

immedop rs rt

PC

PC-relative

+

Memory

• All instructions 32 bits wide

• Register Indirect?

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MIPS arithmetic instructions

Instruction Example Meaning Comments

add add $1,$2,$3 $1 = $2 + $3 3 operands; exception possible

subtract sub $1,$2,$3 $1 = $2 – $3 3 operands; exception possible

add immediate addi $1,$2,100 $1 = $2 + 100 + constant; exception possible

add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; no exceptions

subtract unsigned subu $1,$2,$3 $1 = $2 – $3 3 operands; no exceptions

add imm. unsign. addiu $1,$2,100 $1 = $2 + 100 + constant; no exceptions

multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product

multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product

divide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = remainder

Hi = $2 mod $3

divide unsigned divu $2,$3 Lo = $2 ÷ $3, Unsigned quotient & remainder

Hi = $2 mod $3

Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi

Move from Lo mflo $1 $1 = Lo Used to get copy of Lo

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MIPS logical instructions

Instruction Example Meaning Comment

and and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical AND

or or $1,$2,$3 $1 = $2 | $3 3 reg. operands; Logical OR

xor xor $1,$2,$3 $1 = $2 $3 3 reg. operands; Logical XOR

nor nor $1,$2,$3 $1 = ~($2 |$3) 3 reg. operands; Logical NOR

and immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg, constant

or immediate ori $1,$2,10 $1 = $2 | 10 Logical OR reg, constant

xor immediate xori $1, $2,10 $1 = ~$2 &~10 Logical XOR reg, constant

shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant

shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant

shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend)

shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable

shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable

shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable

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MIPS data transfer instructions

Instruction Comment

SW 500(R4), R3 Store word

SH 502(R2), R3 Store half

SB 41(R3), R2 Store byte

LW R1, 30(R2) Load word

LH R1, 40(R3) Load halfword

LHU R1, 40(R3) Load halfword unsigned

LB R1, 40(R3) Load byte

LBU R1, 40(R3) Load byte unsigned

LUI R1, 40 Load Upper Immediate (16 bits shifted left by 16)

0000 … 0000

LUI R5

R5

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Addressing Mode Usage? (ignore register mode)3 programs measured on machine with all address modes (VAX)

--- Displacement: 42% avg, 32% to 55% 75%

--- Immediate: 33% avg, 17% to 43% 85%

--- Register deferred (indirect): 13% avg, 3% to 24%

--- Scaled: 7% avg, 0% to 16%

--- Memory indirect: 3% avg, 1% to 6%

--- Misc: 2% avg, 0% to 3%

75% displacement & immediate88% displacement, immediate & register indirect

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MIPS Compare and Branch

° Compare and Branch

• BEQ rs, rt, offset if R[rs] == R[rt] then PC-relative branch

• BNE rs, rt, offset <>

° Compare to zero and Branch

• BLEZ rs, offset if R[rs] <= 0 then PC-relative branch

• BGTZ rs, offset >

• BLT <

• BGEZ >=

• BLTZAL rs, offset if R[rs] < 0 then branch and link (into R 31)

• BGEZAL >=

° Remaining set of compare and branch take two instructions

° Almost all comparisons are against zero!

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Conditional Branch Addressing

• PC-relative since most branches are relatively close to the current PC address

• At least 8 bits suggested (± 128 instructions)

• Compare Equal/Not Equal most important for integer programs (86%)

Frequency of comparison types in branches

0% 50% 100%

EQ/NE

GT/LE

LT/GE

37%

23%

40%

86%

7%

7%

Int Avg.

FP Avg.

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MIPS Compare and Set, Jump instructions

Instruction Example Meaning

set on less than slt $1,$2,$3 if ($2 < $3) $1=1; else $1=0 Compare less than; 2’s comp.

set less than imm slti $1,$2,100 if ($2 < 100) $1=1; else $1=0 Compare < constant; 2’s comp.

set less than uns. sltu $1,$2,$3 if ($2 < $3) $1=1; else $1=0 Compare less than; natural numbers

set l. t. imm. uns. sltiu $1,$2,100 if ($2 < 100) $1=1; else $1=0 Compare < constant; natural numbers

jump j 10000 go to 10000Jump to target address

jump register jr $31 go to $31For switch, procedure return

jump and link jal 10000 $31 = PC + 4; go to 10000For procedure call

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MIPS (RISC) vs. Intel 80x86 (CISC)

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Intel History: ISA evolved since 1978

° 8086: 16-bit, all internal registers 16 bits wide; no general purpose registers; ‘78

° 8087: + 60 Fl. Pt. instructions, (Prof. Kahan) adds 80-bit-wide stack, but no registers; ‘80

° 80286: adds elaborate protection model; ‘82

° 80386: 32-bit; converts 8 16-bit registers into 8 32-bit general purpose registers; new addressing modes; adds paging; ‘85

° 80486, Pentium, Pentium II: + 4 instructions

° MMX: + 57 instructions for multimedia; ‘97

° Pentium III: +70 instructions for multimedia; ‘99

° Pentium 4: +144 instructions for multimedia; '00

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MIPS vs. Intel 80x86

° MIPS: “Three-address architecture”

• Arithmetic-logic specify all 3 operands

add $s0,$s1,$s2 # s0=s1+s2

• Benefit: fewer instructions performance

° x86: “Two-address architecture”

• Only 2 operands, so the destination is also one of the sources

add $s1,$s0 # s0=s0+s1

• Often true in C statements: c += b;

• Benefit: smaller instructions smaller code

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MIPS vs. Intel 80x86

° MIPS: “load-store architecture”

• Only Load/Store access memory; rest operations register-register; e.g.,

lw $t0, 12($gp) add $s0,$s0,$t0 # s0=s0+Mem[12+gp]

• Benefit: simpler hardware easier to pipeline, higher performance

° x86: “register-memory architecture”

• All operations can have an operand in memory; other operand is a register; e.g.,

add 12(%gp),%s0 # s0=s0+Mem[12+gp]

• Benefit: fewer instructions smaller code

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MIPS vs. Intel 80x86

° MIPS: “fixed-length instructions”

• All instructions same size, e.g., 4 bytes

• simple hardware performance

• branches can be multiples of 4 bytes

° x86: “variable-length instructions”

• Instructions are multiple of bytes: 1 to 17;

small code size (30% smaller?)

• More Recent Performance Benefit: better instruction cache hit rates

• Instructions can include 8- or 32-bit immediates

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Instructions: MIPS vs. 80x86

° addu, addiu

° subu

° and,or, xor

° sll, srl, sra

° lw

° sw

° mov

° li

° lui

° addl

° subl

° andl, orl, xorl

° sall, shrl, sarl

° movl mem, reg

° movl reg, mem

° movl reg, reg

° movl imm, reg

° n.a.

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80386 addressing (ALU instructions too)

° base reg + offset (like MIPS)•movl -8000044(%ebp), %eax

° base reg + index reg (2 regs form addr.)•movl (%eax,%ebx),%edi

# edi = Mem[ebx + eax]

° scaled reg + index (shift one reg by 1,2)•movl(%eax,%edx,4),%ebx

# ebx = Mem[edx*4 + eax]

° scaled reg + index + offset•movl 12(%eax,%edx,4),%ebx

# ebx = Mem[edx*4 + eax + 12]

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Branch: MIPS vs. 80x86

° beq

° bne

° slt; beq

° slt; bne

° jal

° jr $31

° (cmpl;) jeif previous operation set condition code, then cmpl unnecessary

° (cmpl;) jne

° (cmpl;) jlt

° (cmpl;) jge

° call

° ret

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RISC vs. CISC

° RISC = Reduced Instruction Set Computer

• Term coined at Berkeley, ideas pioneered by IBM, Berkeley, Stanford

° RISC characteristics:

• Load-store architecture

• Fixed-length instructions (typically 32 bits)

• Three-address architecture

° RISC examples: MIPS, SPARC, IBM/Motorola PowerPC, Compaq Alpha, ARM, SH4, HP-PA, ...

° CISC = Complex Instruction Set Computer

• Term referred to non-RISC architectures

° CISC characteristics:

• Register-memory architecture

• Variable-length instructions

° RISC examples: Intel 80x86, VAX, IBM 360, …