24th IEEE International Symposium on Asynchronous ...€¢ CAD tools for integrating asynchronous...
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ASYNC Vienna, Austria 2018 May13-16 Call for Papers Important Dates Abstract Registration Regular Papers: November 26, 2017 Other Papers: February 14, 2018 Paper Submission Regular Papers: December 3, 2017 Other Papers: (Abstracts only) Notification of Acceptance Regular Papers: February 7, 2018 Other Papers: February 28, 2018 Publication Ready Version Regular Papers: March 10, 2018 Other Papers: March 10, 2018 General Chairs Andreas Steininger, TU Vienna, Austria [email protected] Matthias Fuegger, CNRS & ENS Paris-Saclay, France [email protected] Program Chairs Milos Krstic, IHP and University of Postdam, Germany [email protected] Ian W. Jones, Oracle, USA [email protected] http://async2018.wien Submissions for regular and special topics must report original scientific work, in 6-8 pages IEEE double-column conference format (single- spaced, 10pt or larger font size), with author information concealed. Accepted papers will be published in the IEEE digital library IEEEXplore and symposium proceedings. Paper Format and Submission The International Symposium on Asynchronous Circuits and Systems (ASYNC) is the premier forum for researchers to present their latest findings in asynchronous design. Authors are invited to submit papers on any aspect of asynchronous design, ranging from design, synthesis, and test to asynchronous applications. Topics of interest include: • Asynchronous pipelines, architectures, CPUs, and memories • Asynchronous ultra-low power systems, energy harvesting, and mixed-signal/analogue • Asynchrony in emerging technologies, including bio, neural, nano, and quantum computing • CAD tools for asynchronous design, synthesis, analysis, and optimization • Formal methods for verification and performance/power analysis • Test, security, fault tolerance, and radiation hard design • Asynchronous variability-tolerant design, resilient design, and design for manufacturing • Asynchronous design for neural networks and machine learning applications • Circuit designs, case studies, comparisons, and applications • Mixed-timed circuits, clock domain crossing, GALS systems, Network-on-Chip, and multi-chip interconnects • Hardware implementations of asynchronous models and algorithms, asynchronous techniques in clocked designs, and elastic and latency-tolerant synchronous design We solicit 1-2 page submissions that present “fresh ideas” in asynchronous design, not yet ready for publication. These will go through a separate light-weight review process. Accepted submissions will be assembled in a binder and handed out at the workshop. We also invite students to present a poster on their research, co-authored with their advisor, and to submit a 1 page abstract that will receive a light-weight review. “Fresh Ideas” / Student Posters ASYNC 2018 will include papers and tutorials from industry on the state-of-the-art application of asynchronous designs to both existing and emerging technologies. The topics are specifically targeted at industry and include: • Synchronizers and clock domain crossing techniques • Techniques for combining asynchronous and clocked designs • CAD tools for integrating asynchronous circuits with clocked designs • Circuit designs, case studies, comparisons, and applications We solicit 1-2 page submissions for the workshop, IEEE double-column conference format. These papers will go through a separate light-weight review process. Accepted papers will be published in the IEEE digital library IEEEXplore and symposium proceedings. We also solicit tools and demos for presentation at the conference. Industrial Papers / Tools & Demos 24th IEEE International Symposium on Asynchronous Circuits and Systems © WienTourismus/Christian Stemper
Transcript of 24th IEEE International Symposium on Asynchronous ...€¢ CAD tools for integrating asynchronous...
ASYNC Vienna, Austria
2018 May13-16 Call for Papers
Important Dates
Abstract Registration Regular Papers: November 26, 2017 Other Papers: February 14, 2018
Paper Submission Regular Papers: December 3, 2017 Other Papers: (Abstracts only)
Notification of Acceptance Regular Papers: February 7, 2018 Other Papers: February 28, 2018
Publication Ready Version Regular Papers: March 10, 2018 Other Papers: March 10, 2018
General Chairs Andreas Steininger, TU Vienna, Austria [email protected] Matthias Fuegger, CNRS & ENS Paris-Saclay, France [email protected]
Program Chairs Milos Krstic, IHP and University of Postdam, Germany [email protected] Ian W. Jones, Oracle, USA [email protected]
http://async2018.wien
Submissions for regular and special topics must report original scientific work, in 6-8 pages IEEE double-column conference format (single-spaced, 10pt or larger font size), with author information concealed. Accepted papers will be published in the IEEE digital library IEEEXplore and symposium proceedings.
Paper Format and Submission
The International Symposium on Asynchronous Circuits and Systems (ASYNC) is the premier forum for researchers to present their latest findings in asynchronous design. Authors are invited to submit papers on any aspect of asynchronous design, ranging from design, synthesis, and test to asynchronous applications. Topics of interest include: • Asynchronous pipelines, architectures, CPUs, and memories • Asynchronous ultra-low power systems, energy harvesting, and mixed-signal/analogue • Asynchrony in emerging technologies, including bio, neural, nano, and quantum computing • CAD tools for asynchronous design, synthesis, analysis, and optimization • Formal methods for verification and performance/power analysis • Test, security, fault tolerance, and radiation hard design • Asynchronous variability-tolerant design, resilient design, and design for manufacturing • Asynchronous design for neural networks and machine learning applications • Circuit designs, case studies, comparisons, and applications • Mixed-timed circuits, clock domain crossing, GALS systems, Network-on-Chip, and multi-chip interconnects • Hardware implementations of asynchronous models and algorithms, asynchronous techniques in clocked designs, and elastic and latency-tolerant synchronous design
We solicit 1-2 page submissions that present “fresh ideas” in asynchronous design, not yet ready for publication. These will go through a separate light-weight review process. Accepted submissions will be assembled in a binder and handed out at the workshop. We also invite students to present a poster on their research, co-authored with their advisor, and to submit a 1 page abstract that will receive a light-weight review.
“Fresh Ideas” / Student Posters
ASYNC 2018 will include papers and tutorials from industry on the state-of-the-art application of asynchronous designs to both existing and emerging technologies. The topics are specifically targeted at industry and include: • Synchronizers and clock domain crossing techniques • Techniques for combining asynchronous and clocked designs • CAD tools for integrating asynchronous circuits with clocked designs • Circuit designs, case studies, comparisons, and applicationsWe solicit 1-2 page submissions for the workshop, IEEE double-column conference format. These papers will go through a separate light-weight review process. Accepted papers will be published in the IEEE digital library IEEEXplore and symposium proceedings. We also solicit tools and demos for presentation at the conference.
Industrial Papers / Tools & Demos
24th IEEE International Symposium on Asynchronous Circuits and Systems
© WienTourismus/Christian Stemper
