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Lecture 16Programmable Logic Devices

PROMs, PLAs, PALS,

Lecture 16Programmable Logic Devices

PROMs, PLAs, PALS, TopicsTopics

Review of shift registers, ROMS

ALU Design

Readings: 8.5, 9.1Readings: 8.5, 9.1

October 19, 2010

CSCE211 Digital Design

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2 CSCE211H Fall 2010

OverviewOverviewLast TimeLast Time

State machine construction $.35 toll booth (=coke machine with no change)

NewNew

Twodimensional ROMs

Overview Field Programmable Gate Arrays

Next Time:Next Time:

Test 2 : Thursday Nov 9, Review ???

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Read Only Memory FunctionalityRead Only Memory Functionality

Figure 9Figure 9--11

2nbROM

A0

A1 D0

A2 D1

An2 Db1

An1

addressinputs

dataoutputs

Copyright 2000 by Prentice Hall, Inc.

Digital Design Principles and Practices, 3/e

Nota Bene! Figure are from last years versionIn which this chapter was Chap 10 now this is in Chap 9.

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3-Input4-Output ROM3-Input4-Output ROMInputs Outputs Table 10-1

Truth table for a

3-input, 4-output combinational logic

function.

A2 A1 A0 D3 D2 D1 D0

0 0 0 1 1 1 0

0 0 1 1 1 0 1

0 1 0 1 0 1 1

0 1 1 0 1 1 1

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

3x8decoder

A0

A1

A2

A0OR

OR

OR

OR D0

D1

D2

D3

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Construction of a 2 x n ROMConstruction of a 2 x n ROM

Zap some connections duringZap some connections duringconstructionconstruction

Denoted xDenoted x

2x4decoder

A0

A1

d0

d1

d2

d3

Y0 Y1 Y2 Yn-1

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2x4 Decoder with Output-PolarityControl2x4 Decoder with Output-PolarityControl

Figure 9Figure 9--22I0

(A0)

(A1)

(A2)

I1

POL

Y0

(D0)

(D1)

(D2)

(D3)

Y1

Y2

Y3



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Implementing Arbitrary Boolean functions with ROMsImplementing Arbitrary Boolean functions with ROMs

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Multipliers in ROMMultipliers in ROM

Figure 9Figure 9--44

A0

A1

D0

A2

A3

A4

A5

A6

A7

P0

P1P2

P3

P4

P5

P6

P7

D1D2

D3

D4

D5

D6

D7

Y0

Y1Y2

Y3

X0

X1

X2

X3

multiplicand

multiplier

product

256 8 ROM



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Fig 9-5 Logic Diagram of 8x4 diode ROMFig 9-5 Logic Diagram of 8x4 diode ROM

xx

D0 0

1

0

0

D2

D3

+5 V

+5 V

U1

74x138

ROW0_L HIGH

HIGH

HIGH

HIGH

HIGH

LOW

HIGH

HIGH

R

R

ROW1_L

ROW2_L

ROW3_L

ROW4_L

ROW5_L

ROW6_L

ROW7_L74HC14

D0_L

D1_L

D2_L

D3_L

G2A

G1

G2B

Y0

Y1

Y2

Y3

615

14

13

1

3

5

9 8

6

4

2

4

5

BA

C

A1A01

0

1 A2Y4

Y5

Y6

Y7

1 12

11

10

9

7

2

3

D1

U2

U2

U2

U2

HIGH

LOW

HIGH

HIGHCopyright 2000 by Prentice Hall, Inc.


74LS138 =1-OF-8 DECODER/DEMULTIPLEXER

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Two-Dimensional DecodingTwo-Dimensional Decoding

I0

(A0)

(A1)

(A2)

I1

POL

Y0

(D0)

(D1)

(D2)

(D3)

Y1

Y2

Y3



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Field Programmable Gate ArraysField Programmable Gate Arrays

Xilinx SpartanXilinx Spartan--3 FPGA family.3 FPGA family. Download circuits onto the chip

FPGA Field

Programmable

Gate array

SpartanSpartan--3 FPGAs with 1 million system gates for under $12.003 FPGAs with 1 million system gates for under $12.00

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Xilinx FPGAXilinx FPGA

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Configurable Logic BlocksConfigurable Logic Blocks

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LUTs Look Up TablesLUTs Look Up Tables

Circuits are built in FPGA using Look Up Tables or LUTs.Circuits are built in FPGA using Look Up Tables or LUTs.

A lut is just a sequence of storage cells and then a collection ofA lut is just a sequence of storage cells and then a collection ofmultiplexers select which storage cell is routed to the output,multiplexers select which storage cell is routed to the output,

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LUT Structure(PawelChodowiec - Architecture ofXilinx FPGA devices)LUT Structure(PawelChodowiec - Architecture ofXilinx FPGA devices)

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CLB for Functions of 5 variablesCLB for Functions of 5 variables

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DL Diode Logic GatesDL Diode Logic Gates

Or GateOr Gate

AND GateAND Gate

Diagrams from play-hookey.com

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74x138 3x8 Decoder / Demultiplexer74x138 3x8 Decoder / Demultiplexer

xx

How a demux?

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Two-Dimensional Decoding AgainTwo-Dimensional Decoding Again

128x1 ROM128x1 ROMHigh order 3High order 3

address bitsaddress bitsused to selectused to selectone of 8 wordsone of 8 words

Low order4 bitsLow order4 bitsused to selectused to selectone of theseone of thesebits for thebits for theoutputoutput

+5 V

3-to-8decoder

0

1

2

310

2

A5A4

A6

A1

A0

A2

A3

S116-to-1 multiplexer

D

Y

S0

S2

S3

4

5

6

7

R

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15


Digital Design Principles and Practices, 3

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Memory (RAM) AccessMemory (RAM) Access

xx VDD

floating gate

nonfloating gate

active-highword lines

active-low bit lines



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ROM Timing DiagramsROM Timing Diagrams

CS_LCS_L Chip select (Low)Chip select (Low)

OE_LOE_L --

ADDR

CS_L

OE_L

DATA

tAA tOZ tOZ tOE

tOH

tOE

tACS

stable stable stable

tAA max(tAA,tACS)

valid validvalid



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22C

SCE

211H Fall 2010

EPROMSEPROMS

xx

12

13

10

2764

PGM

VPP

O1

O0

O2

O3

O4

O5

O6

O7

A0

A1

A2

19 19 19 19

15

16

11

17

18

9

8

1

7

6

5

4

3

21

23

A3

A4A5

A6

A7

A825

A924

A10

27

2

22

20

A11

A12

CS

OE

12

13

10

27128

PGM

VPP

O1

O0

O2

O3

O4

O5

O6

O7

A0

A1

A2

15

16

11

17

18

9

8

1

7

6

5

4

3

21

23

A3

A4A5

A6

A7

A825

A924

A10

27

2

22

20

22

20

22

20

A11

A1226

A13

CS

OE

12

13

10

27256

VPP

O1

O0

O2

O3

O4

O5

O6

O7

A0

A1

A2

15

16

11

17

18

9

8

1

7

6

5

4

3

21

23

A3

A4

A5A6

A7

A825

A924

A10

2A11

A12

26 A1327

A14

CS

OE

12

13

10

27512

O1

O0

O2

O3

O4

O5

O6

O7

A0

A1

A2

15

16

11

17

18

9

8

7

6

5

4

3

21

23

A3

A4

A5

A6A7

A825

A924

A10

2A11

A1226

A13

27 A141

A15

CS

OE/VPP

VCC

VIH VIH

VCC VCC

8K 8 16K 8 32K 8 64K 8



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Hooking Microprocessor to ROMHooking Microprocessor to ROM

xx

D7

7

6

20

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

D0D1

D2

D3

D4

D5

D6

D7

READ

WRITE

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

D0

D1

D2

D3

D4

D5

D6

D7

A16

A17

A18

A19

+5 VR

A16

A19

A18

A17

A15

19

22

12

13

10VPP

O1

O0

O2

O3

O4

O5

O6

O7

A0

A1

A2

15

16

11

17

18

9

8

1

7

6

5

4

3

21

23

A3

A4

A5

A6

A7

A825

A9

24

A10

2A11

A1226

A1327

A14

CS

OEU5

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

D0

D1

D2

D3

D4

D5

D6

microprocessor 27256

D7

20

19

22

12

13

10VPP

O1

O0

O2

O3

O4

O5

O6

O7

A0

A1

A2

15

16

11

17

18

9

8

1

7

6

5

4

3

21

23

A3

A4

A5

A6

A7

A825

A9

24

A10

2A11

A1226

A1327

A14

CS

OEU4

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

D0

D1

D2

D3

D4

D5

D6

27256

D7

20

19

22

12

13

10VPP

O1

O0

O2

O3

O4

O5

O6

O7

A0

A1

A2

15

16

11

17

18

9

8

1

7

6

5

4

3

21

23

A3

A4

A5

A6

A7

A825

A9

24

A10

2A11

A1226

A1327

A14

CS

OEU3

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

D0

D1

D2

D3

D4

D5

D6

27256

D7

20

19

22

12

13

10VPP

O1

O0

O2

O3

O4

O5

O6

O7

A0

A1

A2

15

16

11

17

18

9

8

1

7

6

5

4

3

21

23

A3

A4

A5

A6

A7

A825

A9

24

A10

2A11

A1226

A1327

A14

CS

OEU2

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

D0

D1

D2

D3

D4

D5

D6

27256

U1

A[190]

D[70]

1/2 74x139

1A

1B

1Y0

1Y1

1Y2

1Y3

1 4

5

2

3

HIMEM_L SE0000_L

SE8000_L

SF0000_L

SF8000_L

U7

1G

1

2 12

13

U6

74x10

RD_L

Copyright 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e

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211H Fall 2010

Programmable Logic Array - PLAProgrammable Logic Array - PLA

xxI2

I3

I1

I4

P1 P2 P3 P4

O2

O3

O1

P5 P6

Cop

yright2000byPrenticeHall,In

c.

DigitalDesignPrinciplesandPractices,3/e

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PLA implementationPLA implementation

xx

O1

O2

O3

P1 P2 P3 P4 P5 P6

I1

I2

I3

VCC

VCC

I4

I1 I1

I2 I2

I3 I3I4

I4



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SCE

211H Fall 2010

PLA Example: O1 = PLA Example: O1 =

xxI2

I3

I1

I4

P1 P2 P3 P4

O2

O3

O1

P5 P6

Cop

yright2000byPrenticeHall,In

c.

Digita

lDesignPrinciplesandPractices,3/e

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27 C

SCE

211H Fall 2010

Programmable Array

Logic PAL16L8

Programmable Array

Logic PAL16L8xx

3031

(2)

(19)

(18)

(17)

(16)

(15)

(14)

(13)

(12)

(11)

0 1 2 3 4 5 6 7 8 9 1011 12131415 16171819 20212223 24252627 2829

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

3031

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

(1)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

I1

I2

I3

I4

I5

I6

I7

I8

I9

O1

IO2

IO3

IO4

IO5

IO6

IO7

O8

I10

Copyright 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e

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211H Fall 2010

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211H Fall 2010

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211H Fall 2010

Last Years Test2, Another test is onWebsite/Handouts/test2Short.pdfLast Years Test2, Another test is onWebsite/Handouts/test2Short.pdf

1.1. Carry LookaheadCarry Lookahead

2.2. 4 bit multi4 bit multi--function registerfunction register

3.3. Sequential design problemSequential design problem

4.

4. State DiagramState Diagram

transition tabletransition table

5.5. Transition tableTransition table excitation tableexcitation table

6.6. XilinxXilinx

7.7. Missing?Missing?

a. ROM: how they work?

b. Design ROM to implement circuit (diagram)

c. PLAs, PALS

d. ???

211Lec16-PLAs

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