2103003 White Paper ImprovingBTSclocking 101531

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Improving Clock Performance in Base StationsWhite Paper

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers' internal use. 1Document No.: PMC-2103003, Issue 1

Improving Clock Performance

in Base Stations

White Paper

by Mark Hiebert and Ben Lake

Issue No. 1: June 2011

PMC-Sierra, Inc.

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Legal Information

Copyright

Copyright 2011 PMC-Sierra, Inc. All rights reserved.

The information in this document is proprietary and confidential to PMC-Sierra, Inc., and for itscustomers internal use. In any event, no part of this document may be reproduced or

redistributed in any form without the express written consent of PMC-Sierra, Inc.

Disclaimer

None of the information contained in this document constitutes an express or implied warranty

by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of anysuch information or the fitness, or suitability for a particular purpose, merchantability,

performance, compatibility with other parts or systems, of any of the products of PMC-Sierra,Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaimsall representations and warranties of any kind regarding the contents or use of the information,

including, but not limited to, express and implied warranties of accuracy, completeness,merchantability, fitness for a particular use, or non-infringement.

In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental orconsequential damages, including, but not limited to, lost profits, lost business or lost dataresulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has

been advised of the possibility of such damage.

Trademarks

For a complete list of PMC-Sierras trademarks and registered trademarks, visit:http://www.pmc-sierra.com/legal/

Other product and company names mentioned herein may be the trademarks of their respectiveowners.

Patents

The technology discussed in this document may be protected by one or more patent grants.Downloa

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Abstract

As base station architectures shift towards multi-standard, multi-carrier Remote Radio Heads

and Active Antenna Modules, system designers are being challenged to reduce cost, power, andarea while increasing the number of clocks in the system and still meeting all standards-basedrequirements. To meet stringent clock specifications, currently deployed systems often includeadditional filtering or costly discrete clocking components, which is often a sub-optimal trade-off between system performance and circuit cost, area, and power consumption.

A key issue related to accurately specifying clock performance levels is the edge sensitivenature of sampled systems, where a sampled system is defined as any device where the outputsignal phase alignment is related to the phase of the clock which samples the input signal.

ADCs, DACs, LO synthesizer clock inputs and hard-switching mixers are all examples ofdevices which are sensitive to the noise at the clocks threshold crossing; therefore it is essentialto accurately measure the phase noise at the threshold crossing of the clock signal. A result ofthe sampling process is that aliasing occurs on the clock signal and all of the noise associatedwith that clock at the threshold crossing. Frequency planning is an important technique to avoid

selecting frequencies at which aliased spurs fall into the wanted frequency band. Use of propermeasurement techniques such as observing the spectral content of a clock following a highquality limiting amplifier to isolate phase noise at the threshold crossing enables systemdesigners to more accurately account for spurious noise and aliasing effects in sampled systems.

In addition, careful phase planning of system clocks can significantly reduce spurious couplingbetween clocks.

This white paper reviews the basic concepts of phase noise, contrasting continuous with

discretely sampled phase noise, discusses frequency aliasing, and explores phase planningtechniques that aid designers to address high-density clocking requirements in next-generation

base station systems. A clocking architecture that utilizes these techniques is finally presented asan example of how the clocking requirements for a 2T2R base station are addressed by a singlehigh-density clocking solution.

About PMC

PMC-Sierra, the premier Internet infrastructure semiconductor solution provider, offers itscustomers technical and sales support worldwide through a network of offices in NorthAmerica, Europe, Israel and Asia. PMC-Sierra provides semiconductor solutions for Enterpriseand Channel Storage, Wide Area Network Infrastructure, Fiber To The Home, and Laser

Printer/Enterprise market segments. The Company is publicly traded on the NASDAQ StockMarket under the PMCS symbol. For more information, visitwww.pmc-sierra.com.

About the Authors

Mark Hiebert is a Leader in the Mixed Signal Design Group at PMC-Sierra.

Ben Lake is a Senior Applications Engineer in the Broadband Wireless Division at PMC-Sierra.

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Revision History

IssueNo.

Issue Date Details of Change

1 June 2011 Initial Release.

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Table of Contents

Legal Information ........................................................................................................................... 2

Copyright ................................................................................................................................. 2Disclaimer ............................................................................................................................... 2

Trademarks ............................................................................................................................. 2

Patents .................................................................................................................................... 2

Abstract ................................................................................................................................... 3

About PMC .............................................................................................................................. 3

About the Authors ................................................................................................................... 3

Revision History ............................................................................................................................. 4

List of Figures ................................................................................................................................ 6

1 Introduction ............................................................................................................................. 7

2 Continuous-Time Phase Noise Defined .................................................................................. 7

3 Discrete-Time Phase Noise Defined ....................................................................................... 9

4 Implications of Discrete-Time Phase Noise .......................................................................... 11

5 Jitter versus Discrete-Time Phase Noise .............................................................................. 13

6 Clock Signal Evaluation Considerations ............................................................................... 14

7 Emulating a Clock Receiver .................................................................................................. 17

8 Clock Phase Alignment ......................................................................................................... 19

9 Increasing Clock Density to Address Evolving System Requirements ................................. 22

10 Conclusion ............................................................................................................................ 23

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List of Figures

Figure 1 Continuous-time Phase Noise ......................................................................................... 8

Figure 2 Discrete-time Phase Noise ............................................................................................ 10Figure 3 Discrete-time Phase Noise Represented as a Continuous-time

Process .................................................................................................................... 11

Figure 4 Measured Result of a 153.6MHz Clock with Aliased Spurious Couplingfrom a nearby 491.52MHz Clock ............................................................................. 12

Figure 5 Clock Signals Containing Modulated Noise ................................................................. 14

Figure 6 System Clocks with Amplitude Modulated or Phase Modulated Noise ....................... 16

Figure 7 Limiting Amplifier Emulating a Clock Input .................................................................... 18

Figure 8 Example Measurement Setup using a Limiting Amplifier ............................................ 18

Figure 9 Clock Phase Alignment Simulation ............................................................................... 20

Figure 10 Spurious Coupling Between Clock Outputs versus Phase Alignment ........................ 21

Figure 11 RRH 4T4R Clocking Example using PM7520 SyntheCLK ......................................... 22

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1 Introduction

Clock phase noise is a topic that has been discussed extensively. A pure sine wave is commonly

used in examples to represent the clock with an associated amount of phase noise. However,modern radio systems use advanced digital and analog circuits to sample, create, and

synchronize various analog signals. The clock inputs to these devices are often only sensitive tothe threshold crossing of the clock signals.

This white paper discusses the clock sensitivity of these devices to show that the clock receiversof most devices effectively sample the phase noise at the rising threshold crossings. Consideringa clock signal where the clock phase information is only sampled once per cycle challenges

some of the traditional assumptions about clock measurement techniques using RF testequipment.

The discrete, sampled nature of the clocks phase information detected by these devices has

several implications in the system, including aliasing of spurious signals and variation incoupling between signals depending on clock phase alignment. Minimizing these effects oncritical clock signals can improve clock performance.

2 Continuous-Time Phase Noise Defined

Phase noise is the angular error present in periodic signals. For example the sinusoidal signal

)(ts includes a continuous-time phase noise term )(tnoisej .

)(2sin)( ttfts noiseCLK jp +=

The periodic signal is often illustrated as a rotating vector with a rotation frequency offCLK,where its instantaneous angle is given by )(2 ttf noiseCLK jp + , as shown in Figure 1below.

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Figure 1 Continuous-Time Phase Noise

NOISE(t)

2*fCLKt

In RF applications, phase noise is often considered a continuous-time process. For example, if

an upconverting mixer is implemented as an ideal analog multiplier, and the LO signal issinusoidal and is defined as having a continuous-time phase noise process.

Considering the mathematical representation of an analog upconverting mixer,

)(2sin)()( _ ttfVtVts noiseLOLOLOIFRFOUT jp +=

it is apparent that the phase noise of the LO signal affects the RF output at any time t. The

output of this mixer is dependent on the continuous-time phase noise process. Referring to

Figure 1, at every point in the LO signal vectors rotation, a disturbance in the ideal phase of the

LO signal directly impacts the characteristics of the output signal, sRFOUT(t).

However, if a device is sensitive only to the threshold crossing of a clock signal, this concept ofcontinuous-time phase noise is insufficient. For example, if an upconverting mixer isimplemented with an LO amplifier that amplifies and clips its incoming LO signal, the output of

the mixer would not be dependent on a continuous-time phase noise process affecting its LOinput signal. Ideally, this type of mixer would convert a LO input signal into a clipped signal

taking values of +/-1, as illustrated by the mathematical representation of a LO-clippingupconverting mixer:

)(2sin)()( _ ttfVsigntVts noiseLOLOLOIFRFOUT jp +=

Where ( ) 1-=xsign if 0x and ( ) 1=xsign if 0>x

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For this type of device, the value of )(_ tnoiseLOj only affects the RF output signal at the instants

where the LO phase argument )(2 _ ttf noiseLOLO jp + takes values of pn . Referring again to

Figure 1, only at the points in the LO signal vectors rotation where the vector crosses the

horizontal axis does a disturbance in the ideal phase of the LO signal impact the characteristicsof the output signal.

The fact that the LO-clipping mixer is insensitive to the phase of its LO signal except at distinct

points in the LO period has important implications for how we need to think about phase noiseto get an accurate picture of its effect on the devices output.

3 Discrete-Time Phase Noise Defined

Many real world devices are sensitive to the phase of their clock signal only at thresholdcrossing points, including:

Data converters, such as Digital-to-Analog Converters (DACs) and Analog-to-DigitalConverters (ADCs),

LO synthesizers which employ a digital phase/frequency detector in the PLL, and

Mixers where the LO signal is clipped or hard-switching.

Therefore, almost all major functional blocks within the RF and baseband sections of a base

station system are sensitive to phase noise only at discrete moments in each clock cycle, at thethreshold crossing of the clock.

Consider devices clocked by a sinusoidal signal )(tswith continuous-time phase noise

[ ])(2sin)( ttfts noiseCLK jp +*=

SinceCLK

CLKf

T1

= , the signal can also be written as

+

*= )(

2sin)( t

T

tts noise

CLK

jp

If the device was only sensitive to phase of the clock at the instant it rises through the zero

threshold, its clock receiver would detect a clock event every time the phase argument crosses

n*2.

pjp

2*)(2

ntT

tnoise

CLK

=

+

*

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To meaningfully define the phase noise for these devices which are only sensitive to the clockphase during specific instants in the clocks period (e.g. the zero threshold crossing), we must

acknowledge that the phase noise is also only detected (or sampled) at these discrete instants.The phase noise detected by this device can be accurately represented as a discrete sequence ofsamples of the original continuous-time phase noise process. The phase noise of the nth clock

period is given by:

[ ] )( CLKnoisenoise nTn jj @

where this relationship is approximate. The phase noise is not sampled at exactly CLKnT

because the phase noise process itself disturbs the sampling instant, but this approximation doesnot affect the following discussion.

Continuous-time phase noise and the resultant discrete sequence of phase noise samples areillustrated in the following figure, where the discrete-time phase noise is assumed to be

measured at the rising zero threshold crossing.

Figure 2 Discrete-Time Phase Noise

noise[0] noise[1] noise[2] noise[3]

Clock Signal

Continuous Time

Phase Noise

Discrete Time

Phase Noise

Samples

Clock Phase Noise, noise(t)

Clock Amplitude, s(t)

time

time

noise[4] noise[5]

Note that the phase noise for the nth

clock period is equal to the phase error that impacted the nth

rising threshold crossing of the clock, [ ]nnoisej . The sequence [ ]nnoisej is the discrete-time

phase noise representation of the original clock signals continuous-time phase noise, asobserved at the instants of the clock signals rising edge threshold crossing. It has a sample rate

offCLKif the phase of the clock signal is sensed once per clock cycle.

We can look at this discrete-time sequence of phase noise measurements as a representation of

the phase noise seen by this sampled system. This is shown graphically in Figure 3below.Downloa

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Figure 3 Discrete-Time Phase Noise Represented as a Continuous-Time Process

noise[0] noise[1] noise[2] noise[3]

Clock Signal

Phase Error

Discrete Time

Phase Noise

Samples

Clock Phase Noise, noise(t)

Clock Amplitude, s(t)

time

time

noise[4] noise[5]

The resultant phase noise of each discrete-time sample can be envisioned as constant over eachsample period. The information in the samples is limited by the Nyquist bandwidth of the

sampling clock.

4 Implications of Discrete-Time Phase Noise

In sampled systems, system designers are conscious of the implications of moving from the

domain of continuous-time signals to sampled signals. For example in an ADC, aliasing occurswhen continuous-time signals are sampled: any signal content at frequencies above half thesample frequency, fSAMPLE, will alias into the discrete-time spectrum of the sampled outputsequence. The discrete-time Power Spectral Density (PSD) of the sampled values is capturedwithin a frequency band from DC to fSAMPLE/2. Aliasing and Nyquist bandwidth concepts also

apply when considering the characteristics of discretely sampled phase noise.

Aliasing effects, when considering phase noise as a discrete-time sampled sequence, can beillustrated by considering a 100MHz sinusoidal clock driving a system sensitive only to the

rising threshold crossing, but including a continuous-time phase noise process with a frequencyof 501MHz:

)5012sin(2sin)( tMHzAtfts PhNCLK **+= pp

The phase noise present in each of the clocks rising threshold crossings is:

)100/1*2sin(

)100/1*25*2sin(

)100/1*2100/500*2sin(

)100/5012sin(

)(

MHzMHznA

MHzMHznnA

MHzMHznMHzMHznA

MHznMHzA

nTn

PhN

PhN

PhN

PhN

CLKnoisenoise

*=

*+*=*+*=

**=

@

p

pppp

p

jj

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From the above equations, it is apparent that the phase disturbances as observed on the clocksthreshold crossings have a periodicity of 1MHz. The 501MHz frequency content in the

continuous-time phase noise process aliases to 1MHz when the phase of the clock is onlyobserved at a specific instant of the clock period.

A practical example that highlights this aliasing effect is to consider a 153.6MHz clock signalwith a nearby 491.52 MHz clock signal coupling on to this clock. If the 153.6MHz clocksignals phase is only observed once per clock period, it is nonsensical to define spuriouscontent at 491.52MHz offset in the sequence of discrete-time phase noise samples. 491.52MHzis above the 153.6MHz/2 bandwidth limit for the discrete-time phase noise in this example

system. If the 491.52MHz clock signal couples and affects the phase of the 153.6MHz clocksignal at the threshold crossings, it would result in a 30.72MHz offset (491.52MHz 4*153.6MHz/2 = 30.72MHz) periodic phase disturbance in the discrete-time phase noisespectrum detected on the 153.6MHz clock signal (after being sampled by the clock input). Byusing a hard clipping / limiting amplifier to emulate an edge-sensitive clock input and driving it

with both a 153.6MHz wanted clock signal and a 491.52MHz unwanted coupled signal, an

example of this effect was measured in a lab setup and captured below in Figure 4.

Figure 4 Measured Result of a 153.6MHz Clock wi th Al iased Spurious Coupl ing f rom anearby 491.52MHz Clock

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The above example shows how critical it can be to be aware of aliasing effects when selectingthe clock frequencies within a system. Consider another example system where a 153.6MHz

ADC clock and a 614.4MHz DAC clock are used. The ADC clock input detects clock edges,meaning that it effectively detects a sequence of discrete-time phase noise samples with a rate of153.6Msps. All power in this sequence can be displayed in the frequency range DC to153.6MHz/2 and spurious content at the ADC clocks threshold crossing location will aliasdown into this frequency range. Therefore any spurious coupling from the DAC clock

(614.4MHz mod 76.8MHz = 0) will alias down to DC and have no impact on the phase noisecharacteristics of the clock information detected by the ADC.

5 Jit ter versus Discrete-Time Phase Noise

When making the transition from continuous-time phase noise to the disturbances in thresholdcrossing events on a clock signal, the disturbances in the threshold crossing are generallyreferred to as jitter and are represented in units of time (i.e. seconds). However, in RF

applications, representing the clock disturbances as phase noise, measurable in dBc orradians, can be a more appropriate choice of units and terminology; this is true even where theconcept of continuous-time phase noise is no longer an accurate representation. Describing

phase noise in units of time can be limiting in the context of performance impacts in an RFsignal chain.

For example, if a LO-clipping RF mixer is clocked by a 1GHz sine wave with threshold

crossings that are modulated by 50fs with a frequency of 1MHz,

[ ]( ))*1*2sin(*1.0*1*2sin)()( tMHztGHzVsigntVts LOIFRFOUT pp +=

In this application, it is meaningful to note that the discrete-time phase noise sequence has a

1MHz periodic content with an RMS phase noise power of

uRadfsGHz 314)50(*)1(**2 =p

which can also be expressed as

dBcuRad 70)314(log*20 10 -= .

Note that the above result is the double sideband phase noise power. The single sideband power,which is more commonly used in lab measurements, is half of that value

dBcdBdBcPower SSBPhaseNoise 73370_ -=--= .

It is also important to observe that phase noise power varies with clock frequency, for the same

amount of timing jitter. In the above example, if the 1GHz sine wave was replaced with a100MHz sine wave, the same disturbance would have a phase noise of 31.4uRad and theresultant single sideband phase noise power would be -93dBc. Therefore, it is essential toconsider the operating frequency of each clock in the system when defining spurious

performance specifications for those clock outputs.

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The LO phase modulation power, in radians or dBc, gives specific insight into the spectralpurity of the RF output signal. In this application, it is much less meaningful to note that the

periodic timing jitter on the clipped LO signal has an RMS level of 50fs. No straightforwardinsights into the spectral purity of the RF output signal can be derived from this description ofthe jitter on the clock edge crossings, expressed in units of time.

The practicality of using units of radians or dBc to represent phase noise characteristics appliesfor RF mixers, but also for other clock inputs in an RF signal path, such as ADC/DAC clockinputs or digital phase/frequency detectors in RF PLLs. For this reason, the followingdiscussion will continue to focus on the concept of threshold crossing disturbances as discrete-

time phase noise, inferring that clock disturbances are represented in units of phase.

6 Clock Signal Evaluation Considerations

Suppose that two identical systems were each clocked by a sinusoidal clock signal, one clock

containing amplitude noiseAnoise(t) and the other clock containing phase noise )(tnoisej impairments:

**+=

CLK

noiseINPUTT

ttAts

p2sin))(1()(1

+

*= )(

2sin)(2 t

T

tts noise

CLK

INPUT jp

It is important to note that when the continuous-time power spectral densities of these two clocksignals are observed, one clock with only phase modulation and one clock with only amplitudemodulation, identical spectral power distributions are detected if the modulation power levels

are equal. Figure 5presents an example of similar amounts of amplitude modulated noise andphase modulated noise on the same clock displaying similar power spectral densities.

Figure 5 Clock Signals Containing Modulated Noise

Amplitude Modulated Clock Signal Phase Modulated Clock Signal

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In some situations both the amplitude noise and phase noise of a clock signal are relevant. Theideal analog upconverting mixer presented in Section 2 is one of those cases. Conversely, many

sampled systems are sensitive to only the clock phase at the threshold crossing of the clocksignal. In these sampled systems, the clock signal after the clock receiver can be thought of as a

square wave, where the clock receivers output )(ty depends on the input )(tx in the manner

described below

( ))()( txsignty =

Where ( ) 1-=xsign if 0x and ( ) 1=xsign if 0>x

For each clock input signal passing through a receiver such as this, the input clock signal with

only amplitude noise would produce no deviations in the clock receivers output signal becausethe amplitude noise doesnt affect the position of the signals threshold crossing. However, the

input clock signal with only phase noise would produce deviations in the clock receivers output

signal because the phase noise )(tnoisej shifts the location of the signals zero thresholdcrossing.

This behavior has been modeled in Matlab, simulating the time domain waveforms, the signalspower spectral density, and the resultant phase noise (jitter) of the clock threshold crossings.The simulation results for both a clock waveform containing only amplitude modulation and a

clock waveform containing only phase modulation are shown in Figure 6.

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Figure 6 System Clocks w ith Ampli tude Modulated or Phase Modulated Noise

Amplitude Modulated Clock Signal Phase Modulated Clock Signal

In order to illustrate the fundamental difference between these sources of noise, the amount of

modulation used in the above simulation is much larger than the noise in real systems.Measuring the spectral content of the actual clock signals on a continuous-time instrument willshow identical results, but the measurement provides no insight into the power spectrum of the

phase information on the clock at the threshold crossings. Analyzing the power spectral densityof the discrete-time samples of clock phase at the threshold crossings (jitter) confirms that an

ideal clock buffer will only pass through noise that affects the phase of the clock thresholdcrossings.

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Now that we have established that we are primarily concerned with the clock phase noise onlyat the threshold crossing in sampled systems, it is essential to use techniques in the laboratory

that can effectively measure that phase noise in isolation and then develop solutions to minimizethose specific sources of noise. Emulating a system that is sensitive to only the clock phase atthe threshold crossing using a high gain limiting amplifier is an effective way to enablecontinuous-time test equipment to effectively see the same types of phase noise that areencountered in these sampled systems.

7 Emulating a Clock Receiver

Measurement instruments such as Spectrum Analyzers are continuous-time instruments and

therefore directly measuring a clock signal will not be indicative of the performance when thatclocks phase information is sampled by a system which is only sensitive to the clock thresholdcrossing. In order to determine the impact of clock impairments for systems that rejectamplitude-modulated noise on clock signals and are sensitive to phase-modulated noise at the

clock threshold crossing, it is necessary to use a clock measurement methodology that behavesin a similar manner.

A high-gain, high-performance buffer device, or limiting amplifier, can be used to condition theclock signal before measurement. Passing the clock signal through a limiting amplifier

effectively clips the clock signal such that amplitude modulation is removed but phasemodulation near the threshold crossing is preserved. The limiting amplifier closely mimics the

functionality of the clock input of a sampled system, shown below in Figure 7, enabling precisemeasurement of phase noise and spurious coupling due to phase modulation on a continuous-

time measurement instrument, such as a Spectrum Analyzer. The spectral content at the outputof this limiting amplifier is representative of the spectral content in the discrete-time samples of

phase noise that would be detected by a device that is sensitive to only the clock threshold

crossing.

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Figure 7 Limi ting Amplif ier Emulating a Clock Input

It is essential to choose a high-performance limiting amplifier with a high bandwidth and lownoise characteristics so that the clock signal being measured is not significantly degraded. PMC-Sierra has designed a limiting amplifier test board using the clock input buffer of a PM7520SyntheCLK device. An example of a limiting amplifier being used to measure the spuriouscontent of the clock source at the clock threshold crossings is shown in Figure 8.

Figure 8 Example Measurement Setup using a Limiting Amplif ier

Differential Limiting

Amplifier

SpectrumAnalyzer

PM7520 SyntheCLK orother high-performance

clock source

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The limiting amplifier enables measurement of spurious coupling and aliasing effects equivalentto the sampling process that occurs at the clock input of sampled systems.1 If the clock source

was connected directly to the Spectrum Analyzer, then the measurement would report theaverage spectral content of the clock signal, including spectral content that occurs away from

the threshold crossing; there would be no way to discriminate between the effects that disturbthe threshold crossing (phase modulated noise), and those that do not (amplitude noise). Notethat the limiting amplifier also provides the required differential to single-ended conversion,

which ensures that common-mode noise is removed, enabling an accurate measurement withsingle-ended test equipment while still providing the expected differential termination for theclock output being measured. This is an appropriate measurement technique because typically adifferential clock receiver would be used in the actual application.

8 Clock Coupling Depends on Phase Alignment

System clocks generally have very fast edge rates and appear very similar to square waves.

Thus, signal disturbances near the threshold crossing will occur as phase modulated noise, whiledisturbances away from the threshold crossing will occur as amplitude modulated noise. Asdiscussed in Section 6, noise that does not affect the clock signal near the threshold crossingwill not be detected at the clock receiver. Therefore, if we consider the example of a clockingdevice with multiple clock outputs, high-speed switching transients caused by other clockoutputs can couple onto a clock output that has very strict phase noise requirements. It is

possible to minimize the phase disturbance to the threshold crossing of the desired output clockby adjusting the phases of the other output clocks.

Figure 9 shows a simulation demonstrating a lower frequency clock coupling onto a higherfrequency clock with the phase of the lower frequency clock being shifted in phase. Note thatthe right side of the figure shows the discrete-time Power Spectral Density (PSD) of this clock

signal, where phase is measured only at the threshold crossing.

1Note that an ideal limiting amplifier would include a divide by 2 circuit internally, such that only the

rising edge is measured.

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Figure 9 Clock Phase Alignment Simulation

This effect in the simulation is quite dramatic, but in real systems the effect of phase alignment

is much more complex. Multiple interfering clock sources, Printed Circuit Board (PCB) tracepropagation delays, trace impedance mismatches at various frequencies, etc. all cumulate into ameasured effect that correlates closely to theory, but is not as predictable. Consider a practicalexample using the PMC-Sierra PM7520 SyntheCLK device configured for a 76.8 MHz clockoutput and 153.6 MHz clock output. The 153.6 MHz clock output is measured for spurious

coupling from the 76.8 MHz clock output, and the 153.6 MHz output is adjusted through 16

possible output phase alignments to find the best isolation between clock outputs, is shownbelow in Figure 10.

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Figure 10 Spurious Coupl ing Between Clock Outputs versus Phase Alignment

/2 3/2 2

The PMC-Sierra PM7520 SyntheCLK device features 30 clock outputs where each output has adeterministic phase relationship to the other outputs and independent, glitchless phase control.This enables system designers to conveniently optimize phase alignment without the need forcomplex routing or additional circuitry to account for multiple clock buffers. Optimizing the

phase alignment of all clock outputs within a given frequency plan can significantly improve the

isolation between various clock outputs, resulting in better spurious performance on criticalsystem output clocks such as transmit path DACs and receive path ADCs.2

2Please contact PMC-Sierra Applications Support ([email protected]) for phase-optimized

performance results for specific frequency plans.

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9 Increasing Clock Density to Address Evolving SystemRequirements

The shift in Base Station architecture towards multi-standard, multi-carrier Remote RadioHeads and Active Antenna Modules is dramatically increasing the number of high-performanceclocks required per system. PMC-Sierras PM7520 SyntheCLK addresses this need by

providing a single, highly-integrated solution with a 30-output dual-PLL clock synthesizer.SyntheCLK features include:

Jitter attenuation of the recovered clock;

A programmable system clock synthesizer unit capable of providing output clocks up to

1.583 GHz;

30 low phase noise clock outputs, each with independent frequency control, output phase

control, and glitch-free synchronization.

An example of the PM7520 SyntheCLK being used in a 4 Transmit 4 Receive (4T4R) Remote

Radio Head application is shown in Figure 11.

Figure 11 RRH 4T4R Clock ing Example us ing PM7520 SyntheCLK

Tx DAC

Tx Observation ADC

Rx ADC

Envelope Tracking DAC

DAC

ADC

ADC

Tx LO

Rx LO

DAC

VCXO

SerDes

3

4

4

4

2

4

4

Observation LO

2

FPGA / ASIC

SerDes Recovered

Clock

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10 Conclusion

Clock signals can include amplitude-modulated noise or phase-modulated noise. The

continuous-time representation of the power spectral densities of signals with either of theseimpairments can be indistinguishable. When a clock signal is sampled by an input that is only

sensitive to the threshold crossing, the phase noise is also sampled at those threshold crossinginstants; noise on the clock signal at all frequencies above fSAMPLE/2 can alias down into thisregion. Careful frequency planning can help to ensure that no unwanted signals will alias onto a

critical clock signal.

Measurement techniques that analyze the clock perturbations at the threshold crossing give a

more accurate representation of the phase noise in the resultant sampled signal. Simulations andlab observations match the theory that a limiting amplifier closely mimics the functionality of aclock input. By removing the amplitude modulated noise from a clock signal and by beingsensitive only to the threshold crossing position of the input signal, the limiting amplifier

enables measurement of only the phase noise at the threshold crossing. The limiting amplifierallows system designers to measure and analyze the aliasing effects that are seen in sampledsystems.

The sensitivity of sampled systems to phase modulation, but not to amplitude modulation,

suggests that phase optimization of key clocks can significantly reduce spurious couplingbetween output clocks, thereby improving the performance of the clock signals. This enablessystem designers to deliver high-performance, high-density base station architectures which areclocked from a single device. PMC-Sierras PM7520 SyntheCLK provides the required

functionality and high-level of integration to enable next generation base station designs thatreduce circuit cost, area, and power consumption while meeting stringent performancerequirements.

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Contacting PMC-Sierra

PMC-Sierra

8555 Baxter PlaceBurnaby, BCCanada V5A 4V7

Tel: +1 (604) 415-6000Fax: +1 (604) 415-6200

Document Information:[email protected] Information:[email protected] Support:[email protected] Site:http://www.pmc-sierra.com

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mailto:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]://www.pmc-sierra.com/http://www.pmc-sierra.com/http://www.pmc-sierra.com/http://www.pmc-sierra.com/mailto:[email protected]:[email protected]:[email protected]

2103003 White Paper ImprovingBTSclocking 101531

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