2065-14 Advanced Training Course on FPGA Design...
Transcript of 2065-14 Advanced Training Course on FPGA Design...
2065-14
Advanced Training Course on FPGA Design and VHDL for HardwareSimulation and Synthesis
Nizar Abdallah
26 October - 20 November, 2009
ACTEL Corp.2061 Stierlin Court Mountain ViewCA 94043-4655
U.S.A.
FPGA Architectures & VHDLIntroduction to FPGAs & FPGA Design Flow
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FPGA Architectures & VHDL
Introduction to FPGAs & FPGA design flowsIntroduction to SynthesisThe VHDL hardware description languageDesign verification, validation, and testing
Programmable logic & FPGA architecturesActel’s SoC Flash FPGA architecturesCo-design & co-verification of HW/SW embedded systems
Emerging technologies and future opportunities.
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Motivation
High integrationBasic: memory, logic, I/OsEven more: PLL, DSP, A/D, D/A, clock oscillator…
Accelerated product’s time-to-marketFlexibility needs
Design skillsSystem levelDSP algorithmsSW/HW co-designHDL modelingDesign methodologyProject management
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Digital Logic Technologies
Digital Circuit Implementation
Full Custom Semi-Custom
Standard Cell
Gate Arrays
FPGA
ASICsProgrammableLogic
SPLD CPLD Structured ASICs
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What’s a FPGA?
A simplistic old definition:a high capacity programmable logic deviceAn array of programmable basic logic cells surrounded by programmable interconnectsCan be configured (programmed) by end-users (field-programmable) to implement specific applicationsCapacity up to multi-millions logic gates and speed up to 500MHzPopular applications: prototyping, on-site hardware reconfiguration, DSP, logic emulation, network components, etc…
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CPLDs versus FPGAs
FPGAs
Larger Capacity
Complex Architecture
More Registers
CPLDs
More Predictable Timing
Simple Architecture
Fewer Registers
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Basic FPGA Block Diagram
Generic FPGA Architecture
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Rich FPGA Block Diagram
Rich FPGA Architecture
1. Integrated ADC2. Low-Power Support3. Embedded Flash Memory4. Advanced I/O Standard5. Charge Pumps6. Analog Quads7. Flash FPGA VersaTile8. SRAM and FIFOs9. Integrated Oscillators
10. Routing Structure11. JTAG
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ARMCortex-M1
ΔΦαηφλμϕψΓ∀234567∞ΔΦαηφλμϕΔΦαηφλμϕψΓ∀234567∞ψΓ∀234567∞
DESIGNER’S DREAM
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Design Principles
HierarchyDivide & conquerSimplification of the problem
RegularityDivide into identical building blocksSimplifies the assemblage verification
ModularityRobust definition of all components (entity)Allows easy interfacing
LocalityEnsuring that interaction among modules remains localMakes designs more predictable and re-useable
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Step 1: Specifications
Put down the circuit conceptEasy verificationA reference manual for communication
Between peopleBetween people and computers
How?No Ordinary languageAccurate languageA language that can be simulated
Put down the requirementsTiming budgetPower budgetArea budgetFinancial budget
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Step 2: Partitioning
Divide and conquer strategyVery difficult step: Relays on the know-how of the designerMain idea: To split into several small parts
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Step 3: Implementation
Simplified FPGA design implementation flow
DesignEntry
Logic Synthesis
P&R(Layout) Programming
Verification
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Step 4: Assemblage
Hierarchical wayStart from the lowest levelFinal product validation is now possible
Compare to original specificationsSimulateOn-board verification
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Design Abstraction & Design Domains
Allow dealing with design complexity
BehavioralBehavioral
AlgorithmicAlgorithmic
Abstraction LevelsAbstraction Levels Design DomainsDesign Domains
How it works
How it is connected
How it is implemented
FSMFSM
RTLRTL
CGateGate StructuralStructural
Layout Physical
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FSM Abstraction Level
Finite State Machine
Controller part of a digital design
Internal states
State changes driven by:Status informationClock and other external inputs...
E0E0
E1E1
E2E2
E3E3
ck, ...
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RTL Abstraction Level
Register Transfer LevelRegisters connected by combinatorial logicVery close to the hardware
REGISTERSREGISTERS
COMBINATIONALCOMBINATIONALLOGICLOGIC
DOUTDOUTDINDIN
CLOCKCLOCK
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Gate Abstraction Level
A gate net-list describing instantiation of models
CINCINAABB
COUTCOUT
SUMSUM
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Introduction to FPGAs & FPGA design flowsIntroduction to SynthesisThe VHDL hardware description languageDesign verification, validation, and testing
Programmable logic & FPGA architecturesActel’s SoC Flash FPGA architecturesCo-design & co-verification of HW/SW embedded systems
Emerging technologies and future opportunities.
FPGA Architectures & VHDL
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What’s Synthesis?
The process of converting a design from one abstraction level into a lower abstraction levelLogic synthesis is mapping an RTL description into a specific target technologyIncludes an optimization step for:
Faster speedSmaller area
Synthesis flow involves multiple stepsState minimizationState assignmentLogic optimizationTechnology mappingTiming optimization
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Logic Synthesis
ENTITY dec2to4 isPORT(A,B,enable:in BIT;
vdd,vss,vdde,vsse:in BIT;Y:out bit_vector(0 to 3));
end dec2to4;
architecture dflow of dec2to4 is
signal a_bar,b_bar:bit;signal a1,a2,a3,a4:bit;
begina_bar <= not a;b_bar <= not b;
ENTITY dec2to4 isPORT(A,B,enable:in BIT;
vdd,vss,vdde,vsse:in BIT;Y:out bit_vector(0 to 3));
end dec2to4;
architecture dflow of dec2to4 is
signal a_bar,b_bar:bit;signal a1,a2,a3,a4:bit;
begina_bar <= not a;b_bar <= not b;
CombinationalLogic Synthesis
Gate Netlist =Gate Level
Structural Description
SequentialLogic Synthesis
Gate Netlist =Gate Level
Structural Description
ENTITY adder isPORT(A,B,enable:in BIT;
vdd,vss,vdde,vsse:in BIT;ck: in bit;Y:out bit_vector(0 to 3));
end dec2to4;
architecture dflow of adder is
signal regstr:reg_vector(0 to 3)register;
signal a1,a2,a3,a4:bit;
begin
ENTITY adder isPORT(A,B,enable:in BIT;
vdd,vss,vdde,vsse:in BIT;ck: in bit;Y:out bit_vector(0 to 3));
end dec2to4;
architecture dflow of adder is
signal regstr:reg_vector(0 to 3)register;
signal a1,a2,a3,a4:bit;
begin
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Optimization and Logic Synthesis
Involves multiple internal iterative steps
State Assignment
Technology Mapping
Placing & Routing
State DiagramMinimization
LogicMinimization
TimingOptimization
Dependence
Dependence
Dependence
WireLoadModel
FSM
Timing &Area
Constraints
SequentialBoolean Network
SequentialGate Network
Technology Cell Library
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1. Analyze the DesignCheck HDL syntax (is it synthesizable?)Locate referenced cells and librariesResolve parameters and definesDetect design top-level and hierarchy dependencies to determine mapping order
2. MappingBuild hierarchyInfer sequential elements: Flip-flops and latchesInfer operators: +, -, *, / (to blackbox models)Infer RAMsInfer Boolean logicInfer finite state machines
Synthesis Step-by-Step(Precision Synthesis Reference Manual, Chapter 4)
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Synthesis Step-by-Step (cont’d)
3. Pre-OptimizationComponent extraction – counters, RAMs, etc., are separated from generic logicUnused logic pruningBoundary optimization
Disconnect unused module portsMerge multiple ports connected
Constant propagation
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Synthesis Step-by-Step (cont’d)
Resource sharing
a1a2
select
resultif (select)
result = a1 + a2;else
result = a1 – a2;
if (select)result = a1 + a2;
elseresult = a1 – a2;
+
−
resulta1
a2
+/−
Before resource sharing After resource sharing
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Synthesis Step-by-Step (cont’d)
4. SynthesisMaps pre-optimized design into gates and/or FPGA look-up tablesImplements operatorsGenerates a complete, but non-optimal, netlist
5. OptimizationReorganizes logic to meet timing or area constraintsCalculates estimated interconnect delays using wire load modelResolves design rules such as
Maximum fanoutMaximum net capacitanceMaximum transition time on net
6. Synthesis result is a netlist (circuit) that satisfiesDesign rulesArea constraintsTiming constraints based on estimated delays
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Synthesis Vendors
Synopsys:Design CompilerFPGA Compiler II
Mentor Graphics:Exemplar Logic Leonardo SpectrumPrecision
Synplicity: SynplifySynplify Pro
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RTL Simulation
Simulates with a clock-cycle accuracyNo timing guarantee
Allows getting proper function of the design before jumping into details
We chose VHDL for this courseOne of the two popular languages used for hardware modeling
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VHDL-Vital ’95 Simulation Vendors
Synopsys:Scirocco
Mentor Graphics:Model Technology ModelSim
Cadence:NC-VHDL simulator
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References
Clive Maxfield,The Design Warrior's Guide to FPGAs:Devices, Tools, and Flows,Elsevier Science & Technology, 2004ISBN 0750676043
Smith, D. J.,HDL Chip Design,Doone Publications, Madison AL, 2001ISBN 0965193438
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References (cont’d)
K.C. Chang,Digital Systems Design With VHDL and Synthesis: An Integrated Approach,Wiley-IEEE Computer Society Press, First edition 1999ISBN 0-7695-0023-4
RC Cofer, Benjamin F. Harding,Rapid System Prototyping with FPGAs: Accelerating the Design Process,Newnes; Bk&CD-Rom edition, Sep. 2005ISBN 0750678666