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Master Thesis/Internship

Topic Guide

2013-2014


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Master Thesis/Internship Topics 2013-2014 1

Information.............................................................................................................................................................................................5

I.

CMOS Scaling (sub-22 nm) .................................................................................................... 6

Electrical evaluation and reliability assessment of local interconnects......................................................................... 6

Time-Dependent Dielectric Breakdown (TDDB) reliability of advanced CMOS gate dielectrics ........................ 6

Conductive Atomic Force Microscopy (C-AFM) for memory devices characterization ........................................ 7

Investigation and optimization of the electrical switching properties of scaled Ta2O5-based resistiveRAM memory cells .................................................................................................................................................................... 7

Reliability measurement and modeling of advanced BEOL interconnect .................................................................... 9

Evaluation of MgO as tunnel barrier in material stacks for MRAM applications ....................................................... 9

Thermo-compression bonding of fine-pitch micro-bumps for 3D integration of ICs............................................ 10

Study of chipping mechanisms in the dicing of thin silicon wafers .............................................................................. 10

Evaluation of photoresist outgassing for Extreme Ultraviolet Lithography .............................................................. 11

Deposition, characterization and application of dielectric films .................................................................................. 11

Development, characterization and application of pore sealing treatments ............................................................ 12

Hot carrier reliability on advanced logic/DRAM devices............................................................................................... 13

Investigation of advanced self-rectifying resistive switching memory cells (SRC-RRAM) ..................................... 14

Self-assembled monolayers as enabling technology for microelectronics ................................................................. 14

Advanced barrier CMP slurry development ..................................................................................................................... 15

Development of a ramped voltage BTI procedure for fast gate dielectric testing .................................................. 16

Compact modeling of advanced transistors ...................................................................................................................... 17

Modeling of temperature effects in advanced devices .................................................................................................... 17

Characterization and modeling of oxide border traps in Ge/III-V MOSFETs .......................................................... 18

Interface stability and reliability of high-mobility channel MOSFETs .......................................................................... 18

Carbon nanotube contacts: electrical characterization of CNT – damascene contacts ...................................... 19

Carbon nanotube growth and its catalyst nanoparticle deposition for future contact applications .................. 20

Bottom-up fill of deep holes with nanowires for future contact schemes ............................................................... 21

Energy spectrum of a cylindrical superlattice nanowire ................................................................................................ 21

Modeling of tunable band gap bilayer structures and devices ...................................................................................... 22

Design of an reliability characterization package for future generation high-performance CMOSransistors .................................................................................................................................................................................... 22

Design and simulation of on-chip circuits for parallel characterization of ultra-scaled transistors andSRAM cells for BTI reliability ................................................................................................................................................ 23

Graphene: device fabrication for optoelectronics ........................................................................................................... 24


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Graphene: device fabrication and characterization ......................................................................................................... 25

Plasma etching and characterization of novel materials for advanced patterning ................................................... 26

Low damage plasma processing: new materials for pore stuffing of 2.0 porous SiOCH materials .................... 26

Depth loading study in STI .................................................................................................................................................... 27

Advanced materials characterization using ion beam scattering ................................................................................. 28

Development of an accelerator based metrology application ...................................................................................... 29

Analysis of surface preparation for HV and UHV-SSRM ............................................................................................... 30

Active dopant characterization with micro-probes on advanced ultra-shallow high-mobility CMOSsemiconductor structures...................................................................................................................................................... 30

Development of a professional data analysis package for the micro-four point probe (M4PP) .......................... 31

Fundamentals of nanoscopic materials removal ............................................................................................................... 32

Strain characterization in advanced transistor structures using Raman .................................................................... 33

Non-destructive assessment of electrical properties of nanoscale probe tips ....................................................... 33

Nickel damascene process for MEMS ................................................................................................................................. 34

Defectivity monitoring of directed self-assembly ............................................................................................................ 35

Modeling of leakage in very high permittivity dielectrics for DRAM applications ................................................... 36

II. Heterogeneous Integration ................................................................................................. 37

Calibration of stress sensors for 3D-IC applications...................................................................................................... 37

III. Electronics for Healthcare and Life Sciences.................................................................... 38

Studying the function of neural circuits .............................................................................................................................. 38

Measurement of nanomaterial exposure in air ................................................................................................................ 39

Sensors for weight management and energy expenditure ............................................................................................ 39

How to detect dehydration with body area networks?................................................................................................. 40

Ionic fluidic study of metallic nanopores ............................................................................................................................ 41

Exploration of efficient electroporation protocols for intracellular recording of action potentials usingconfigurations of microelectrodes on chip........................................................................................................................ 41

Characterization of optical waveguides for optogenetic stimulation of in vitro and in vivo neurons ................... 42

High-density carbon nanotube electrodes for recording and stimulating electrogenic cells ............................... 42

Controlling light-matter interactions with plasmonic nanoantennas .......................................................................... 43

Engineering micro-structures for an optimized lens-free image .................................................................................. 44

Measuring electrical properties of cancer cells ................................................................................................................ 45

Gram staining using spectroscopy ....................................................................................................................................... 45

Gold nanostars for imaging and photothermal treatment of cancer .......................................................................... 46


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Antibody stabilizers for lateral flow assays........................................................................................................................ 46

Multiplex ligation polymerase amplification on chip ....................................................................................................... 47

TNFα detection in cell-culture medium of activated cells ............................................................................................ 47

Detection of single protein molecules in microwells on a digital lab-on-a-chip for point-of-carediagnostics .................................................................................................................................................................................. 48

Quantitative protein kinetics analysis using a refractometric LSPR sensor with an improved figure ofmerit ............................................................................................................................................................................................ 48

High quality-factor resonators in silicon nitride waveguides ........................................................................................ 49

Noise characterization and modeling of electrodes for in vivo and in vitro neural recording ............................ 50

Characterization of the light-sensitivity of CMOS-ICs for life science applications ............................................... 50

Multimodal integration of EEG and functional Near Infrared Spectroscopy for ambulatory brain imaging ..... 51

IV. Imaging Systems ....................................................................................................................53

Dynamic current steering in active pixel sensors ............................................................................................................ 53

V. Large Area Flexible Electronics .......................................................................................... 54

Degradation mechanisms in organic solar cells ................................................................................................................ 54

Organic photodetectors......................................................................................................................................................... 54

Contact resistance optimization in organic thin film transistors ................................................................................. 55

Bias stress stability study of a-IGZO TFTs ........................................................................................................................ 56

VI.

Wireless Communication .................................................................................................... 57

Radio-frequency communication with metal-oxide electronics on plastic ............................................................... 57

Algorithm and architecture co-optimizations for cost and power constrained signal processing system ....... 58

Digital assistance and digital frontend for deep submicron analog circuits............................................................... 58

Functional error mitigation schemes for latency-constrained wireless systems ..................................................... 59

VII. Energy...................................................................................................................................... 60

Hydrogen generation through water photoelectrolysis using semiconductor photoanodes............................... 60

Electrical characterisation of amorphous Si layers for solar cell applications .......................................................... 60

Dielectric ablation by laser processing for photovoltaic applications ........................................................................ 61

Development of assembly technology for next-generation c-Si PV modules .......................................................... 61


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Optimization of the bonding and detachment process of epitaxial silicon foils for application in thin-filmcrystalline silicon solar cells................................................................................................................................................... 62

Development and validation of an optical model for PV modules .............................................................................. 63

Degradation mechanisms in organic solar cells ................................................................................................................ 63

Large area coating of organic photovoltaic modules ...................................................................................................... 64

2D and 3D modeling of high efficiency back junction solar cells ................................................................................. 65

Photonic nanostructures for light management in novel thin silicon solar cells and modules............................. 65

VIII. Sensor Systems for Industrial Applications ..................................................................... 67

Opto-acoustic micro-resonator for sensing applications .............................................................................................. 67

MEMS-based compass: optimization of magnetometers enabled by MEMS resonators ........................................ 68

Cost-effective photonic sensor for point-of-care medical diagnostics ...................................................................... 69

IX.

Microelectronics Design ....................................................................................................... 70

Visualisatie van DfX analyse feedback in een elektronisch ontwerp .......................................................................... 70

Design van een 3.3V digitale standaardcelbibliotheek in UMC 180 nm technologie voorruimtetoepassingen .................................................................................................................................................................. 70

Ontwerp van radiatie-tolerante f lipflopsvoor imec’s DARE bibliotheken ................................................................ 72

Design prediction tool development for solder joint reliability for printed board assemblies, includingthe flexibility of components/boards................................................................................................................................... 73

X. NERF........................................................................................................................................ 74

Design and construction of automated environments to study spatial memory function in rodents ............... 74

Closed-loop real-time read out and control of memory processing in behaving rats ........................................... 74

Scale-space based segmentation and identification of cells in microscopic images ................................................. 75

Optogenetic dissection of dopamine function for learning from reward and punishment ................................... 76

Using superparamagnetic nanoparticles as force actuators in cells and tissues....................................................... 76

Design, prototyping and testing of miniaturized brain implants .................................................................................. 77

Inferring population network dynamics from cellular imaging data in behaving animals ....................................... 78


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Information

Students from universities and engineering schools can apply for a master thesis and/or internship project at imec.Imec offers topics in engineering and (industrial) sciences in different fields of research.

The internship and thesis projects currently available are collected in this topic guide and are classified according tothe imec research domains. You can find more detailed information on each research domain under the heading‘Research’ on www.imec.be.

Should you require more information, you can send an e-mail to [email protected].

How to apply?

Send an application e-mail with your motivation letter and detailed resume to the responsible scientist(s)mentioned at the bottom of the topic description of your preference.The scientist(s) will screen your application and let you know whether or not you are selected for a project at

imec.

It is not recommended to apply for more than three topics.

For more information, go to the Internship and Master Thesis page under the heading Academy on our website.

http://www.imec.be/http://www.imec.be/http://www.imec.be/mailto:[email protected]:[email protected]:[email protected]:[email protected]://www.imec.be/


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I. CMOS Scaling (sub-22 nm)

Electrical evaluation and reliability assessment of local interconnects

In future CMOS technologies the individual transistors will be connected through local interconnects in order toincrease the device density and to reduce the metal one complexity. These local interconnects however have tofulfill the same strict reliability specification as the other chip components and a thorough understanding of thepotential degradation mechanisms is needed.The main task of this thesis/internship is the electrical characterization of these local interconnects. This includesthe evaluation of various newly designed test structures, the comparison of different local interconnect processesand the investigation of potential reliability issues.

Type of project: Thesis or internship project (preferred duration is 6 months)

Degree: Master in Industrial Sciences or Master in Science or Master in Engineering

Responsible scientist:

For further information or for application, please contact Thomas Kauerauf ([email protected]) .

Time-Dependent Dielectric Breakdown (TDDB) reliability of advanced CMOS gatedielectrics

CMOS scaling is not only concerned with the reduction of the channel length and channel width, but also thescaling of other transistor parameters such as the gate dielectric thickness. Recently high-k gate dielectric wereintroduced and the long-term reliability of these ultra-thin layers is of major concern. The time-dependentdielectric breakdown (TDDB) is one of the critical mechanisms, where the generation of individual defects in thedielectric leads to an increase in gate leakage current and eventually to device failure. Although there has been alot of learning on TDDB in the recent years, there are still many open questions waiting to be answered.

The main task of this thesis/internship is to study the effect of electrical stress at the gate on key transistorparameters. Since the degradation does not occur abrupt but gradually, testing and analyzing the shift of theseparameters over time is required. A second aspect will be to evaluate whether these parameter shifts are actuallycritical to the device performance and if additional effects such as self-heating can be expected.

Type of project: Thesis or internship project (preferred duration is 6 months)


Responsible scientist: For further information or for application, please contact Thomas Kauerauf ([email protected]) .

mailto:[email protected]:[email protected]:[email protected]:[email protected]


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Conductive Atomic Force Microscopy (C-AFM) for memory devicescharacterization

Conductive bridging resistive memory CBRAM, based on resistance switching mechanisms, is emerging as apotential replacement for Flash and/or DRAM applications, due to its high scalability potential, for future 20 nmtechnology nodes and beyond (fig. A).Conductive atomic force microscopy C-AFM (fig. B) is a scanning probe microscopy technique, relying on a normalatomic force microscope equipped with a current sensor capable to measure ultra low currents. C-AFMrepresents an invaluable tool in two ways. First it allows examining very small features with nm-scale spatialresolution (nanoscopic electrical probing), and secondly the tip can be used as a nano sized electrode.This internship/thesis fits into the characterization framework for OXRRAM/CBRAM using C-AFM. You will betrained in the use of the tool and you will intensively use it focusing on device characterization methodologies.During the period of the internship the student will focus particularly on material characterization andenvironmental conditions .The data analysis and interpretation will cover an important part of the work; you willapply statistical principles in data collection and will be asked to rule out your results. You will work in aninternational R&D team; a good command of English language is required.The detailed content of the work will be defined in detail at the moment of starting this project.

Type of project: Thesis or internship project of 6 months

Degree: Master in Science or Master in Engineering majoring in physics, electrical engineering, material science,

chemistry

Responsible scientist:For further information or for application, please contact Umberto Celano ([email protected]).

Investigation and optimization of the electrical switching properties of scaledTa2O5-based resistive RAM memory cells

The Resistance RAM (RRAM) is a new class of memories emerging as serious candidate for future memoryreplacement. Resistance RAM cells typically consist of an insulator material sandwiched between two metalelectrodes, and exhibiting resistive-switching properties, that is to say the application of an electrical

current/voltage to the cell induces reversible changes of the cell resistance, which allows thus programmingdifferent memory states.For metal/oxide/metal RRAM devices, the switching to the low resistance state (LRS) is understood as theformation of oxygen-vacancy chain through the oxide while the return to the high resistance state (HRS) is due topartial recovery of these defects, the two operations being electrically induced.

mailto:[email protected]:[email protected]


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Ta2O5 materials have recently drawn a lot of attention due to excellent set of RRAM memory propertiesdemonstrated recently on scaled cells (see Fig.1). Not only controlled memory operation, low programmingpower, and good data retention were demonstrated, but also in particular longer write-programming enduranceresults were obtained on such material (Fig.1c) than on other switching oxides.

(a) (b) (c)

Fig1: examples of scaled Ta2O5-based RRAM cell (a), switching I-V traces (b), and excellent write endurance properties (c), as extracted from “M.-J. Lee etal., Nature Materials, vol.10, 2011, p165”

However, little is known yet with respect to the switching mechanisms and improvement potentials in Ta2O5-based RRAM. We recently undertook the integration development of scaled Ta2O5 RRAM memory cells stackedon memory-select transistors. The purpose of the internship will be to study the effect of processing and cell-stackmaterial combinations (including electrodes) on the electrical-switching properties. To this aim, the followingmethods will be used:

• Standard I-V measurements

• Constant voltage stress tests

• Above methods at different temperatures

• Pulse programming using sub-10ns wide electrical pulses

• Possible C-V measurements

• Possible modeling activityThe study will be carried out within a project team consisting of experts in different fields (processing, integration,physical characterization, modeling ...), so that the understanding and modeling of the electrical results can be

facilitated.The study will also be realized in close collaboration with industrial partners. The gained understanding of theswitching will allow defining an optimum stack configuration satisfying the industrial specification for memoryoperation.

Type of project: Internship project of minimum 5 months

Degree: Master in Science or Master in Engineering majoring in material science, physics, electronics

Responsible scientist:For further information or for application, please contact Ludovic Goux ([email protected]).


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Reliability measurement and modeling of advanced BEOL interconnect

Deep submicron interconnect scaling leads to severe issues with reliability of the wires in the BEOL (Back-end-of-line) process stage. Both electromigration and TDDB (Time-dependent dielectric breakdown) play a major role.

deliver mode: 7 we want to measure the characteristics of deeply scaled interconnect schemes to evaluate thedegradation mechanisms and to characterize them under different conditions.Moreover, based on these measurements we want to build a SPICE-level model which allows to model the effectsin a parametric way for use in circuit level simulations of data-path or memory structures.

Profile: strong interest in measurement setups and hardware, basics of electrical SPICE-level modeling, basics ofreliability degradation.

Type of project: Thesis of minimum 6 months (full-time, at Leuven)

Degree: Master in Engineering majoring in micro- or nano-electronics

Responsible scientist(s):

For further information or for application, please contact Kristof Croes ([email protected]) and FranckyCatthoor ([email protected]).

Evaluation of MgO as tunnel barrier in material stacks for MRAM applications

Magnetic random access memory (MRAM) is a non-volatile memory having the information stored in themagnetization direction. In order to realize next generation of high density non-volatile memory a lower switchingcurrent density and high thermal stability are needed. A promising solution to achieve these requirements inMRAM relies on MgO based magnetic tunnel junctions (MTJs) with perpendicular magnetic anisotropy. CrystallineMgO with (001) texture is needed to achieve perpendicular magnetic anisotropy in CoFeB/MgO/CoFeB based

MTJs. Parameters that are believed to have an important impact on performance are: texture, interface, B-contentof CoFeB, seed and capping layers or post-deposition anneals conditions. In this project basic understanding of thestacks is being built up. MgO will be deposited via MgO RF sputtering or Mg post-oxidation. A comparison withMgO ALD (atomic layer deposition) properties could be performed. The project will comprise beside stackdeposition, extensive physical analysis such as XRD, AFM, TEM, SIMS, XPS and magnetic properties such asevaluation of magnetoresistance ratio and magnetization saturation.

1. S. Ikeda, K. Miura, H.Yamamoto, K. Mizunuma, H.D. Gan, M. Endo, S. Kanai, J. Hayakawa, F. Matsukura, and H. Ohno, Nature Materials, 2010, 9,721.

2. K. Yakushiji, K. Noma, T. Saruya, H. Kubota, A. Fukushima, T. Nagahama, S. Yuasa and K. Ando, Applied Physics Express, 2010, 3, 053003.3. D.C. Worledge, G. Hu, D.W. Abraham, J.Z.Sun, P.L. Trouillard, J. Nowak, S. Brown, M.C. Gaidis, E.J. O'Sullivan and R.P. Robertazzi, Applied Physics.

Letters, 2011, 98, 022501.4. Y.S. Choi, K. Tsunekawa, Y. Nagamine, and D. Djayaprawira, Journal of Applied Physics, 2007, 101, 013907.

Type of project: Thesis and/or internship project of 3 up to 6 months

Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in material science,physics, electronics, chemistry

Responsible scientist:For further information or for application, please contact Mihaela Popovici ([email protected]).

mailto:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]


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Thermo-compression bonding of fine-pitch micro-bumps for 3D integration of ICs

Three-dimensional integration of ICs is a major driving technology for future size shrinkage and performanceimprovement of electronic products. One of the key elements in 3D integration is to build reliable fine pitch

interconnects between the vertically stacked ICs.At imec, we are working on thermo-compression bonding technology to make interconnection joints between themicro-bumps on the ICs. In this master thesis, you will work on both the theoretical and experimental aspects ofthermo-compression bonding to deepen the understanding of this process and to further develop it towards finerpitch requirements. You will focus on the investigation of actual physical conditions and resulting micro-scalechanges applied on the bonding interfaces between micro-bumps under different process conditions, and theirinfluence on the final bonding quality. In the implementation of this work, you will be involved in model building,planning of experiments, processing, characterization, and finally the analysis of results. You will have access tocutting-edge tools with the guidance from experienced researchers and engineers.

Type of project: Thesis project of 6 months

Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in physics, applied

mechanics, material science or relevant fields

Responsible scientist:For further information or for application, please contact Teng Wang ([email protected]).

Study of chipping mechanisms in the dicing of thin silicon wafers

Chipping of silicon wafers during their dicing is an important factor which limits the throughput and yield of thedicing process. Chipping also plays a significant role in determining the reliability of ICs. The recent development of3D integrated ICs and ultra-thin packages have strongly driven the need of thinning silicon wafers to a thicknessrange of below 100 µm, which has made theIn this thesis work, your focus will be on the understanding of chipping mechanisms on both front sides and backsides of thin silicon wafers. The target is to identify different chipping mechanisms under different dicing conditionsand on wafers with different passivation layers through carefully designed experiments and microscopic inspectionusing both optical and scanning electron microscopes. You will be involved in design and execution of experiments,characterization, and analysis of experimental results. You will have access to cutting-edge processing andmetrology tools, assisted by experienced researchers and engineers.

Type of project: Thesis project of 6 months

Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in physics, materialscience, mechanical engineering or relevant fields

Responsible scientists:For further information or for application, please contact Teng Wang ([email protected]) and Kenneth Rebibis

([email protected]).



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Evaluation of photoresist outgassing for Extreme Ultraviolet Lithography

Extreme Ultraviolet (EUV) light is currently of increased interest in semiconductor processing. EUV Lithography(EUVL) is the leading candidate for 15nm half-pitch device manufacturing and beyond. One of the concerns of thisprocess technology is related to outgassing of materials in the vacuum environment – e.g. from photoresists –,

which, enhanced by the EUV irradiation, can result in a reflectivity decrease of the optical elements and in otherdecrease of exposure tool performance.In this field the student would work at imec on an experimental outgassing set-up (Fig. 1) to evaluate the EUVrelated outgassing and contamination and is involved in outgassing analysis of various photoresist materials. Thiswill contribute significantly to the understanding how materials and process conditions can impact contamination inthe EUV scanners, and lead to procedures to qualify resist materials before they are used on the EUV scanners.

Fig.: Experimental EUV outgassing set-up at imec for investigation of outgassing of lithography materials.

Type of project: Preferably internship project of minimum 6 months

Degree: Master in Science or Master in Engineering majoring in physics, material science, chemistry

Responsible scientist:For further information or for application, please contact Ivan Pollentier ([email protected]).

Deposition, characterization and application of dielectric films

New dielectric films are being developed for many applications in integrated circuits. Dielectric films are, ingeneral, used to form an electrical insulator between active devices-transistors and/or electrically conducting metallines. Their main characteristics are:

•

good uniformity over the wafer• high resistivity

• controlled stress

• hardness and Young’s modulus



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The deposition process also has the following needs:

• reproducibility and compatibility with other process steps in the manufacturing of the integrated circuit

• the adhesion of the film to films below and above has to be assured

• a good reliability of the IC, which is strongly dependent on the quality of the dielectric filmsThe characterization of thin dielectric films consists of several phases. At imec, we start with the determination ofthickness, refractive index, density, chemical composition through Fourier Transform Infrared spectrometry,

stress, Young’s modulus, hardness, porosity, hydrophilicity and dielectric constant of the films. If thischaracterization looks promising, a second series of tests which simulate other (former and later) process steps,are performed; this also includes tests to determine the adhesion to other films, mainly by 4 point bending analysis.Also, a more detailed chemical analysis, e.g. through XPS and TOFSIMS, will be performed. If all tests are positive,finally, the material is used in an integration process, resulting in a real test chip and the final electricalcharacterizations (including reliability characterizations) are made.The student will be very strongly involved in the detailed characterization of the basic film properties. Hereby(s)he will use state of the art analysis equipment, such as ellipsometers, a Fourier Transform Infraredspectrometer, a high precision mass measurement system, and others. Furthermore (s)he will also be involved inthe next phase of the characterization cycle, as setting up the processes for the simulation of integration aspectsand the electrical characterization on test chips.Academic and industrial results will be reported in meetings where both imec staff and industrial affiliatesparticipate.

Type of project: Internship project of 6 months

Degree: Master in Science or Master in Engineering majoring in material science, chemistry

Responsible scientist:For further information or for application, please contact Patrick Verdonck ([email protected]).

Development, characterization and application of pore sealing treatments

New low-k dielectric films are being developed for many applications in integrated circuits. The new low-k filmsare quite porous and have large pores. During the integration of these low-k films into an integrated circuit, it is

necessary to seal these pores in order to obtain structures with a high reliability.The pore sealing process has to obey demanding requirements, such as:

• the final thickness of the pore sealing films should be as low as possible, of the order of a few nm

• the dielectric constant of the pore sealing film should be as low as possible, below 4

• during the deposition of the pore sealing film, the pores in the bulk of the low-k film have to remain open

• the pore sealing treatment should damage the low-k film as little as possibleAt imec, we have already started to explore different routes for these pore sealing treatments. The deposition ofboth dielectric and metal films is being studied. Also the combination of different treatments (plasma, application ofself assembled monolayers etc.) are being investigated. Pore sealing of different materials is being tested, as well onfilms with a dielectric constant of less than 2.0 and very large pores, with a pore diameter up to 4 nm, as on filmswith a dielectric constant of 2.4 with a pore diameter of less than 1 nm.Different characterization techniques are applied. Ellipsometric porosimetry is very important to detect the sealingof the treatments. Also determination of the final dielectric constant by C-V measurements is essential. Besides

these, the most interesting film stacks are also being characterized by other techniques such as: Fourier TransformInfrared spectrometry, XPS and TOFSIMS. If these tests yield positive results, the new treatment is used in anintegration process, resulting in a real test chip and the final electrical characterizations (including reliabilitycharacterizations) are made.



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The student will be very strongly involved in the detailed characterization of the film-stack properties. Hereby(s)he will use state of the art analysis equipment, such as ellipsometers, a Fourier Transform Infraredspectrometer, a high precision mass measurement system, C-V meters and others.Academic and industrial results will be reported in meetings where both imec staff and industrial affiliatesparticipate.

Type of project: Internship project of 6 months

Degree: Master in Science or Master in Engineering majoring in material science, chemistry

Responsible scientist:For further information or for application, please contact Patrick Verdonck ([email protected]).

Hot carrier reliability on advanced logic/DRAM devices

The continuous device scaling down allows the integration of a large number of transistors on a chip and increasesthe speed. However since the 65 nm node, the VDD is saturating at a level around 1V due to the non-scaling sub-threshold slopes of the MOSFET’s. And this increases electric fields with scaling, makes hot carrier reliability an

very important issue.In this study, hot carrier degradation in very thin EOT regime will be investigated by exploring defects in the gateoxide/ junction. Also, the impact of the process conditions including different high-k stacks and/or device structurewill be studied. For the applicant, a good knowledge of semiconductor physics is required. During the project, thestudent will have the opportunity to participate and interact with the researchers of the Logic/DRAM program.

Type of project: Thesis and/or internship project

Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in material science,physics, electronics

Responsible scientist:For further information or for application, please contact Moon Ju Cho ([email protected]).



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Investigation of advanced self-rectifying resistive switching memory cells (SRC-RRAM)

Resistive Random-Access-Memory (RRAM), based on resistance switching mechanisms, is emerging as a potentialnonvolatile memory candidate for below-20nm technology nodes, due to its better scalability, beyond the limits

currently predicted for NAND Flash. 10nm-small RRAM cells are shown to have low voltage operation, very fastswitching time, in the order of ns and below, small energy consumption per switching and good reliability. To takeon the benefits of these excellent attributes to circuit level and enable high density memory array implementation,additional self-rectifying functionality is required for the resistive switching stack and needs to be achieved within atwo-terminal, 10nm scalable structure.The main task of this internship/thesis is to screen new resistive switching memory concepts with the aim ofassessing their potential for self-rectifying memory cells and/or investigate RRAM cells that show self-rectifyingcharacteristics, with the aim of understanding the switching behavior, relate it to intrinsic performance and identifypaths for further improvement/optimization.You will be involved in electrical characterization, focusing on performance and/or reliability aspects. You will beusing state-of-the-art instrumentation and you will apply statistical principles in data collection using in-housedeveloped characterization methodologies, so as to ensure a short response time in characterization. You willprocess data and assist in their interpretation. Feedback for process improvement is a key point.You must have a good background in semiconductor physics and knowledge of CMOS technology. You must befluent in at least one programming/data analysis environment such as Matlab or similar and familiar with LabViewand basic instrumentation for electrical testing. You will work in an international R&D team; a good command ofEnglish language is required.The detailed content of the work will be defined at the moment of starting this project, in line with latest researchpriorities.

Type of project: Internship or thesis project of 6 months

Degree: Master in Science or Master in Engineering majoring in electronics, electrical engineering, physics

Responsible scientist:For further information or for application, please contact Bogdan Govoreanu ([email protected]).

Self-assembled monolayers as enabling technology for microelectronics

As the total transistors and interconnect sizes come down to few tens of nanometers a shift in paradigm for themanufacturing and integration of microelectronics components becomes apparent. Organic molecules - owing totheir size, mechanical flexibility and chemical tunability - fit well in this slot and, thus, are expected to play a keyrole in IC downscaling. In this respect, self-assembled monolayers (SAMs) seem the best candidates. SAMs are aprototypical form of nanotechnology: the SAM precursor molecules carry the “instructions” required to generatean ordered, nanostructured material without external intervention. SAMs demonstrate that molecular-scale design,synthesis, and organization can generate macroscopic materials properties and functions. Although the details ofthe thermodynamics, kinetics, and mechanisms of assembly will differ significantly, these monomolecular filmsestablish a model for developing general strategies to fabricate nanostructured materials from individual

nanometer-scale components. Because SAMs can assemble onto surfaces of any geometry or size, they provide ageneral and highly flexible method to tailor the interfaces between nanometer-scale structures and theirenvironment with molecular (i.e., subnanometer scale) precision. SAMs can control the wettability andelectrostatic nature of the interfaces of individual nanostructures and thus their ability to organize into largeassemblies adding chemical functionality, thermodynamic stability (e.g., improving the adhesion at thedielectric/metal interface).

mailto:[email protected])mailto:[email protected])


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In particular, metallization of SAMs, i.e. the formation of metallic or barrier overlayers or clusters on top ofmonomolecular organic films, is of great importance for many areas of fundamental and applied research. Albeitthis problem was actively addressed in the last years, reliable methods to the deposition of metal on top of theSAM are continuing to be a topic of intense research. This task is challenging since most of the studies show anundesirable metal penetration through the SAM. It is generally believed that this is caused by structural defects inthe monolayer. Cu is the interconnect material of choice in the metallization step for advanced semiconductordevice manufacturing. The current approaches to Cu metallization include chemical vapor deposition (CVD),physical vapor deposition (PVD), selective electroless deposition (ELD) and electroplating.The purpose of this work is to characterize and benchmark the thin SAM organic films deposited both in liquidphase and vapor phase on full 300mm wafer scale as a function of the ELD films quality. The effects of the SAMschemistry (functional groups, vapor vs. liquid phase deposition, deposition solvents etc...) and ELD experimentalconditions on the deposition mechanism and efficiency of the electroless Cu bath (e.g. in terms of Cu thicknessand roughness control, adhesion at the interfaces dielectric/SAMs/Cu..., which will be characterized by the student)will be investigated.

Type of project: Thesis and/or internship project of minimum 6 months

Degree: Master in Science or Master in Engineering majoring in chemistry, material science


For further information or for application, please contact Silvia Armini ([email protected]).

Advanced barrier CMP slurry development

In order to build even smaller devices, very narrow structures have to be filled with copper to achieve advancedinterconnects. The aspect ratio of these lines makes them hard to fill without defects and voids. One of theapproaches that helps the deposition of copper into narrow structures is to vary the underlying barrier-seed layer.The choice of this layer improves copper electroplating and can make ELD Cu deposition possible.In the subsequent processing steps, the copper as well as the underlying barrier-seed layer needs to be removed inthe field area, leaving conducting material only within the interconnect structures. This is achieved through a CuChemical Mechanical Polishing (CMP) step followed by a barrier CMP step (which removes the barrier-seed layer).When polishing these barrier layers using CMP, there are several process issues that can occur. First of all, thebarrier metal needs to be removed quickly and evenly, which can be hard due to native oxides on the surface.Second, it is necessary to keep corrosion issues under control during the CMP process.The goal of this project is to optimize barrier-seed layer removal rates on blanket wafers while limiting (galvanic)corrosion using model slurries which are optimized for barrier CMP. In order to achieve a good removal rate,different oxidizers and complexing agents are added to model slurries while surfactants/inhibitors are added toprotect the surface against corrosion and improve planarity. Static etch rates for these slurries need to bedetermined to estimate extent of static corrosion. Other CMP parameters (e.g. pressures, flow rates) can beadjusted to further improve the process. Basic electrochemical measurements can be done as well to determinethe effect on the corrosion currents in the Cu-barrier CMP system for different slurry additives.For the best performing slurries, it needs to be ascertained that the defectivity and planarity of the polished surfaceis good. Performance with respect to other device materials needs to be checked. Time permitting, these slurriesmay be tested on patterned wafers as well as on other advanced barrier materials.Applied techniques include CMP on our experimental polisher, sheet resistance measurements, defectivity analysis,electrochemical tests, etc.A basic knowledge of chemistry is necessary, some experience in electrochemistry is a plus.


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Type of project: Internship or thesis project of minimum 3 months

Degree: Master in Industrial Sciences or Master in Science majoring in chemistry, chemical technology, materialsscience, physics

Responsible scientist:For further information or for application, please contact Lieve Teugels ([email protected]).

Development of a ramped voltage BTI procedure for fast gate dielectric testing

As the vertical scaling of the conventional poly-Si/SiO2/Si field effect transistors (MOSFET) reached the nanometricscale, the high electric field dropping in the oxide resulted in an intolerable gate leakage current. At that point,industry opted for replacing the conventional SiO2/poly-Si structure by high-k/metal gate stacks that toleratephysically thicker oxide while keeping or even increasing the oxide capacitance. Once the leakage current issuewas circumvented, the so-called bias temperature instability (BTI) is becoming one of the most critical factors,complicating the qualification of the future technology nodes [ 1, 2,3]. Furthermore, the number of stochasticallybehaving gate oxide defects in each device decreases to a numerable level due to the lateral downscaling, whiletheir relative impact on the device characteristics increases. For all these reasons, BTI lifetime cannot be described

any longer by a unique number, and BTI lifetime distribution has to be taken into consideration. As a consequence,even in the ideal case of the average BTI lifetime meeting the ITRS [4] specifications, a fraction of nanoscaled deviceswill fail at low overdrives.The main task of this thesis/internship is to develop a fast methodology to assess NBTI lifetime distributions. Aramped voltage BTI procedure is proposed as fast alternative to the time consuming current methodology. Thisincludes the adaptation of the test software, the demonstration of the finished routine, the benchmark with theclassical BTI routine and eventually the electrical testing of advanced gate stacks.

[1] E. Cartier, A. Kerber, T. Ando, M. M. Frank, K. Choi, S. Krishnan, B. Linder, K. Zhao, F. Monsieur, J. Stathis and V. Narayanan “Fundamental aspects ofHfO2-based high-k metal gate stack reliability and implications on tinv -scaling,” in Proc.: IEDM 2011, pp. 441-444.[2] M. Cho, M. Aoulaiche, R. Degraeve, B. Kaczer, J. Franco, T. Kauerauf, Ph. J. Roussel, L. Å. Ragnarsson, J. Tseng, T.Y. Hoffmann and G. Groeseneken,“Positive and negative bias temperature instability on sub-nanometer EOT high-k MOSFETs,” in Proc.: IRPS 2010, pp. 1095-1098.[3] J. Franco, B. Kaczer, G. Eneman, J. Mitard, A. Stesmans, V. Afanas'ev, T. Kauerauf, Ph.J. Roussel, M. Toledano-Luque, M. Cho, R. Degraeve, T. Grasser,L.- Ǻ. Ragnarsson, L. Witters, J. Tseng, S. Takeoka, W.-E. Wang, T.Y. Hoffmann, G. Groeseneken, “6Å EOT Si 0.45Ge0.55 pMOSFET with optimized reliability

(V DD=1V): Meeting the NBTI lifetime target at ultra-thin EOT,” in Proc.: IEDM 2010, pp.70-73.[4] International Technology Roadmap for Semiconductors available at http://public.itrs.net.

Type of project: Internship or thesis project of 6 months preferably


Responsible scientist:For further information or for application, please contact Maria Toledano Luque ([email protected]).



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Compact modeling of advanced transistors

As CMOS technology is entering the 10nm and sub-10nm technology era, important innovations are introduced inthe device design and even in the device concepts. New constraints are also appearing such a layout dependenteffects. To enable circuit design based on these new transistors and behaviors, the compact models used for circuitsimulations must evolve accordingly.

Working on compact modeling allows to have a very broad view on the field of semiconductors, from fabricationconstraints towards device physics, and taking into account system level requirements.The goal of this project is to model modern devices (FinFETs) fabricated at imec. This work will imply reviewingthe standard methodology used in transistor compact modeling, setup the required experiments to extract keytransistor model parameters, perform the measurements, and use the results to build compact models based onSilicon data. Industry standard software for compact model extraction will be available, as well as access to alltechnical information required to perform compact model extraction. The student will be part of the compactmodeling team and interact with device developers and circuit designers.


Degree: Master in Engineering majoring in (micro)electronics

Responsible scientists: For further information or for application, please contact Morin Dehan ([email protected]) and Marie GarciaBardon ([email protected]) .

Modeling of temperature effects in advanced devices

As technology feature sizes are reduced, temperature becomes an important parameter in devices and in circuitdesign. Temperature impacts strongly the speed, the power and the reliability of circuits. Massive amounts of heatare generated by the higher and higher density of power with lower access to cooling. The low access to heatdissipation can even generate "self-heating" effects, for example in FinFETs. In parallel, the use of advancedmaterials stacks change the sensitivity of devices to temperature and can even reverse well-known trends used todesign circuits.These effects have to be understood and captured in device compact models to be transferred at circuit designlevel, where their impact will be evaluated and solutions could be found.The goal of this project is to understand and model how temperature affects device functionality in bulk and SOIFinFETs, as well as to understand the impact of scaling on temperature variations. The study will be based onmeasurements of imec devices. The modeling and understanding will be mainly based on use of industry standardcompact models such as BSIM to produce model cards for circuit simulation. The student will be part of thecompact modeling team but also interact with the device characterization engineers and circuit designers.


Degree: Master in Engineering majoring in (micro)electronics

Responsible scientists:

For further information or for application, please contact Morin Dehan ([email protected]) and Marie GarciaBardon ([email protected]) .

mailto:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]


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Characterization and modeling of oxide border traps in Ge/III-V MOSFETs

Recent developments on CMOS-driven III-V and Ge MOS (Metal-oxide-semiconductor) technologies provide newopportunities in advancing the performance envelope of logic devices as well as lowering the operating power. Thequest of high speed/low power post-Si CMOS with heterogeneous integration calls for in-depth studies on variousaspects including device modeling and characterization, performance benchmarking, reliability/passivation/contact

studies and ultimately, scaling beyond 10nm node. Recently, the impact of oxide traps (border traps) on deviceperformance has been demonstrated [1] on III-V and Ge MOSFETs.The proposed research activities for the internship include (but not limited to):

1. Electrical characterization of III-V/Ge planar MOS- and FIN- FETs for gate stack performance, and oxide and

interface evaluation (Admittance analysis, AC-transconductance, charge pumping... ), paired to device

benchmarking.

2. Modeling and simulation: relating the border traps and electrical results measured on devices with different

channel materials, gate stacks and layer structures.

[1] D. Lin, et al, p. 645 IEDM 2012

Type of project: Internship or thesis project

Degree: Master in Science or Master in Engineering majoring in electrical engineering, physics, materials science

Responsible scientists: For further information or for application, please contact Koen Martens ([email protected]) and Dennis Lin([email protected]).

Interface stability and reliability of high-mobility channel MOSFETs

After the end of conventional CMOS scaling era, unabated enhancement of the device performance has beenguaranteed by materials and architecture innovation. Three main technological breakthroughs have beenintroduced in recent CMOS nodes: strain engineering (90nm node), high-k/metal gate technology (45nm) and tri-

gate (finFET) architectures (22nm). A new innovation will be soon needed for continued equivalent scaling in futurenodes.One of the most promising options currently under consideration is the introduction of high-mobility channelmaterials, namely Ge-based channels for pMOS and III-V compounds for nMOS. However, significant technologicalchallenges remains to be solved. In particular, interface passivation of non-Si channel materials is a critical issuewhich severely impacts the device performance and reliability. Moreover, further challenges derive from the needof integrating such novel materials in the novel finFET architecture and in combination with previously introducedinnovations (strain-engineering, high-k/metal gate stacks).The main task of this thesis/internship is the electrical characterization of high-mobility channel device prototypes.This includes the use of several measurement approaches (I-V, C-V, pulsed I-V, Charge Pumping, Measure-Stress-Measure techniques) with both manual and semi-automatic computer-controlled measurement setups.

Type of project: Internship or thesis project of 6 months preferably


Responsible scientist: For further information or for application, please contact Jacopo Franco ([email protected]).



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Carbon nanotube contacts: electrical characterization of CNT – damascenecontacts

Carbon Nanotubes (CNT) have remarkable electrical, thermal and mechanical properties that make theminteresting candidates as a metal in future contact applications where conventional metals cannot meet therequired specs that come with the extreme scaling in nanotechnology. At imec, CNT interconnects are beingcreated and electrically evaluated inside 150nm diameter contact holes. All steps for the CNT integration, thesteps for patterning the Cu damascene top contact, and the mask set used are compatible with 130nm devicetechnologies on 200mm wafers.[1,2] Our new platform is designed for automatic electrical testing using Kelvinvias, parallel vias or other probing pads.This project is focusing on improving the CNT quality to reduce the contact resistance [1-3]. In parallel, splits inthe integration module on the top contact are included to obtain more insight in the CNT-to-metal contact. Theelectrical performance studies have the objective to obtain a detailed understanding of the CNT interconnect andfind ways to improve the CNT interconnect performance.The purpose of the project is: (1) Obtaining a better understanding of the behavior of the CNT interconnectunder stressed conditions (high frequency, breakdown, aging, reliability...), supported by theoretical modeling. (2) Developing a theoretical model that can be validated experimentally to distinguish the resistance from the CNTand bottom and/or top contact.The CNT growth and integration work is realized in a

cross-functional team bridging the two groups of Prof. Dr.S. De Gendt and Dr. Zs. Tökei (team InterConnectIntegration).

[1] van der Veen et al., IEEE IITC conf. proc. (2012) 14.2[2] van der Veen et al., “Electrical Characterization of CNT contacts with Cudamascene Top Contact” Microelectron Eng. (2013)http://dx.doi.org/10.1016/j.mee.2012.09.004 [3] Chiodarelli et al. Nanotechnology 22 (2011) 085302.


Degree: Master in Science or Master in Engineering majoring in physics, electronics, material science,nanotechnology

Responsible scientists: For further information or for application, please contact Yohan Barbarin ([email protected]) and Marleenvan der Veen ([email protected]).

Cross-section of the electrical structure showing four 150nm contact holesfilled with CNT and metallized with Cu single damascene top contact

http://dx.doi.org/10.1016/j.mee.2012.09.004http://dx.doi.org/10.1016/j.mee.2012.09.004mailto:[email protected]:[email protected]://dx.doi.org/10.1016/j.mee.2012.09.004


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Carbon nanotube growth and its catalyst nanoparticle deposition for future contactapplications

Due to their remarkable electrical, thermal and mechanical properties, carbonnanotubes (CNT) have been considered for various applications in differentfields of research. One particular application, situated in the world ofintegrated circuits, is a CNT based interconnect and CNT contacts.Various reports exist in literature where the growth of CNT with a highquality is demonstrated. However, most of these results are obtained underprocess conditions that are not fully CMOS compatible and hence cannot beused in nanoelectronic applications in CMOS.The aim of this project is to investigate and develop a CMOS compatiblegrowth process that results in high quality CNTs.The CNTs need to be grown in very small via features (sub 22 nm) orstructures with a high aspect ratio (diameter with respect to depth of thehole), as is projected for future generations of interconnects and other contactapplications (Figure 2). The most important boundary conditions for this CNTgrowth are:

1) Catalyst placement on the bottom of the deep hole.

2)

Achieve CNT growth directly on conductive substrates.

The first part of the project focuses on the fundamentalaspect of catalyst deposition and choosing thenanoparticle deposition process for CNT growth inhigh aspect ratio features. After a good understandinghas been obtained on the catalyst deposition process, afixed catalyst will be chosen to study the CNT growthwith the objective to achieve sufficient CNT growth forelectrical characterization.The work will start from earlier findings within theCNT team in the group of Prof. Dr. S. De Gendt.

Figure 1: Scanning Electron Image of CNT growth in small vias


Degree: Master in Science majoring in chemistry, material science, nanotechnology

Responsible scientists: For further information or for application, please contact Johannes Vanpaemel ([email protected]) and Marleen van der Veen ([email protected]).

Figure 1: Schematic view of CNTs in small viafeatures (


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Bottom-up fill of deep holes with nanowires for future contact schemes

Nanowires are expected to play a key role in the transistor and interconnect down scaling as the paradigm forintegration of microelectronics components is entering the sub-22nm scale. Conventional metals will no longersimply meet the requirements needed for the performance and conventional depositions methods are no longer afilling solution at sub-14nm dimensions.

The aim of this project is to realize CMOS compatible nanowire depositionin extreme small dimensions at the nanoscale. The focus is to deposit themetals like Cu and W, or alloys, using a void-free and preferably frombottom-up growth process. Techniques that can be considered for themetallic nanowire growth are chemical vapor deposition, atomic layerdeposition, or selective electroless or electrochemical deposition. Thebottom-up growth will be studied on metallic contacts or barrier layers.Several test vehicles for the bottom-up growth will be available for the growthtests.The characterization of the vertical nanowires grown on a conductivesubstrate will focus on the relation between the structural properties and theelectrical properties. The ultimate goal is to identify metallic nanowires thatcan show ballistic transport on a sub-10nm scale. For this, it’s needed to study

and understand how the electrical conduction through the nanowires is influenced by the dimensions (diameterand length), and whether optimization of the growth can improve the nanowires performance. Successful grownnanowires can be tested further in full integration schemes using the advanced imec pilot line on 300mm full waferlevel. The work will start from earlier findings within the cross-functional metallization teams bridging the group of H.Struyf and the InterConnect Integration program of Dr. Zs. Tökei.


Degree: Master in Science or Master in Engineering majoring in chemistry, material science, nanotechnology


For further information or for application, please contact Marleen van der Veen ([email protected]).

Energy spectrum of a cylindrical superlattice nanowire

In this thesis the energy spectrum for a cylindrical nanowire consisting either out of heterostructure superlatticeor periodic gate configurations or periodic width fluctuations will be calculated. In first instance the student willconsider a simple periodic potential profile along the axis of the nanowire to understand the formation of theminiband spectrum as a function of periodicity and potential energy heights. Once this problem is solved we willconsider periodic all-around gates and study the energy spectrum as a function of the applied gate voltages, wireradius, spacing between the gates. Finally, the case of a periodic superlattice heterostructure and an infinite arrayof periodically spaced width fluctuations will also be considered.The research is situated in the broader quest for devices that can be fabricated in future sub-10 nm nodes.Amongst other challenges, one problem to overcome is to suppress unwanted currents that remain present whentransistors are in sub-threshold mode (‘off’). One approach to this problem is the use of minibands to filter out theelectrons that contribute to this unwanted current. Hence a good understanding of the influence of wiregeometry, superlattice parameters, etc. on the formation of minibands is necessary. Since the usual semi-classicalapproximations for semiconductors are no longer useful on this length-scale, calculations will start from solving theSchrödinger equation itself, a paradigm called wavefunction engineering that is becoming increasingly moreimportant as devices continue shrinking.


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The student will perform the aforementioned calculations by making acceptable approximations which will renderthe problem tractable. If necessary the student can also rely on available software to numerically solve theproblem. The student will make an analysis of the energy spectrum and draw preliminary conclusions with respectto the transport properties of the charge carriers in the nanowire.The candidate should have a strong background/interest in solid-state physics, quantum mechanics andcomputational physics.

Type of project: Thesis project

Degree: Master in Science or Master in Engineering majoring in physics, nanoscience, nanotechnology

Responsible scientist: For further information or for application, please contact Bart Soree ([email protected]).

Modeling of tunable band gap bilayer structures and devices

It is possible to tune the band gap in bilayer graphene and transition-metal dichalcogenides by external electricfields applied perpendicular to the layers. The band gap of bilayer graphene increases while the band gap of MoS2,

MoSe2, MoTe2, and WS2 bilayer structures continuously decreases with increasing applied electric field. This fieldeffect suggests potential directions for the fabrication of novel electronic and photonic devices.The focus of this master thesis will be on the modeling of the bilayer graphene tunneling field effect transistoreither in the P-N or P-I-N configuration. The possibility of tuning the band gap (electric field) by sweeping the gatevoltage offers a new path towards switching transistor devices on or off. Preliminary simulations have alreadyshown that sub-60 subthreshold slope current-voltage characteristics with reasonable Ion/Ioff ratios can beachieved.The student will make use of an existing simulation program based on the Non-Equilibrium Green’s Function(NEGF) formalism. The purpose is to model, understand and investigate the device characteristics as a function ofgate voltage, insulator thickness and multiple gate configurations.The candidate should have a strong background/interest in solid-state physics, quantum mechanics andcomputational physics.

Type of project: Thesis project

Degree: Master in Science or Master in Engineering majoring in physics, nanoscience, nanotechnology

Responsible scientist: For further information or for application, please contact Bart Soree ([email protected]).

Design of an reliability characterization package for future generation high-

performance CMOS transistors

Continuously shrinking the device size and device dielectric thickness results in changes of physical and electrical

properties which imposes limits on their usefulness, in particular a broad range of as-fabricated and stress-generated defects strongly affect the device performance. It is important to characterize these defects on the basisof extent of performance degradation caused by them in the CMOS devices. In particular, scaling the equivalentoxide thickness (EOT) has tremendous impact on failure mechanisms like bias-temperature instability (BTI), time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI), stress-induced leakage current (SILC) andrandom telegraph noise (RTN). Therefore, based on these degradation studies it is desired to introduce variants inthe deposition strategies to reduce the defect density or to mitigate their harmful effects.


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Since measuring strategies are tailored to each different failure mechanism, it is time-consuming to gather deviceparameters for each of these failure mechanisms. The focus of this internship/thesis would be the development of asoftware tool which combines a systematical and uniform approach for basic device parameter extraction incombination with existing device reliability characterization packages. The gathered information should then beextracted and processed to be stored in a central database.The candidate will be given the opportunity to co-work with state-of-the art semiconductor reliability researchersand scientists where he provides a generic software framework for future characterization of high performanceCMOS transistors. The candidate is required to have competent programming skills in general purposeprogramming languages, preferably in Perl, C++. Knowledge of semiconductor components is recommended.

Type of project: Thesis project, possibly in combination with internship of 6 months

Degree: Master in Industrial Engineering majoring in computer sciences, electronics

Responsible scientists: For further information or for application, please contact Erik Bury ([email protected]), Pieter Weckx([email protected]) and Ben Kaczer ([email protected]).

Design and simulation of on-chip circuits for parallel characterization of ultra-scaled transistors and SRAM cells for BTI reliability

It is well established that with the size of CMOS devices decreasing to atomic dimensions, the number of dopantatoms in each device reduces to numerable levels, resulting in increased time-zero (i.e., as-fabricated) variability. Atthe same time also the number of defects is decreasing to literally single-digit numbers, resulting in furthervariability increase with time (i.e., increased time-dependent variability and thus, further reduced reliability). Thistrend has recently lead to a shift in our perception of reliability: the “top-down” approach (deducing themicroscopic mechanisms behind the average degradation in large devices) is being replaced in deeply-scaled devicesby the “bottom-up” approach, in which the time-dependent variability is understood in terms of individual defects.The small ensembles of stochastically behaving individual defects are then responsible for the wide time-dependentdistributions of CMOS device parameters. Understanding these distributions requires electrical measurements ona large number of devices, necessitating in turn parallel evaluation schemes. Moreover, the impact of these defect

on circuit performance has barely been studied, except for simulations.Parallel evaluation of device reliability and circuits to monitor the effect of these degradation mechanisms is ofcrucial importance to gather enough statistical information. For this on-chip stressing and monitoring circuits,capable of capturing the degradation effects on ultra-scaled transistors, (reduced drain current, threshold voltageshift, ..) are required.In this thesis project such on-chip circuits will be created where the candidate is given the chance to undertakeeach step in the development process, from designing, simulating and (optionally) lay-outing of the circuit. Thecandidate will be required to have a solid knowledge of semiconductor components with experience in both digitaland analog circuit design. Recommended skills include SPICE circuit simulation and Cadence (optional).

Type of project: Thesis or internship project of 5 up to 6 months

Degree: Master in Electronical Engineering or Nanoscience

Responsible scientists: For further information or for application, please contact Erik Bury ([email protected]), Pieter Weckx([email protected]) and Ben Kaczer ([email protected]).

mailto:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]


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Graphene: device fabrication for optoelectronics

Graphene, an atomically-thin sheet of carbon atoms arranged in a sp2 honeycomb lattice, has been successfullyisolated for the first time only in 2004 [Novoselov et al, Science 306 (2004) 666.]. The peculiar electronicproperties of graphene arise mainly from the configuration of its energy band structure, which, combined with theintrinsically low occurrence of defects and the stiffness of its lattice, allows for the featuring of intriguing 2-D

physical phenomena. With respect to optoelectronic device performances, the high transparency in the visible-lightrange and the low resistivity of graphene sheets are the most attractive features, which makes graphene an idealcandidate to explore further its potential as a transparent electrode.The goal of this project is to study the layer interactions between substrate, graphene and optical active materials(e.g. quantum dot interactions), to characterize device performances and by molecular fine-tuning increase theoptoelectronic device performance.

(a) (b) (c)

Figure: (a) Schematic of the QD-treated graphene transistor in the typical measurement configuration employed in this work. (b) Transfer

characteristics I ds vs. V g of a SLG FET in pristine conditions, after QD deposition, and during QD excitation (532 nm laser). The inset shows an

optical microscope image of the 2-probe graphene device (scale bar: 2 μm). (c) Energy level diagram of the CdSe/ZnS QDs in contact with

SLG.[Pictures taken from: Klekachev et al, Physica E: Low-dimensional Systems and Nanostructures (2011) 43(5) 1046-1049]

During the internship/master thesis you will learn how to manipulate and functionalize graphene, to characterizethe doping level and the bandgap formation. Therefore, you will be involved in the design, fabrication, andcharacterization of graphene optoelectronic devices. The challenges involved are:

• the study of the interfacial reactions between the substrate, graphene and doping layer

•

post-processing of as-grown graphene (e.g., transfer, modification, device design)

• device fabrication by lithography

• electrical and optical device characterizationThe work will start from earlier findings within the graphene team and is conducted in the group of Prof. Dr. S. DeGendt.

Type of project: Thesis or internship project

Degree: Master in Science or Master in Engineering majoring in material science, nanotechnology, chemistry,physics

Responsible scientist: For further information or for application, please contact Inge Asselberghs ([email protected]).



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Graphene: device fabrication and characterization

Graphene, an atomically-thin sheet of carbon atoms arranged in a sp2 honeycomb lattice, has been successfullyisolated for the first time only in 2004 [Novoselov et al, Science 306 (2004) 666.]. The peculiar electronicproperties of graphene arise mainly from the configuration of its energy band structure, which, combined with theintrinsically low occurrence of defects and the stiffness of its lattice, allows for the featuring of intriguing 2-Dphysical phenomena. Graphene has been proposed as a candidate for CMOS and post-CMOS electronics.However, in order to make electronic applications of graphene realistic, one has to necessarily tune its electronicproperties, so that, for example, a bandgap is introduced. The realization of a proper bandgap is critical for thedevice performance. Most recently, the research team has demonstrated the tuning of single-layer graphene by p-and n- doping due to engineering the interactions with the SiO2 support [Nourbakhsh et al, PSS 6 (2012) 53.].

Figure: (a) Transfer characteristics and (b) transconductance of SLG-FETs fabricated on pristine and silanized Si/SiO2 substrates. The latter sample is thentreated in basic (red) and acidic (blue) solutions to turn the behavior from n- to p-type.[Figure taken from: Nourbakhsh et al, PSS 6 (2012) 53.] (c) image

of a graphene device.

The candidate will learn how to manipulate and functionalize graphene, to characterize the doping level and thebandgap formation. Therefore, he/she will be involved in the design, fabrication, and characterization of graphenedevices. Part of the work will entail the manipulation and functionalization of graphene produced by bothmechanical exfoliation and synthetically grown graphene, for benchmarking purposes. The challenges involved are:

• the study of the interfacial reactions between the substrate, graphene and doping layer;

• post-processing of as-grown graphene (e.g., transfer, modification, device design);

• device fabrication by lithography;

• electrical device characterization.The work will start from earlier findings within the graphene team and is conducted in the group of Prof. Dr. S. DeGendt.

Type of project: Thesis or internship project

Degree: Master in Science or Master in Engineering majoring in material science, nanotechnology, chemistry,physics

Responsible scientist: For further information or for application, please contact Inge Asselberghs ([email protected]).



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Plasma etching and characterization of novel materials for advanced patterning

Continuation of CMOS scaling, following Moore’s law, is a key challenge for the IC industry. Nowadays, the 22 nmnode is on production (Intel), 14 and 10, 7 nm nodes are being explored at R&D level. From a patterningperspective, i.e. the ability to print and etch such structures on the wafer, 193i and EUV lithography coupled toself-aligned double or quadruple patterning will enable the patterning down to 15-20 nm line/space features.

Besides this, direct-self-assembly (DSA) polymers offer the possibility to print sub-15 nm line/space structures.For building advanced CMOS devices, reaching small dimensions at lithography stage is a must, but also patterntransfer into the target substrate must be done in a well controlled and reproducible manner. The currentmaterials used for patterning transfer are reaching their limits. Thus, novel materials in the field need to beexplored. These materials should allow to pattern smooth structures since the ITRS roadmap suggest that a linewith a critical dimension of 10 nm should have a line width roughness (LWR) of less than 10 Angstroms. Thepatterning of smooth sub-15 nm features within specifications (LWR, CD, etc.) will be a milestone for the IC R&Dand industry.The general objective of this Master work is to evaluate potential new materials that can be used in a CMOSintegration scheme. 1) Evaluate etch rates using plasma processes, 2) measure thickness, stress and opticalproperties by means of Spectroscopic ellipsometry, 3) evaluate mechanical properties of the materials when theyare exposed to different thermal cycles, 4) evaluate the performance of the selected materials in a real patterneddevice (Profile and LWR).

Type of project: Internship project of 6 up to 12 months

Degree: Master in Engineering majoring in chemistry, electronics, physics (materials, plasma)

Responsible scientists: For further information or for application, please contact Efraín Altamirano-Sánchez([email protected]) and J .-F. de Marneffe ([email protected]).

Low damage plasma processing: new materials for pore stuffing of 2.0 porous

SiOCH materials

In order to cope with device scaling, inter-line crosstalk and interconnect delays, chip manufacturers areintroducing since a few years low dielectric constant materials (low-k’s) as insulating material separating conductingCu lines. Currently, targeted k values for 2020 are of the order to 2.0 and below, to be compared with 4.2 forbulk SiO2 (reference dielectric for the semiconductor industry). In order to achieve such a low k value, Si-basedCVD materials are favored, where methyl groups are introduced (less polarizables) together with substractiveporosity. Those materials are referred as p-SiOCH, hybrid dielectrics, or organo-silicon glass (OSG). Currentstate-of-the-art synthesis methods allow to reach k values ~ 2.0, with porosity ~ 45% and average pore size ~2.4nm. Recent studies indicate that those materials are damaged by plasma processing, leading to methyl groupsuppression and loss of hydrophobicity. The source of damage is twofold; first, active radicals do penetrate theinterconnected porous structure and react with pore sidewalls, leading, through various reaction pathways, to thereplacement of hydrophobic Si-CH3 terminations by hydrophilic Si-OH; second, vacuum-ultra-violet (VUV)

photons emitted by the plasma, due to their high-energy (> 6eV) do break the Si-CH3 bonds as well, causingchemical and structural re-organization of the material, with appearance of high-polarity bonds and densification.Both together, plasma radicals and VUV act synergetically, leading to even higher damage. An option to overcomethese issues is the so-called pore stuffing approach, w

2013_2014 stage-thesisgids_07052013

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