IEEE Catalog Number: ISBN:

CFP13442-POD 978-1-4673-6418-8

2013 IEEE 10th International Conference on ASIC (ASICON 2013)

Shenzhen, China 28-31 October 2013

Pages 1-483

1/2

X

Keynote Speech Index

K-1 High performance SiGe Bi-CMOS Technology and its application N/A

Dr. David Harame

IBM fellow / IEEE fellow and IBM CTO for microelectronics. USA

K-2 Design Margin, Scaling, and the Future of Moore’s Law N/A

Prof. Andrew Kahng

UC San Diego CSE and ECE Departments, Fellow of ACM and IEEE, Chair

of ITRS Roadmap on design technologies

K-3 The Era of Exponentials Accelerating Innovation in Electronics That

Impact Everything, Everyone, Everywhere N/A

Dr. Rich Goldman

Vice President, Corporate Marketing & Strategic Market Development,

Synopsys, USA

K-4 Low Power RF Circuits for Broadband Signals N/A

Prof. Ramesh Harjani

University of Minnesota (Twin Cities).USA, TPC Chair for IEEE CICC

K-5 Power Management Solutions Enabled by Mixed-Signal Intelligence N/A

Dr. Bin Zhao

Fairchild Semiconductor, USA, IEEE Fellow, IEEE Distinguished Lecturer,

and Vice President of IEEE EDS

XI

Tutorial Session Index

T-1-1 Introduction to RF CMOS circuit design N/A

Prof. Noboru Ishihara

Tokyo Institute of Technology, Japan

T-1-2 Electrostatic Discharge (ESD) Protection of RF Integrated Circuits N/A

Prof. Juin J. Liou

Pegasus Distinguished Professor, University of Central Florida, Orlando, Florida, USA

Chang Jiang Scholar Endowed Professor, Ministry of Education, China

T-1-3 RF and analog integrated circuits and systems for wireless and portable applications N/A

Prof. Howard Luong

Hongkong University of Science and Technology, Hong Kong

T-2-1 Digital Microfluidic Biochips: Towards Hardware/Software Co-Design and

Cyberphysical System Integration N/A

Prof. Tsung-Yi Ho

National Cheng Kung University, Taiwan

T-2-2 Layout decomposition methods for double patterning and triple patterning

lithography N/A

Prof.Andrew Kahng

UCSD, USA

Dr. HailongYao

Tsinghua University, China

XII

Technical Session Index

SESSION A1

Micro Processor

A1-1 Distributed Task Migration for Thermal Hot Spot Reduction in Many-core Microprocessors (invited paper) 1

Zao Liu, Xin Huang, Sheldon Tan (UC Riverside), Hai Wang, He Tang (UESTC)

A1-2 Low Power Instruction Cache Design Based on Branch Execution Tracks 5

Quanquan Li, Qi Wang, Tiejun Zhang, Donghui Wang, Chaohuan Hou (Institute of Acoustics, Chinese Academy of Sciences)

A1-3 A Low-Power and High-efficiency Cache Design for Embedded Bus-based Symmetric Multiprocessors 9

Xiantuo Rao, Teng Wang, Xin’an Wang, Yinhui Wang (Shenzhen Graduate School, Peking University)

A1-4 Delay Hidden Techniques based on Configuration Contexts Reuse and Differential Reconfiguration in Coarse-grained Reconfigurable Processor 13

Haopeng Liu, Weiguang Sheng, Weifeng He, Zhigang Mao (School of Microelectronics, Shanghai Jiao Tong University)

A1-5 A High Throughput FPGA Embedded DSP Architecture Design 17

Hanyang Xu, Jinmei Lai (Department of Microelectronics, Fudan University)

A1-6 Energy Evaluation for Two-level On-chip Cache with Non-Volatile Memory on Mobile Processors 21

Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa (Waseda univarsity), Tadahiko Sugibayashi (NEC Corporation)

SESSION A2

Circuits and Systems for Wireless Communications (I)

A2-1 Integrated Silicon RF Front-End Solutions for Mobile Communications (invited paper) 25

Alvin Joseph, Randy Wolf (IBM)

XIII

A2-2 Low-Power High-Speed Communication with Short-Millimeter-Wave CMOS Transceivers (invited paper) 29

Minoru Fujishima (Hiroshima University)

A2-3 Design of Low power UWB CMOS LNA using RC Feedback and Body-bias Technology 33

Meng-Ting Hsu, Yu-Chang Hsieh, An-Cheng Ou (Department and Institute of Electronic Engineering, National Yunlin University of Science and Technology)

A2-4 Implementation of a Configurable MIMO Detector with Complex K-best Algorithm 37

Jieqiong Cheng, Junsong Zheng, Xiaofang Zhou (State Key Lab of ASIC & System), Linshan Zhang (YunNan Electric Power Test & Research Institute Group Co., Ltd)

A2-5 Highly Flexible WBAN Transmit-Receive System Based on USRP 41

TianChan Guan, Jun Han, Xiaoyang Zeng (State Key Laboratory of ASIC & System, Fudan University, Shanghai, China)

A2-6 A New Channel emulator for Low Voltage Broadband Power Line Communication 45

Yan Zhao, Xiaofang Zhou (ASIC & Systems, Fudan), Chao Lu (Aseit Co., Ltd.)

SESSION A3

Network on Chip

A3-1 A Power-Efficient Network-on-Chip for Multi-core Stream Processors 49

Guoyue Jiang (Institute of Microelectronics, Tsinghua University), Fang Wang, Zhaolin Li (Research Institute of Information Technology, Tsinghua University), Shaojun Wei (Institute of Microelectronics, Tsinghua University)

A3-2 A Thermal-Aware Mapping Algorithm for 3D Mesh Network-on-Chip Architecture 53

Gui Feng, Fen Ge, Shuang Yu, Ning Wu (College of Electronic and Information Engineering)

A3-3 A Two-phase Floorplanning approach for Application-specific Network-on-Chip 57

Shuang Yu, Fen Ge, Gui Feng, Ning Wu (College of Electronic and Information Engineering)

A3-4 MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support 61

Dexue Zhang, Xiaoyang Zeng, Zongyan Wang (Fudan university), Weike Wang (Shandong University of Science and Technology), Xinhua Chen (Qingdao ShanHai

XIV

Microelectronics Co., Ltd.)

A3-5 A 2D Mesh NoC with Self-Configurable and Shared-FIFOs Routers 65

Wei Zhou, Jianming Yu, Jie Lin, Zhiyi Yu, Xiaoyang Zeng (State Key Laboratory of ASIC & System, Fudan University)

A3-6 A hybrid router combining circuit switching and packet switching with virtual channels for on-chip networks 69

Jie Lin, Wei Zhou, Zhiyi Yu, Xiaoyang Zeng (Fudan University)

A3-7 Low Overhead Task Migration Mechanism in NoC-based MPSoC 73

FangFa Fu, Liang Wang, Lu Yu, Jinxiang Wang (Harbin Institute of Technology, Microelectronics Center)

A3-8 Design of an Optimized Low-latency Interrupt Controller for IMS-DPU 77

Zijia Guo, Teng Wang, Xin’an Wang (Peking University Shenzhen Graduate School), Ziyi Hu (Institute of Microelectronics of Chinese Academy of Sciences)

SESSION A4

Special Session (I) Ultra-Low voltage circuit design

A4-1 Soft Error Immunity of Subthreshold SRAM (invited paper) 81 Masanori Hashimoto (Osaka University)

A4-2 Variation-aware Subthreshold Logic Circuit Design (invited paper) 85

Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya (University of Tokyo), Masahiro Nomura, Hirofumi Shinohara (Semiconductor Technology Academic Research Center (STARC)), Takayasu Sakurai (University of Tokyo)

A4-3 Design of an Ultra Low-Power CMOS Amplifier for Low-Voltage Power-Aware Analog LSIs (invited paper) N/A

Tetsuya Hirose (Kobe University)

A4-4 Statistical simulation methods for circuit performance analysis (invited paper) 89 Takashi Sato (Kyoto University)

SESSION A5

Multimedia Circuit

XV

A5-1 A High Performance VLSI Architecture for Integer Motion Estimation in HEVC (invited paper) 93

Xu Yuan, Liu Jinsong, Gong Liwei, Zhang Zhi (Shenzhen University), Robert K.F. Teng (California State University, Long Beach)

A5-2 ASIC design for UHDTV video coding (invited paper) N/A

Dajiang Zhou, Jinjia Zhou, Gang He, Satoshi Goto (Waseda University)

A5-3 An Optimized Hardware Architecture for Intra Prediction in H.264 Decoder 97

Qi Wang, Quanquan Li, Shi Chen, Tiejun Zhang, Chaohuan Hou (Institute of Acoustics, Chinese Academy of Sciences)

A5-4 A FAST 8×8 IDCT ALGORITHM FOR HEVC 101

Tianlong Ma, Cong Liu, Yibo Fan, Xiaoyang Zeng (FUDAN UNIVERSITY)

A5-5 A Highly pipelined VLSI Architecture for All Modes and Block Sizes Intra Prediction in HEVC Encoder 105

Cong Liu, Weiwei Shen, Tianlong Ma, Yibo Fan, Xiaoyang Zeng (State Key Lab of ASIC and System, Fudan University)

A5-6 Transform-Based Fast Mode and Depth Decision Algorithm for HEVC Intra Prediction 109

Gang He, Dajiang Zhou, Satoshi Goto (Waseda University)

SESSION A6

Application-Specific SoCs

A6-1 Efficient Implementation of 3780-point FFT on a 16-Core Processor 113

Haofan Yang (Fudan University), Kedong Chen (Shanghai University of Engineering Science), Shengqiong Xie, Minge Jing, Zhiyi Yu, Xianyang Zeng (Fudan University)

A6-2 Design of a High Throughput Configurable Variable-Length FFT Processor Based on Switch Network Architecture 117

Renfeng Dou, Yifan Bo, Jun Han, Xiaoyang Zeng (State Key Laboratory of ASIC and System, Fudan university)

A6-3 A High-Resolution TDC Implemented in a 90nm Process FPGA 121

Jinmei Lai, Yanquan Luo, Qi Shao (State Key Laboratory of ASIC and System, Fudan University), Lichun Bao, Xueling Liu (Beijing Aerospace Control Center)

XVI

A6-4 A Temperature Sensing Front-end Using CMOS Substrate PNP Transistors 124

Dexin Kong, Ting Yu, Fengqi Yu (Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences)

A6-5 Scan-based Attack against Trivium Stream Cipher Independent of Scan Structure 128

Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa (Dept. of Computer Science and Engineering, Waseda University)

SESSION A7

Special Session (II) Advances in Parasitic Extraction and Circuit Simulation

A7-1 Fast transistor-level circuit simulation and variational analysis via the ultra-compact virtual source model (invited paper) 132

Yang Zhang, Quan Chen, Ngai Wong (Department of Electrical and Electronic Engineering, The University of Hong Kong)

A7-2 pmm: A Matlab Toolbox for Passive Macromodeling in RF/mm-wave Circuit Design (invited paper) 136

Zuochang Ye (Tsinghua University)

A7-3 Sparse Basis Pursuit on Automatic Nonlinear Circuit Modeling (invited paper) 140 Yu-Chung Hsiao, Luca Daniel (MIT)

A7-4 RWCap V2: Advanced Floating Random Walk Solver for the Capacitance Extraction of VLSI Interconnects (invited paper) 144

Wenjian Yu (Tsinghua University)

SESSION A8

Circuits and Systems for Wireless Communications (III)

A8-1 Full Software Radio Transceivers (invited paper) 148

Yann Deval, Francois Rivet (University of Bordeaux - Bordeaux Institute of Technology), Yoan Veyrac, Nicolas Regimbal (Atlantic Innovation), Patrick Garrec, Richard Montigny (Thales Aerospace), Didier Belot, Thierry Taris

A8-2 Analysis inductively coupling wireless connection in 3D package (invited paper) 152

Baocun Wang, Guoyi Yu, Xiaofei Chen, Li Zhang, Xavier Zou (Huazhong University of Science and Technology)

XVII

A8-3 Low-complexity Synchronizer Used in DC-OFDM UWB System 157

Bing Jing, Hao Chen, Fan Ye, Ning Li, Junyan Ren (Fudan university)

A8-4 A Low-Cost Fast Fourier Transform Processor for DC-OFDM System N/A

Zhenqi Liu, Fan Ye, Ning Li, Junyan Ren (State Key laboratory of ASIC & system, Fudan University)

A8-5 An Efficient Low-cost Fixed-point Digital Down Converter with Modified Filter Bank 161

Hanyu Wang, Jinxiang Wang, Yu Lu, Fangfa Fu (Microelectronics Center, Harbin Institute of Technology)

SESSION B1

Amplifier

B1-1 A 20 Gb/s Limiting Amplifier in 65nm CMOS Technology 165 Rui He, Jianfei Xu, Na Yan, Hao Min (Fudan University)

B1-3 A 12-bit 200-MS/s Sample-and-Hold Amplifier with a hybrid Miller-feedforward compensation technique 169

Yongzhen Chen, Chixiao Chen, Qiang Zhang, Fan Ye, Junyan Ren (Fudan University)

B1-4 A CMOS Synchronous Time Amplifier 173

Siliang Hua, Donghui Wang, Yan Liu (Institute of Acoustics, Chinese Academy of Sciences)

B1-5 Design of A Time-Interleaved Band-Pass Modulator for Class-S Power Amplifier 177

Yang Zhao (State Key Laboratory of ASIC & System, Fudan University), Bill Yang Liu (Analog Device Corp),Zhiliang Hong (State Key Laboratory of ASIC & System, Fudan University)

B1-6 Design of Dual-Wideband Low Noise Amplifier base on Common Gate Topology 181

Meng-Ting Hsu, Po-Yu Lee, Yu-Zhang Huang (Department and Institute of Electronic Engineering National Yunlin University of Science and Technology)

SESSION B2

Analog-to-Digital Converters (I)

XVIII

B2-1 Quantitative Analysis for High Speed Interpolated/Averaging ADC (invited paper) 185

He Tang, Yong Peng, Xiang Lu, Hai Wang (Univ. of Elec. Sci. and Tech. of China), Albert Wang (Department of Electrical, University of Califomia)

B2-2 Folding and Interpolation ADC Design Methodology (invited paper) 189

Siqiang Fan (Fairchild Semiconductor), Albert Wang (University of California, Riverside), Bin Zhao (Fairchild Semiconductor)

B2-3 A 10-bit Pipelined ADC with Improved S/H Circuit for CMOS Image Sensor 193

Yiling Ding, Qi Zhang, Ning Wang, Dunshan Yuan, Guohong Li, Hui Wang, Songlin Feng (Shanghai Advanced Research Institute, Chinese Academy of Sciences)

B2-4 An 8-bit 100KS/s Low Power Successive Approximation Register ADC for Biomedical Applications 197

Xiao Yan, Lingzhi Fu, Junyu Wang (Fudan University)

SESSION B3

RF Circuits

B3-1 A 5kV ESD-Protected 2.4GHz PA in 180nm RFCMOS Optimized by ESD-PA Co-Design Technique (invited paper) 201

Zitao Shi (Marvell Tech. Group Ltd. Shanghai, China), Xin Wang(Omni Vision Technologies), Albert Wang (Dept. of Electrical Engineering, University of California, Riverside, USA), Yuhua Cheng (SHRIME, Peking University, China)

B3-2 RF Design and Technology Supporting Active Safety in Automotive Applications (invited paper) 205

Massimo Gimignani, Mario Paparo, Domenico Rossi, Salvo Scaccianoce (STMicroelectronics)

B3-3 A 800nW High-Accuracy RC Oscillator with Resistor Calibration for RFID 209

Jinhai Zhang, Bo Wang, Yi Peng, Tongning Hu, Xin’an Wang (School of ECE Peking University Shenzhen Graduate School)

B3-4 A CMOS Passive Mixer-First Receiver Front-end for UHF RFID Reader 213

Zhiheng Lin, Xi Tan, Hao Min (AUTO-ID Laboratory of Fudan University)

B3-5 An adaptive Q factor tuning and input impedance matching method for ultra-low power front end of UHF RFID tag 217

Chong Huang (UNICORETECH.LTD.COM.CN), Xiaochen Gu (College of electronic

XIX

science and engineering, National University of defense technology, Changsha, China), Lei Cai (Faculty of Materials, Optoelectronics and Physics, Xiangtan University), Cong Li, Dun Yan, Bingbing Zhang, Qin Qin, Hongyi Wang, Jiancheng Li (College of electronic science and engineering, National University of defense technology, Changsha, China)

B3-6 A high conversion coefficient RF front end of ultra-low power RFID tag 221

Chong Huang (UNICORETECH.LTD.COM.CN), Xiaochen Gu (College of electronic science and engineering, National University of defense technology, Changsha, China), Lei Cai (Faculty of Materials, Optoelectronics and Physics, Xiangtan University), Cong Li, Dun Yan, Bingbing Zhang, Qin Qin, Hongyi Wang, Jiancheng Li (College of electronic science and engineering, National University of defense technology, Changsha, China)

SESSION B4

Clock Synthesizer and Building Blocks

B4-1 A 24 GHz Reconfiguarble Frequency Synthesizer for 60 GHz WPAN (invited paper) 225

Nagarajan Mahalingam, Yisheng Wang, Kaixue Ma, Shou Xian Mou, Kiat Seng Yeo (Nanyang Technological University, Singapore)

B4-2 Low Spur CMOS Phase-Locked Loop with Wide Tuning Range for CMOS Image Sensor 229

Zhiqing Chen, Qi Zhang, Ning Wang, Dunshan Yuan, Guohong Li, Hui Wang, Songlin Feng (Shanghai Advanced Research Institute, Chinese Academy of Sciences)

B4-3 Design of Frequency Synthesizer in Frequency-Hopping Transceiver 233

Yong Xu (Institue of Communication Engineering, PLA University of Science and Technology), Fei Zhao (PLA University of Science and Technology), Chen Hu, Zheng Sun, Yuanliang Wu, Jianwen Lu

B4-4 Design of Drain-gate Transformer Feedback VCO With Body-biasing 237

Meng-Ting Hsu, Jie-An Huang, Yao-Yan Lee (Department and Institute of Electronic Engineering, National Yunlin University of Science and Technology)

B4-5 A Reference Spur Estimation Method for Integer-N PLLs 241

Bo Wang, Jinhai Zhang (Peking University Shenzhen Graduate School), Edouard NGOYA (XLIM, UMR CNRS 7252, University of Limoges)

B4-6 A Fast and Accurate Automatic Frequency Calibration Scheme for Frequency

XX

Synthesizer 245

Yan Dun, Jiancheng Li, Songting Li, Xiaochen Gu, Chong Huang (National University of Defense Technology)

B4-7 A 30.4% tuning range Quadrature LC VCO using Class-C structure N/A

Zibo Zhou, Wei Li, Ning Li, Junyan Ren (ASIC Laboratory, Department of Microelectronics)

SESSION B5

Wireless transceiver and building blocks

B5-1 A 10-Gb/s Simplified Transceiver with a Quarter-Rate 4-Tap Decision Feedback Equalizer in 0.18- m CMOS Technology 249

Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Liji Wu, Zhihua Wang (Institute of Microelectronics, Tsinghua University)

B5-2 A 10Gb/s Analog Equalizer in 0.18um CMOS 253

Linghan Wu, Ziqiang Wang, Ke Huang, Shuai Yuan, Xuqiang Zheng, Chun Zhang, Zhihua Wang (Tsinghua University)

B5-3 A Widely-tunable Multi-standard Direct-Conversion CMOS TV Receiver for Direct Broadcasting Satellite Service N/A

Songting Li, Jiancheng Li, Xiaochen Gu, Dun Yan, Hongyi Wang, Zhaowen Zhuang (National University of Defense Technology)

B5-4 Design of novel high speed dual-modulus prescaler based on new optimized structure 257

Zheng Sun, Yong Xu, Chen Hu, Guangyan Ma, Yuanliang Wu, Ying Huang (PLA University of Science and Technology)

B5-5 A Finite Gain Bandwidth Compensation Method for Low Power Continouts-time

Modulator 261 Zemin Feng, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren (Fudan University)

B5-6 A 80-dB DR, 10-MHz BWContinuous-Time Sigma-Delta Modulator with Low Power Comparators and Switch Drivers 265

Yuzhong Xiao , Chixiao Chen, Rui Wei, Fan Jiang, Jun Xu, Junyan Ren (Fudan university)

B5-7 A Novel Equalizer for the High-loss Backplane at Nyquist Frequency 269

You Li, Feng Zhang, Yumei Zhou (Institute of Microelectronics of Chinese Academy of

XXI

Sciences)

B5-8 Dual Control Mode AGC for Wireless Communication System 273

Fan Meng, Rui Guan, Dongpo Chen (Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiao Tong University)

SESSION B6

Analog Circuits (I)

B6-1 A Nonlinear Weighted PID Controlled 12V to 1V DC-DC Converter with Transient Suppression (invited paper) 277

Chu-Hsiang Chia, Pui-Sun Lei, Robert Chen-Hao Chang, Wei-Chih Wang (National Chung Hsing University)

B6-2 An Integrated Zigbee Transmitter and DC-DC Converter On 0.18μm HV and RF CMOS Technology (invited paper) 281

Chaojiang Li, Dawn Wang, Myra Boenke, Ted Letavic, John Cohn (IBM)

B6-3 A 25-Gb/s 32.1-dB CMOS Limiting Amplifier for Integrated Optical Receivers (invited paper) 285

Zhengxiong Hou, Yipeng Wang, Quan Pan, C. Patrick Yue (The Hong Kong University of Science and Technology)

B6-4 A Novel Dynamic Element Match Technique in Current-Steering DAC 289

Baoguang Liu, Yuan Wang, Guangliang Guo, Song Jia, Xing Zhang (Institute of Microelectronics, Peking University)

B6-5 A Practical Method for Auto-Design and Optimization of DC-DC Buck Converter 293

Guanming Huang, Dian Zhou (University of Texas at Dallas), Xuan Zeng (Fudan University), Shengguo Wang (University of North Carolina at Charlotte)

SESSION B7

Analog Circuits (II)

B7-1 Design Automation of Analog Circuit Considering the Process Variations (invited paper) 297

Dian Zhou, Guanming Huang (University of Texas at Dallas)

XXII

B7-2 A Process Variation Insensitive Bandgap Reference with Self-Calibration Technique 301

Ling Du, Ning Ning, Kejun Wu, Yang Liu, Qi Yu (University of Electronic Science and Technology of China)

B7-3 A CMOS PGA with DCOC and I/Q mismatch calibration 305

Xingpeng Pan, Rui Guan, Dongpo Chen (Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiao Tong University)

B7-4 VCCS Controlled LDO with Small On-Chip Capacitor 309

Qiuli Li, Yao Qian, Danzhu Lv, Zhiliang Hong (State Key laboratory of ASIC and Systems, Fudan University)

B7-5 Analog Routing Considering Min-Area Constraint 313

Weijie Chen, Hailong Yao, Yici Cai, Qiang Zhou (Tsinghua University)

B7-6 3D Hybrid Modeling of Substrate Coupling Noise in Lightly Doped Mixed-Signal ICs 317

Yongsheng Wang, Fang Li, Hualing Yang, Yonglai Zhang, Yanhui Ren (Harbin Instritute of Technology)

B7-7 A VCO with F-V Linearization Techniques for CNS Application 321

Peng Chen, Rui Guan, Dongpo Chen (Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiao Tong University)

SESSION B8

Digital Circuits

B8-1 Self-Synchronous Circuit Designs, SSFPGA and SSRSA for Low Voltage Autonomous Control and Tamper Resistivity (invited paper) 325

Makoto Ikeda (University of Tokyo)

B8-2 Key Component Designs of Subthreshold Baseband Processors in Passive RF Device (invited paper) 329

Weiwei Shi (Shenzhen University), Chiu-Sing Choy (Chinese University of Hong kong), Robert Teng

B8-3 Controlling-Value-Based Power Gating Considering Controllability Propagation and Power-off Probability 333

Zhe DU, Yu JIN, Shinji KIMURA (Waseda University)

XXIII

B8-4 Robust Current-Mode On-Chip Interconnect Signaling Scheme in Deep Submicron 337

Xinsheng Wang, Mingyang Hu, Mingyan Yu (Harbin Institute of Technology)

B8-5 An Extensible and Real-time Compressive Sensing Reconstruction Hardware for WBANs using OMP 341

Weijing Shi, Yi Li, Jun Han, Xu Cheng, Xiaoyang Zeng (State Key Laboratory of ASIC and System, Fudan University)

B8-6 Improved Unified Interconnect Unit for High Speed and Scalable FPGA 345

Lei Li, Jian Wang, Jinmei Lai (Department of Microelectronics, Fudan University)

SESSION C1

CAD for system, Design for Manufacturing and Testing (I)

C1-1 Developing a Design System to Help Reduce Design Cycle Time (invited paper) 349 Jing Li (Staff Engineer), Xingang Wang (Director, Design Enablement)

C1-2 Oscillator Phase Noise Verification Accounting for Process Variations 353 Liuxi Qian, Dian Zhou, Xuan Zeng, Shengguo Wang (University of Texas at Dallas)

C1-3 Weight-Based FPGA Placement Algorithm with Wire Effect Considered 357

Huagang Li, Jian Wang, Jinmei Lai (State Key Laboratory of ASIC and System, Fudan University)

C1-4 Graph Steiner Tree Construction and Its Routing Applications 361

Jun Dong, Hengliang Zhu, Min Xie, Xuan Zeng (Department of Microelectronics, Fudan University)

SESSION C2

CAD for system, Design for Manufacturing and Testing (II)

C2-1 Lithography Hotspot Detection and Mitigation in Nanometer VLSI (invited paper) 365 Jhih-Rong Gao, Bei Yu, Duo Ding, David Z Pan (University of Texas at Austin)

C2-2 A New Splitting Graph Construction Algorithm for SIAR Router 369

XXIV

Jinming Zhao, Hailong Yao, Yici Cai, Qiang Zhou (Tsinghua University)

C2-3 Data Dependency Aware Prefetch Scheduling for Dynamic Partial Reconfigurable Designs 373

Jixin Zhang (Tsinghua University, Wuhan University of Technology), Ning Xu (Wuhan University of Technology), Yuchun Ma, Yu Wang, Jinian Bian (Tsinghua University)

C2-4 Incremental 3D NoC Synthesis based on Physical-aware Router Merging Algorithm 377

Yuanyuan Li (School of Computer Science and Technology, WuHan University of Technology;Department of Computer Science and Technology, Tsinghua University), Ning Xu (School of Computer Science and Technology, WuHan University of Technology), Yuchun Ma, Jinian Bian (Department of Computer Science and Technology, Tsinghua University)

SESSION C3

VLSL New Processing, New Technologies and their integration (I)

C3-1 A 65-nm CMOS P-well/Deep N-well Avalanche Photodetector for Integrated 850-nm Optical (invited paper) 381

Quan Pan, Zhengxiong Hou, Yipeng Wang, C. Patrick Yue (Department of Electronic and Computer Engineering, HKUST)

C3-2 PEALD Ru / RuOx Films for ULSI Applications and Its Transition Control between Metal and Metal Oxide 385

Chun-Min Zhang, Qing-Qing Sun, Peng-Fei Wang, David Wei Zhang (State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University)

C3-3 An Improved Analytical Series Resistance Model for On-Chip Stacked Inductors 389

Wanghui Zou, Xiaofei Chen, Xuecheng Zou (Hunan University)

C3-4 Design and Implementation of Transaction Level Processor based on UVM 393

Yingke Gao, Diancheng Wu, Quanquan Li, Tiejun Zhang, Chaohuan Hou (Digital System Integration Lab, Institute of Acoustics, Chinese Academy of Sciences)

C3-5 Compact and portable chemiluminescence detector for glucose 397

Kaidi Zhang, Guowei Tao, Xiangyu Zeng, Wenjie Sheng, Jia Zhou (Fudan University)

SESSION C4

XXV

Circuits Simulation, Synthesis, Verification and Physical design (I)

C4-1 Interconnect Waveform Calculation Method with Parameter Variation (invited paper) 401

Goro Suzuki, Ryo Yamanaka (Univ. of Kitakyushu)

C4-2 A Sorting-Based IO Connection Assignment for Flip-Chip Designs 405 Ran Zhang, Xue Wei, Takahiro Watanabe (Waseda University)

C4-3 Incremental Symbolic Construction for Topological Modeling of Analog Circuits 409 Hanbin Hu, Guoyong Shi, Yan Zhu (Shanghai Jiao Tong University)

C4-4 Parameter and UVM, Making a Layered Testbench Powerful 413 Geng Zhong, Jian Zhou, Bei Xia (Department of Microcontroller, Freescale)

C4-5 Mixed-signal System Verification by SystemC/SystemC-AMS and HSIM-VCS in Near Field Communication Tag Design 417

Zhaori Bi, Wei Li, Dian Zhou (Eric Jonsson School, The University of Texas at Dallas, Richardson 75080, U.S.A.), Xuan Zeng (State Key Lab. of ASIC & System, Fudan University, Shanghai 200433, China), Sheng-Guo Wang (College of Engineering, University of North Carolina at Charlotte, Charlotte, NC 28223, U.S.A)

C4-6 Power and Resource Aware Scheduling with Multiple Voltages 421

Haoran Zhang (Waseda University), Cong Hao (Shanghai Jiao Tong University), Nan Wang (Waseda University), Song Chen (University of Science and Technology of China), Takeshi Yoshimura (Waseda University)

C4-7 The Timing Control Design of 65nm Block RAM in FPGA 425

Xinrui Zhang, Jian Wang, Dan Chen, Jinmei Lai (State Key Laboratory of ASIC and System, Fudan University), Lichun Bao, Xueling Liu (BACC)

SESSION C5

Circuits Simulation, Synthesis, Verification and Physical design (II)

C5-1 Compact Modeling of the Diode Reverse Recovery Effect for Leading Developments of Power Electronic Applications (invited paper) 429

Masataka Miyake, Kai Matsuura, Akifumi Ueno (Hiroshima University)

C5-2 Lagrangian Relaxation Based Pin Assignment and Through-Silicon Via Planning for 3-D SoCs 433

XXVI

Wei Zhong(Waseda University), Song Chen (University of Science and Technology of China), Yang Geng, Takeshi Yoshimura (Waseda University)

C5-3 An Acceleration Method by GPGPU for Analytical Placement using Quasi-Newton Method 437

Syota Kuwabara, Yukihide Kohira (The University of Aizu), Yasuhiro Takashima (The University of Kitakyushu)

C5-4 FFTPL: An Analytic Placement Algorithm Using Fast Fourier Transform for Density Equalization 441

Jingwei Lu (Department of Computer Science and Engineering, University of California, San Diego), Pengwen Chen (Department of Applied Mathematics, National Chung Hsing University), Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng (Cadence Design Systems), Chung-Kuan Cheng (Department of Computer Science and Engineering, University of California, San Diego)

C5-5 Power Grid Simulation using Matrix Exponential Method with Rational Krylov Subspaces 445

Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng (Department of Computer Science and Engineering, University of California, San Diego)

C5-6 Interconnection Allocation Between Functional Units And Registers in High Level Synthesis 449

Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura, Min-You Wu (Shanghai Jiao Tong University)

C5-7 Timing and Resource Constrained Leakage Power Aware Scheduling in High-Level Synthesis 453

Nan Wang (Graduate School of Information, Production and Systems, Waseda University), Cong Hao (Shanghai Jiao Tong University), Nan Liu, Haoran Zhang, Takeshi Yoshimura (Graduate School of Information, Production and Systems, Waseda University)

SESSION C6

MEMS, Nanoelectronics, and New Device (I)

C6-1 Design and Analysis of Nano-scale Bulk FinFETs (invited paper) 457 Jong-Ho Lee, Kyu-Bong Choi, Jongmin Shin (Seoul National University)

C6-2 Network Functions for Characterization of Semiconductor Nanostructures (invited paper) 460

XXVII

Thomas Wong (Illinois Institute of Tchnology), Tao Shen (Kunming University of Science and Technology)

C6-3 Fabrication of Silicon-Based MEMS Capacitive Microphone Structure with Thin Starting Wafer 464

Xiaoxu Kang, Chao Yuan, Qingyun Zuo, Changwa Yao, Shoumian Chen, Yuhang Zhao, Yilin Yan, Yuanjun Xu, Weiping Zhou (Shanghai IC R&D Center)

C6-4 Ultra-low frequency P(VDF-TrFE) piezoelectric energy harvester on flexible substrate 467

Zhaoyang Pi, Lun Zhu, Jingwei Zhang, Dongping Wu, David Wei Zhang (Department of Microelectronics, Fudan University), Zhi-Bin Zhang, Shi-Li Zhang (Solid-State Electronics, The Ångström Laboratory, Uppsala University)

C6-5 Ag dendrite formed on the Cu pyramids as SERS substrate 471

Peng-Fei Nan, Xu Wang, Xin-Ping Qu (State key lab of ASIC and system, Department of Microelectronics, Fudan University)

C6-6 Simulation Design for Continuous Separating and 3D Focusing of Particles Based on Inertial Microfluidics 474

Jian Li, Xiangyu Zeng, Jia Zhou (ASIC and System State Key Lab, Department of Microelectronics, Fudan University)

SESSION C7

MEMS, Nanoelectronics, and New Device (II)

C7-1 Graphene electronics and photonics (invited paper) 478 Tony Low (IBM TJ Watson Research Center)

C7-2 Toward Microwave Integrated Circuits on Flexible Substrates (invited paper) 480

Jung-Hun Seo (University of Wisconsin-Madison), Weidong Zhou (University of Texas at Arlington), Zhenqiang Ma (University of Wisconsin-Madison)

C7-3 An Empirical Model for Static I-V Characteristics of Double Gate Tunneling Field Effect Transistor 484

Daming Huang, Chengjun Yao, Daohang Shi, Mingfu Li (Department of Microelectronics Fudan University)

C7-4 A New High Performance RF LDMOS with Vertical n+n-p-p+ Drain Structure 488

XXVIII

Xiaofei Chen, Yading Shen, Xuecheng Zou (Department of Microelectronics, Huazhong University of Science and Technology), Shuangxi Lin, Wanghui Zou

SESSION C8

MEMS, Nanoelectronics, and New Device (III)

C8-1 Transition Metal Dichalcogenides – A New Material Class for Semiconductor Electronics? (invited paper) 492

Frank Schwierz (Technische Universität Ilmenau)

C8-2 Integrated Amorphous-Si TFT Circuits for Gate Drivers on LCD Panels (invited paper) 496

Nan-Xiong Huang (Feng Chia University), His Rong Han, Wen Tui Liao, Chih Hung Huang, Wen Chun Wang (Wintek Corp.), Miin-Shyue Shiau, Ching-Hwa Cheng, Hong-Chong Wu, Heng-Shou Hsu, Juin J. Liou (Central Florida University), Shry-Sann Liao (Feng Chia University), Ruei-Cheng Sun, Guang-Bao Lu (Fu Jian University of Technology), Don-Gey Liu (Feng Chia University)

C8-3 Growth of semiconducting 2D layered materials on graphene (invited paper) N/A

W. Wang, K. K. Leung, Y. Y. Hui, P.W.K. Fong, S.P. Lau, C. Surya (The Hong Kong Polytechnic University)

C8-4 A Novel Scaling Theory for Fully-Depleted Omega-Gate( G) MOSFETs (invited paper) 500

Gao, Hong-Wun, Te-Kuang Chiang (Member, IEEE)

SESSION D1

Testing, Reliability, Fault-Tolerance (I)

D1-1 Building-In Reliability in BCD (Bipolar-CMOS-DMOS) Technologies (invited paper) 503

Jifa Hao, T. E. Kopley (Fairchild Semiconductor)

D1-2 Networking Industry Trends in ESD Protection for High Speed IOs (invited paper) 507 Richard Wong, Rita Fung, Shi-Jie Wen (Cisco Systems)

D1-3 Two Sides of Pulse Quenching Effect on the Single Event Transient Pulse Width at Circuit-Level 511

XXIX

Bin Liang, Yankang Du (College of Computer, National University of Defense Technology)

D1-4 A Novel Test Scheme for NAND Flash Memory Based on Built-in Oscillator Ring 515

Si Chen, Xiaole Cui, Chung-Len Lee (Peking University Shenzhen Graduate School)

SESSION D2

Testing, Reliability, Fault-Tolerance (II)

D2-1 A Test Pattern Selection Method for Dynamic Burn-in of Logic Circuits Based on ATPG Technique 519

Xuan Yang, Xiaole Cui, Chao Wang, Chung-Len Lee (Peking University Shenzhen Graduate School)

D2-2 Gate Oxide Enhancement for Whole Chip ESD Design between Different Power Domains 523

Hongwei Li, Guang Chen, Huijuan Cheng (SMIC)

D2-3 Novel Gate-Voltage-Bias Techniques for Gate-Coupled MOS (GCMOS) ESD Protection Circuits 527

Guangyi Lu, Yuan Wang, Jian Cao, Song Jia, Ganggang Zhang, Xing Zhang (Insititue of Microelectronics, Peking University)

D2-4 A Cost-Effective Method for Masking Transient Errors in NoC Flit Type 531

Jiajia Jiao, Yuzhuo Fu (Shanghai Jiao Tong University)

SESSION D3

Analog-to-Digital Converters (II)

D3-1 Digital Calibration Techniques for Interstage Gain Nonlinearity in Pipelined ADCs (invited paper) 535

Chaojie Fan, Wenjie Pan, Ke Wang, Jianjun Zhou (Shanghai Jiao Tong University)

D3-2 Design Philosophy of Hysteretic Controller for for DC-DC Switching Converters (invited paper) 539

Jian Lv, Simao S.Ang (Department of Electrical Engineering University of Arkansas, USA)

XXX

D3-3 A High-Speed Front-End Circuit Used in a 16bit 250MSPS Pipelined ADC 543

Ting Li, Dongbing Fu, Yong Zhang, Yan Wang, Lu Liu, Xu Wang (Science and Technology on Analog Integrated Circuit Lab)

D3-4 A 300MHz 10bit Time-Interleaved Pipelined-SAR ADC 547

Lu Sun, Yuxiao Lu, Tingting Mo (Center for Analog/RF IC (CARFIC), School of Microelectronics, Shanghai Jiao Tong University)

D3-5 Calibration for Split Capacitor DAC in SAR ADC 551

Zhe Li, Yuxiao Lu, Tingting Mo (Center for Analog/RF IC (CARFIC), School of Microelectronics,Shanghai JiaoTong University)

SESSION D4

Advanced Memory

D4-2 Conduction Mechanism of Self-Rectifying n+Si-HfO2-Ni RRAM 555

D.Y. Lu (State Key Lab ASIC and System, Department of Microelectronics, Fudan University), X.A. Tran (Nanyang Technological University), H.Y. Yu (South University of Science and Technology of China), D.M. Huang, Y.Y. Lin, S.J. Ding, P.F. Wang, Ming-Fu Li (State Key Lab ASIC and System, Department of Microelectronics, Fudan University)

D4-3 Low-Power High-Yield SRAM Design with VSS Adaptive Boosting and BL Capacitance Variation Sensing 559

Ningxi Liu, Yu Jiang, Qing Dong, Hui Li, Xinyi Hu, Yinyin Lin (Fudan University)

D4-4 A Novel Soft Error Immunity SRAM cell N/A

Jinming Huang, Xin Zhao, Yongqin Huang (ShangHai high performance IC design center)

D4-5 A 2Mb ReRAM with two bits error correction codes circuit for high reliability application 563

Jianguo Yang, Ying Meng, Xiaoyong Xue, R. Huang, Q.T. Zhou, J.G. Wu, Yinyin Lin (Fudan University)

SESSION D5

Circuits and Systems for Wireless Communications (II)

XXXI

D5-1 FFT Design for OFDM-based Cognitive Radio Using a Reconfigurable Baseband Processing Architecture (invited paper) 567

Wenqing Lu (Fudan University), Gerald E. Sobelman (University of Minnesota), Xiaofang Zhou, Junyan Ren (Fudan University)

D5-2 VLSI Design of Fuzzy-Decision Bit-Flipping QC-LDPC Decoder 571

wenzhe zhao (Institute of Artificial Intelligence and Robotics, Xi'an Jiaotong University), minjie lv, hongbin sun, nangning zheng (Xi'an Jiaotong University), tong zhang (Renssellar Polytechnic Institute)

D5-3 A High-Throughput LDPC decoder For Optical Communication 575

Di Wu, Yun Chen, Yuebin Huang, Yeongluh Ueng, Lirong Zhang, Zeng Xiaoyang (Fudan University)

D5-4 Reduced Complexity Implementation of Quasi-Cyclic LDPC Decoders by Parity-Check Matrix Reordering 579

Jianing Su (Advanced Circuit and System Lab, Suzhou Institute of Nano-tech and Nano-Bionics, Chinese Academy of Sciences), Zhenghao Lu (Department of Electronics and Information Science, Soochow University)

D5-5 A Novel Joint Estimation and Compensation Algorithm for Non-idealities of Analog Front-end in DC-OFDM System 583

Jiasen Huang, Hao Chen, Junyan Ren, Fan Ye (Institution of Microelectronics of Fudan University)

SESSION D6

VLSL New Processing, New Technologies and their integration (II) Title

D6-1 Investigation on Effectiveness of Series Gate Resistor in CDM ESD Protection Designs (invited paper) 587

Yuanzhong(Paul) Zhou, Alan W.Righter, Jean-Jacques Hajjar (Analog Devices Inc.)

Post Session (I)

P1-01 An Interference Miss Isolation Mechanism based on Skewed Mapping for Shared Cache in Chip Multiprocessors 591

Anwen Huang, Chao Song, Wei Guo, Peng Li, Minxuan Zhang (School of Computer Science, National University of Defense Technology)

XXXII

P1-02 Low Power Design for FIR Filter 595

Gaowei Xu, Yao Zou, Jun Han, Xiaoyang Zeng (State Key Laboratory of ASIC and System, Fudan University)

P1-03 Design and Implementation of a Dynamic Loop Buffer by Reusing the Instruction Buffer 599

Qi Wang, Yingke Gao, Donghui Wang, Tiejun Zhang, Chaohuan Hou (Digital System Integration Lab, Institute of Acoustics, Chinese Academy of Sciences)

P1-04 Design of a Hybrid Reconfigurable Coprocessor 603

Xiang Wang, Su Zhang, Wei Ni, Yukun Song (Institute of VLSI Design. Hefei University of Technology), Yanhui Yang, Jichun Bu (LZeal Information Technology Co., Ltd)

P1-05 A Novel Inverse Quantization Algorithm Based on Taylor Series for Digital Audio Codecs 607

fan liu (Sichuan Institute of Solid State Circuits, China Electronics Technology Group Corp.), Junfeng Zhu (Actions Semiconductor Co., Ltd., Zhuhai 519085, P.R.China)

P1-06 Genetic Algorithm Based Pipeline Scheduling in High-level Synthesis 610

Xiaohao Gao, Takeshi Yoshimura (Waseda University)

P1-07 A FPGA REAL-TIME STEREO VISION SYSTEM WITH LUMINANCE CONTROL AND PROJECTED PATTERN 614

XU Yuan, YAO Haodong, GONG Liwei, ZHU Mingcheng (Shenzhen University), Robert K.F. Teng (California State University, Long Beach)

P1-08 An Adaptive Multi-modulus Frequency Divider 618

YUAN Hengzhou, MA Zhuo, GUO Yang(College of Computer Science, National University of Defense Technology)

P1-10 Implementation of H.264 Intra-frame Encoding on Clustered Stream Architectures 622

Zhixiang Chen (Tsinghua University), Yi Fang, Fang Wang, Zhaolin Li

P1-11 Frame Synchronization for a Narrow-Band Power Line OFDM Communication System 626

Xiaoxue Yu, Hong Liu, Hao Min (Auto-ID Lab)

P1-12 A Low-Power Ternary Content-Addressable Memory Using Pulse Current Based Match-Line Sense Amplifiers 630

Meng-Chou Chang, Shih-Ju Tsai (National Changhua University of Education)

XXXIII

P1-13 An equalization system for 2 series-connected Li-ion batteries 634

Jiang Jinguang (GNSS Research Center, Wuhan University), Li Sen (School of Physics and Technology, Wuhan University)

P1-14 A Novel Architecture of Local Memory for Programmable SIMD Vision Chip 637

Zhe Chen, Jie Yang, Cong Shi, Nanjian Wu (Institute of Semiconductors, Chinese Academy of Sciences)

P1-15 Pseudo Dual Path Processing to Reduce the Branch Misprediction Penalty in Embedded Processors 641

huatao zhao, Jiongyao ye, yuxin sun, Takahiro watanabe (waseda university)

P1-16 A Fast Multi-core Virtual Platform and its Application on Software Development 645

Zongyan Wang, Dexue Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng (State Key Laboratory of ASIC and System, Fudan University)

P1-17 A Turbo Decoder Implementation for LTE Downlink Mapped on a Multi-Core Processor Platform 649

Qing Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng (Fudan University)

P1-18 H.264 Video Parallel Decoder on a 24-Core Processor 653 Shikai Zhu, Zheng Yu, Shile Cui, Zhiyi Yu, Xiaoyang Zeng (Fudan University)

P1-19 Highly Stable Data SRAM-PUF in 65nm CMOS Process 657 Xuelong Zhang, Pengjun Wang, Yuejun Zhang (Ningbo University)

P1-20 Design and Implementation of RSA for Dual Interface Bank IC Card 661 Jiajia Shao, Liji Wu, Xiangmin Zhang (Tsinghua University) P1-21 A Reconfigurable Floating-Point FFT Architecture 665

Chenlu Wu, Wei Cao, Xuegong Zhou, Lingli Wang (The State Key Laboratory of ASIC and System, Fudan University), Baodi Yuan, Fang Wang (Wuxi Topwin Technology Co. Ltd)

P1-22 A Clocked Differential Switch Logic Using Floating-Gate MOS Transistors 669

Guoqiang Hang, Yang Yang (Zhejiang University City College), Peiyi Zhao, Xiaohui Hu, Xiaohu You

P1-23 An Area-Efficient Implementation of ADC Multistage Decimation Filter 673

Chenxi Deng (Peking University)

P1-24 A Design of Configurable Image Enhancement Unit 678

Zhiyuan Xue, Huan Ying, Yingke Gao, Tiejun Zhang, Donghui Wang, Chaohuan Hou (Institute of Acoustics, Chinese Academy of Sciences)

XXXIV

P1-25 A Novel Energy-Oriented Reconfigurable on-chip Unified Memory Architecture Based on Cache Behavior Phase Graph 682

WU Jianping, Ling Ming, Zhang Yang, Mei Chen, Wang Huan (IC Department, Southeast University)

P1-27 The Decimator with Multiplier-free Realizations for High Precision ADC Applications 687

Yiwu Yao, Kailiang Zhang, Hongming Chen, Yuhua Cheng (Peking University)

P1-28 Implementation of an Embedded Dual-Core Processor for Portable Medical Electronics Applications 691

Yingrui Chen, Teng Wang, Xin’an Wang (Peking University Shenzhen Graduate School), Ziyi Hu (Institute of Microelectronics of Chinese Academy of Sciences)

P1-29 A Novel Architecture Scheme with Adaptive Pipeline Coupling Technique for DSP Processor Design 695

Zheng Tang, Jing Xie, Zhigang Mao (Department of Microelectronics, Shanghai Jiao Tong University)

P1-31 Positionable Wearable Fall Detection System for Elderly Assisted Living Applications 699

Jie Cheng, Yun Chen, Wenxu Bao, YuanZhou Hu, Na Ding, Xiaoyang Zeng (The State-Key Lab of ASIC and System,Fudan University)

P1-32 Mixed-Signal SoC Design and Low Power Research for Tire Pressure Monitoring Systems 703

Yangyang Guo, Liji Wu, Tengfei Zhai, Xiao Yu, Xiangmin Zhang (Tsinghua University)

P1-33 A Semi-auto Interactive 2D-to-3D Video Conversion Technique Based on Edge Detection 707

Tianyi Hu (Department of Microelectronics, Fudan University)

P1-34 Secure Systolic Architecture for Montgomery Modular Multiplication Algorithm 711

Qi Yang (School of Computer, Wuhan University), Xiaoting Hu, Zhongping Qin (School of Software, Huazhong University of Science and Technology)

P1-35 A GFSK transceiver for IEEE Std. 802.15.4g used in China 715

Maoqiang Duan (Lab of Industrial Control Network and System Shenyang Institute of Automation, Chinese Academy of Sciences), Xiaoli Huang (Competitive Intelligence Center Institute of Scientific & Technical Information of Liaoning Province), Zhijia Yang

P1-36 A CMOS Low-Noise Amplifier for BCC Applications 719

XXXV

Zhige Zou, Wuyue Wang, Jianming Lei, Guoyi Yu, Xuecheng Zou (Department of Micro-electronic Engineering School of Optical and Electronic Information)

P1-37 Automatic Gain Control Algorithm with High-Speed and Double Closed-loop in UWB System 723

Bing Jing, Yuankun Xue, Fan Ye, Ning Li, Junyan Ren (Fudan university)

P1-38 An NFC system with high sensitivity based on SDR 727

Longxiang Zhang, Hantian Xu, Yingbo Dai, Hao Min (AUTO-ID Laboratory of Fudan University)

P1-39 A Configurable Distributed Systolic Array for QR Decomposition in MIMO-OFDM Systems 731

Yongxu Zhu, Bin Wu, Yumei Zhou, Kaifeng Xia, Lu Sun (Institute of Microelectronics, Chinese Academy of Sciences)

P1-40 A Collision and Tag Number Detector for UHF RFID Reader Conforming to EPC Gen2 Protocol 736

Lingzhi Fu, Xiao Yan, Junyu Wang (Fudan University)

P1-41 A Wideband CMOS Variable-Gain Low Noise Amplifier with Novel Attenuator 740

Tao Cheng, Tao Yang, Xin Wang, Zhangwen Tang (ASIC & System State Key Laboratory, Fudan University)

P1-42 Enhanced Error Correction against Multiple-Bit-Upset Based on BCH Code for SRAM 744

Weijia Ma, Xiaole Cui, Chung-Len Lee (Peking University Shenzhen Graduate School)

P1-43 A Novel Structure of Dynamic Configurable Scan Chain - Bypassing Unconcerned Segments on the Fly 748

Shengye Wang, Wei Cao, Lingli Wang (State Key Lab of ASIC and System, Fudan University), Na Wang, Ping Tao (East China Institute of Computer Technology)

P1-44 New DfT Architectures for 3D-SICs with a Wireless Test Port 752

Yibo He, Xiaole Cui, Chung-Len Lee (Peking University Shenzhen Graduate School), Xiaoxin Cui, Yufeng Jin (Peking University)

P1-45 Polarity Dependent of Gate Oxide Breakdown from Measurements 756

Shili Wu, Xiaowei He, Yuwei Liu, Guoan Chen (CSMC Technologies Corporation)

P1-46 A Novel ESD Device for Whole-Chip ESD Protection Network of TPMS Mixed Signal SoC 758

Ningyuan Yin, Liji Wu (Tsinghua University), Tengfei Zhai (Institute of Electronics of Chinese Academy of Science), Xiangmin Zhang, Rui Zhu (Tsinghua University)

XXXVI

P1-47 A Current Mode Sense Amplifier with Self-Compensation Circuit for SRAM Application 762

Heqing Xu, Song Jia, Jiyu Chen, Yuan Wang, Gang Du (Department of Microelectronics, Peking University)

P1-48 Novel Operation Scheme and Technological Optimization for 1T bulk Capacitor-less DRAM 766

Hui Li, Wei Zhu, Ningxi Lu, Cunlin Dong, Chao Meng, Yinyin Lin (ASIC and System State Key Lab,Fudan university), Ryan Huang, Qingtian Zou, Jingang Wu (SOC Technology Development Center)

P1-49 Piezoelectric force microscopy study of local bipolar diode current dependence of preferential domain orientation in BiFeO3 thin films with different thicknesses 769

Long He, Zhihui Chen, Anquan Jiang (State Key Laboratory of ASIC and System, Department of Microelectronics, Fudan University)

P1-50 Design and Test of an SRAM Chip 773

Wenbin Liu, Jinhui Wang, Ligang Hou, Hongyan Yang, Jianbo Kang (Beijing University of Technology)

P1-51 A Hardware Implementation of DES with Combined Countermeasure against DPA 777

Xiaoxin Cui, Rui Li, Wei Wei (Peking University), Juan Gu (Shenzhen University), Xiaole Cui (Peking University Shenzhen Graduate School)

Post Session (II)

P2-01 A Linearized V_BE Bandgap Voltage Reference with Wide Temperature Range 781

Chen Xiaofei, Liu Fanhong, Zou Xuecheng (Huazhong University of Science and Technology), Lin Shuangxi (Wuhan Institute of Technology)

P2-02 A novel current-mode versatile filter employing CCCDCC and MO-OTA 785

Sen Li, Jinguang Jiang, Xifeng Zhou, Zeyu Zhang (Wuhan University)

P2-03 Current-mode square-wave converter with current-rectifying function employing MOCCII 790

Sen Li, Jinguang Jiang, Xifeng Zhou, Zeyu Zhang (Wuhan University)

P2-04 Design of A Novel All-CMOS Low Power Voltage Reference Circuit 794

Yusen Xu, Wei Hu, Fengying Huang, Jiwei Huang (Fuzhou university and Fujian Integrated Circuit Design Center)

XXXVII

P2-05 Background Calibration Techniques for Multistage Pipelined ADCs with Dynamic Element Matching and Pseudorandom Noise 798

Que Longcheng, Du Yiying, Lv JIan, Jiang Yadong (UESTC)

P2-06 FMSSQP: An Efficient Global Optimization Tool for the Robust Design of Rail-to-Rail Op-Amp 802

Minghua Li, Dian Zhou (Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, USA), Sheng-Guo Wang (Department of Engineering Technology, University of North Carolina at Charlotte, NC, USA), Xuan Zeng (State Key Laboratory of ASIC & System, Fudan University , China)

P2-07 A High-Efficiency High-Power BUCK Converter Based on Fully N-type Power Transistors 806

Zhuo Wang, Yuan Dong, Xia Wang, Zekun Zhou, Xin Ming, Bo Zhang (State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China)

P2-08 Low Noise Design and Measurement of 32-channel X-ray ROIC 810

Dan Liu, Chuan Jin (The First Research Institute of Ministry of Public Security)

P2-09 Theory and Hardware Implementation of an analog-to-Information Converter Based On Compressive Sensing 814

Sujuan Liu, Meihui Zhang, Wenshu Jiang, Junshan Wang, Peipei Qi (College of Electronic Information and Control Engineering, Beijing University of Technology)

P2-10 A 2.4 mW ,11.7±0.4dB ,3 to 5 GHz Wide-band LNA for Super-Regenerative IR-UWB Receiver 818

Yi Peng, Bo Wang, Tongning Hu, Jinhai Zhang, Xin'an Wang (Shenzhen Graduate School of Peking University)

P2-11 A Three-Stage LDO with Active Feedback Frequency Compensation and Slew-Rate Enhancement 822

Tongning Hu, Bo Wang, Ke Lin, Yi Peng, Xin'an Wang (Shenzhen Graduate School of Peking University)

P2-12 A Folded Current-Reused CMOS Power Amplifier for Low-Voltage 3.0–5.0 GHz UWB Applications 826

Zhengyu Qian, Xiaole Cui, Bo Wang, Xiangrong Zhang, Chung-Len Lee (Peking University Shenzhen Graduate School)

P2-13 A DLL Based Low-Phase-Noise Clock Multiplier with Offset-Tolerant PFD 830

Yuwen Wang, Fan Ye, Junyan Ren (State Key Laboratory of ASIC and Systems, Fudan University)

XXXVIII

P2-14 Co-Design of ESD Protection and LNA in RFIC 834

Yueguo Hao, Qiao Zhang, Xiaopeng Bai, Zitao Shi, Huainan Ma, Yuhua Cheng (Shanghai Research Institute of Micro Electronics (SHRIME),Peking University)

P2-15 CMOS 1.2V Bandgap Voltage Reference Design 838

Chao Feng, Jinhui Wang, Wei Wu, Ligang Hou (Beijing University of Technology), Jianbo Kang

P2-16 A Novel Digital Controller for Boost PFC Converter with High Power Factor and Fast Dynamic Response 842

Daying Sun, Weifeng Sun, Qing Wang, Shen Xu, Shengli Lu (National ASIC System Engineering Research Center, Southeast University)

P2-17 A Proposed Data Converter for Current Signal with Temperature-Compensated Sample Resistor 846

Xiaozong Huang, Luncai Liu, Liu Fan, Jing Zhang, Wengang Huang, Yanlin Zhang, Lei Yu (Analog IC Design Center, Sichuan Institute of Solid-state Circuits, Chongqing, China; State Key Laboratory of Electronic Thin Films and Integrated Devices, UESTC, Chengdu, China)

P2-20 Mixed-Signal Verification Methods for Multi-Power Mixed-Signal System-on-Chip (SoC) Design 849

Chao Liang (freescale semiconductor)

P2-21 An Integrated Stacked Transformer with large inductance at 900MHz 853

Hantian Xu, LongXiang Zhang, Xi Tan, Min Hao (State Key Lab of ASIC & System, Fudan University)

P2-22 Ultra-Low Noise and High PSR LDO Design 857

Jiangpeng Wang (School of Electronic Information, Wuhan University), Jinguang Jiang (GNSS Research Center, Wuhan University)

P2-23 Low-resistance wide-voltage-range analog switch for implantable neural stimulators 861

Yunpu Hu (Institute of Microelectronics, Tsinghua University), Songping Mai, Yixin Zhao (Shenzhen Key Laboratory of Information Science and Technology,Graduate School at Shenzhen, Tsinghua University), Chun Zhang (Institute of Microelectronics, Tsinghua University)

P2-24 A 1.8-V 14-bit Inverter-Based Incremental Sigma Delta ADC for CMOS Image Sensor 865

Biao Wang, Meng Zhang, Xu Cheng, Qi Feng, Xiaoyang Zeng (Fudan University)

P2-25 Low Jitter Clock Driver for High-performance Pipeline ADC 869

XXXIX

Yun Chen, Chaojie Fan, Jianjun Zhou (School of Microelectronics, Shanghai Jiaotong University)

P2-26 A 4-mW 8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC 873

Jian Mei, Jixuan Xiang, Huabin Chen, Fan Ye, Junyan Ren (State Key Laboratory of ASIC & System)

P2-27 A 7.9-fJ/Conversion-Step 8-b 400-MS/s 2-b-per-cycle SAR ADC with A Preset Capacitive DAC 877

Jixuan Xiang, Jian Mei, Hao Chang, Fan Ye (State Key Laboratory of ASIC & System)

P2-28 A High-Performance Current Sensing Circuit with Full-Phase Sampling Capability 881

Ze-kun Zhou, Haiwu Xie, Yue Shi, Chuankui Wu, Jiangang Huang, Xin Ming, Bo Zhang (State key Laboratory of Electronic Thin Films and Integrated Devices)

P2-29 Design of 13.56MHz Power Recovery Circuit with Signal Transmission for Contactless Bank IC Card 885

Yang Li, Liji Wu, Xiangmin Zhang (Tsinghua University)

P2-30 A Small-area Low-power ADC Array for Image Sensor Applications 889 Shengyou Zhong, Libin Yao, Jiqing Zhang (Kunming institute of physics)

P2-31 A Novel Operational Transconductance Amplifier with High Gm Using Improved Differential Current Redistribution Technique (DCRT) 893

Jing Zhu, Yunwu Zhang, Weifeng Sun, Shengli Lu (National ASIC System Engineering Research Center, Southeast University)

P2-32 An Automatic Peak-Valley Current Mode Step-Up/Step-Down DC-DC Converter With Smooth Transition 897

Yanzhao Ma, Shaoxi Wang, Shengbin Zhang, Xiaoya Fan (Northwestern Polytechnical University)

P2-33 A Single Branch Charge Pump without Overstress for RFID Tag 901

Lei Cai (Faculty of Materials, Optoelectronics and Physics, Xiangtan University), Xiaocheng Gu, Jiancheng Li (College of Electronic and Engineering, National University of Defense Technology), Chong Huang (UNICORE Technology), Cong Li (College of Electronic and Engineering, National University of Defense Technology), Qin Qin, Junping Guo

P2-34 A Universal Framework of Dual-Use Model for Both Performance and Functionality Based on the Abstract State Machine 905

Zheng Xie, Xin’an Wang, Zhibin Lian, Qiuping Li, Shanshan Yong (Peking University)

XL

P2-35 Best Polarity Searching for Ternary FPRM Logic Circuit Area Based on Whole Annealing Genetic Algorithm 909

Fei Sun, Pengjun Wang, Haizhen Yu (Ningbo University)

P2-37 An Open 45nm PD-SOI Standard Cell Library Based on Verified BSIM SOI Spice Model with Predictive Technology 913

GONG Liwei, XU Yuan, ZHANG Zhi, SHI Weiwei (Shenzhen University), Robert K.F. Teng (California State University, Long Beach)

P2-38 Characteristics of n-MOSFETs with Stress Effects from Neighborhood Devices 917

Wei Tai, Lele Jiang, Wang Lei, Song Wen, Lifu Chang, Yuhua Cheng (ShangHai Research Institute of MicroElectronics, Peking University)

P2-39 Device Parameter Variations of n-MOSFETS with Dog-bone Layouts 920

Lele Jiang, Song Wen, Wei Tai, Wang Lei, Lifu Chang, Yuhua Cheng(Shrime)

P2-40 An Integrated Development Environment for Reconfigurable Operators Array 923

Shanshan Yong, Xin'an Wang, Ying Cao, Yawei Lu, Zheng Xie (Peking University Shenzhen Graduate School)

P2-41 A Parallel Sparse Linear System Solver for Large-scale Circuit Simulation based on Schur Complement 927

Liuxi Qian, Dian Zhou (University of Texas at Dallas), Xuan Zeng, Fan Yang (Fudan University), Shengguo Wang (University of North Carolina)

P2-42 Evaluation of Cyanoethyl Pullulan material as the dielectric layer for EWOD devices 931

Jianfeng Chen, Yuhua Yu, Xiangyu Zeng, Jian Li, Jia Zhou (ASIC and System State Key Lab, Department of Microelectronics, Fudan University)

P2-43 Study of a High-order Filter Based on Hybrid SETMOS N/A

Li Cai, Qiang Kang, Dang yuan Shi ( Air Force Engineering University of CPLA)

P2-44 Analytic Models for Electric Potential and Subthreshold Swing of the Dual-Material Double-Gate MOSFET 935

Ping Xiang, Zhihao Ding, Guangxi Hu, Hui Chol Ri, Ran Liu, Lingli Wang (Fudan University), Xing Zhou (Nanyang Technological University, Singapore)

P2-45 Three-Dimensional On-Chip Inductor Design Based on Through-Silicon Vias 939

Feng Liang, Si-Qi Zhao (University of Electronic Science and Technology of China), Aobo Chen (University of Electronic Science and Technology of China), Gaofeng Wang (Wuhan University)

P2-46 Analytical Model of the Coupling Capacitance between Cylindrical Through

XLI

Silicon Via and Horizontal Interconnect in 3D IC 942 Wenjian Yu, Siyu Yang, Qingqing Zhang (Tsinghua University)

P2-47 TSVs-aware Floorplanning for 3D Integrated Circuit 946

Jieliang Lu, Qin Wang, Jing Xie, Zhigang Mao (School of Microelectronics, Shanghai Jiaotong University, Shanghai 200240, China)

P2-48 The Annealing Effect of Chemical Vapor Deposited Graphene 950

Y.L. Shen, P. Zhou, L.H. Wang, Q.Q. Sun, Q.Q. Tao, P.F. Wang, S.J. Ding, D.W. Zhang (ASIC & System State Key Lab, School of Microelectronics, Fudan University)

P2-49 Barrier and low k Polish with a Novel Alkaline Barrier slurry combining with FA/O chelating agent 954

Jing-Bo Xu, Feng-Hui, Wen-Zhong Xu, Xu-Wang, Peng-Fei Nan (Fudan University), Yu-Ling Liu (Hebei University of Technology), Xin-Ping Qu (Fudan University)

P2-50 A New Fast Median Filtering Algorithm Based on FPGA 958

Leiou Wang (Institute of Acoustics, Chinese Academy of Sciences)

P2-51 A Power-Constrained Contrast Enhancement Algorithm for AMOLED Display Using Histogram Segmentation 962

Wenhua Qiang ,Qi Zhang, Wei Miao, Guohong Li, Hui Wang, Songlin Feng (Shanghai Advanced Research Institute, Chinese Academy of Sciences)