IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012 3795

Average Inductor Current Sensor for DigitallyControlled Switched-Mode Power Supplies

Miguel Rodrıguez, Student Member, IEEE, Victor Manuel Lopez, Student Member, IEEE,Francisco J. Azcondo, Senior Member, IEEE, Javier Sebastian, Senior Member, IEEE,

and Dragan Maksimovic, Senior Member, IEEE

Abstract—Current-mode control in digitally controlledswitched-mode power supplies typically requires analog-to-digital(A/D) conversion of at least two signals, voltage, and current.The complexity of voltage A/D converters can be reduced usingwindow A/D techniques. In conventional current A/D conversion,however, relatively high resolution is required over a widerange of signals, which results in increased complexity, powerconsumption, and cost of the controller. This paper proposes avery simple feedback sensor capable of high-resolution averageinductor current sensing using two analog comparators and ananalog low-pass filter. The approach requires very few externalcomponents and employs minimal digital hardware resources. Adynamic model and performance of the average inductor currentsensor are experimentally verified on a 12-V input, 19-V output,50-W boost converter prototype. The applicability of the proposedsensor is demonstrated in a digitally controlled 400-W, 400-Voutput Boost power factor preregulator.

Index Terms—Analog-digital conversion, current control, digitalcontrol, switched-mode power supplies.

I. INTRODUCTION

IN the area of digital control of high-frequency switched-mode power supplies (SMPS), numerous advances have

been made in terms of reduced controller complexity or im-proved performance, together with enhanced programmabilityand flexibility features. Practical digital voltage-mode control,requiring relatively small hardware resources, has been demon-strated in a number of applications [1]. Techniques such aswindow-flash analog-to-digital (A/D) conversion have been ap-plied to reduce the controller complexity [2]. Digital current-mode control, however, requires two A/D conversions, as shown

Manuscript received September 19, 2011; revised December 1, 2011 andJanuary 5, 2012; accepted January 6, 2012. Date of current version April 20,2012. This work was supported by the Spanish Ministry of Science and Edu-cation under Project Consolider RUE CSD2009-00046, FEDER Founds andProjects MICINN10-DPI2010-21110-C02-01 and CICYT-TEC2011-23612.Recommended for publication by Associate Editor J. A. Pomilio.

M. Rodrıguez and D. Maksimovic are with the Colorado Power Elec-tronics Center, Department of Electrical, Computer and Energy Engi-neering, University of Colorado, Boulder, CO 80309-425 USA (e-mail:miguel.rodriguez@colorado.edu; maksimov@colorado.edu).

V. M. Lopez and F. J. Azcondo are with the Department of Electronics Tech-nology, Systems and Automation Engineering, University of Cantabria, 39005Santander, Spain (e-mail: lopezvm@unican.es; azcondof@unican.es).

J. Sebastian is with the Power Supply Systems Group, Department of Elec-trical and Electronic Engineering, University of Oviedo, 33204 Gijon, Spain(e-mail: sebas@uniovi.es).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2012.2183893

Fig. 1. Digitally controlled boost converter with current-mode control.

in the boost converter example of Fig. 1. Furthermore, relativelyhigh-resolution current A/D conversion is required over a widerange of sensed currents, which increases complexity, powerconsumption, and cost of the controller implementation. Thisproblem severely affects widespread applications such as powerfactor correction (PFC) rectifiers, where an additional A/D con-verter is required for input voltage sensing [3].

Several alternatives to address these issues have been pro-posed: for instance, specific A/D structures for current sensingare used in [4] to implement average current mode control. Theuse of an external comparator and a digital-to-analog (D/A)converter that can easily be implemented in a digital system hasrecently been proposed: the authors in [5] use such a scheme,embedded in a feedback loop, to estimate the instantaneous in-ductance current, while the authors in [6] propose a simplersystem suitable to implement peak current mode control. Cur-rent estimation techniques based on voltage measurements havealso been investigated [7], [8], especially in the context of multi-phase converter current equalization [9]. Numerous approachesto eliminate the need for some of the required A/D have alsobeen proposed in PFC applications [10]–[15].

This paper proposes a simple and inexpensive high-resolutionaverage inductor current sensor for digitally controlled SMPS. Itis inspired by [5], and by the A/D concepts proposed in [16] and[17], where the output voltage ripple was used to indirectly mea-sure the output voltage using a single analog comparator. Theproposed sensor takes advantage of the inductor current wave-form to measure its average value using very few external com-ponents: two comparators and a simple analog low-pass filter,

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3796 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012

Fig. 2. Proposed current sensor.

in addition to a sense resistor and any conditioning circuitrythat would be required in conventional analog current-modecontrol implementations. It can be easily implemented in digitallogic [field-programmable gate array (FPGA) or custom chip]using few hardware resources, and it provides accurate sensingof the average inductor current in both continuous conductionmode (CCM) and discontinuous conduction mode (DCM).Therefore, the proposed approach can be applied to reduce thenumber of components, size, and cost of digitally controlledpower supplies with FPGA or custom-chip-based controllers.

This paper is organized as follows. Operation of the sensoris described in Section II. A dynamic model is derived in Sec-tion III. Section IV presents results of simulation of the proposedsensor when the converter operates in open- and closed-loopconditions. Section V shows open-loop experimental resultsobtained with a 12-V input, 19-V output, 50-W dc–dc boostconverter, as well as closed-loop operation of a 400-W, 400-Voutput boost power factor preregulator (PFP). Finally, conclu-sions are stated in Section VI.

II. OPERATION OF THE AVERAGE INDUCTOR CURRENT SENSOR

Fig. 2 shows the proposed sensor architecture. The voltagethat represents the instantaneous inductor current, v+ = RsiL ,is compared with the signal v− by the comparator Cmain andwith 0 V by the comparator Cdcm . Note that v− is the result of aD/A conversion of isensed [n], which is the digital output of thecurrent sensor. The output signal of Cmain is a pulse of durationtp , and has a period equal to the converter switching period, Tsw .Therefore, its duty cycle dp can be defined as dp = tp/Tsw . Thefeedback operation of the sensor forces dp to equal dref ; if drefis adequately chosen (for instance, if the converter operates inCCM then dref = 0.5, as indicated in Fig. 2), then isensed [n]is a scaled version of the average inductor current. The lowercomparator Cdcm detects RsiL = 0, providing the informationto set dref to the appropriate value when the converter operatesin DCM.

Fig. 3 shows the main operating waveforms at the inputs ofthe comparator Cmain . From the latter figure and using sim-ple geometrical considerations, the following equation can beobtained:

dp =tp

Tsw= dref + gcomp (〈v+ 〉 − v−) (1)

Fig. 3. Operating waveforms of the proposed current sensor.

dp being the duty cycle of the pulse obtained at the output of thecomparator Cmain , gcomp the equivalent gain of the comparator,and dref a constant value that depends on the conduction modeof the inductor. Note from (1) that dref equals the value of dp

when 〈v+ 〉 = v−: this fact will be used to deduce dref in SectionsII-A and II-B. The notation 〈•〉 indicates the averaging operationover one switching cycle. gcomp can be easily deduced takinginto account that the operation of the comparator is similar tothat of a conventional pulse-width modulator

gcomp ≈ Gcomp =1

V+ ,peak−to−peak(2)

with Gcomp being the value of gcomp when the inherent one-cycle delay of the comparator operation is neglected, andV+ ,peak-to−peak the amplitude of the triangular waveform in-put (as shown in Fig. 3), which in turn depends on the inductorcurrent ripple. The pulse-width measurement block turns theoutput pulse duty cycle dp into the digital signal dp [n]. Afterthat, the quantity dref is subtracted from dp [n], thus generat-ing an error signal de [n] which is the input to the sensor loopcompensator C (z). The output of the compensator isensed [n] isturned back to the analog domain by the D/A converter formedby a second-order Σ − Δ modulator and a simple, first-orderlow-pass filter. The Σ − Δ modulator, driven by the FPGAhigh-frequency clock, generates a bit pattern that contains asignificant amount of high-frequency noise but whose average

RODRIGUEZ et al.: AVERAGE INDUCTOR CURRENT SENSOR FOR DIGITALLY CONTROLLED SWITCHED-MODE POWER SUPPLIES 3797

Fig. 4. Block diagram of the system.

value equals its input signal [18]. The pattern is directly outputby the FPGA, a logic 1, thus, corresponding to the FPGA supplyvoltage and a logic 0 corresponding to 0 V, and filtered using alow-passRC network. The filter eliminates the high-frequencynoise and recovers the average current information. Therefore,the voltage at the negative input of Cmain is an scaled analogversion of isensed [n] and the modulator-filter set acts as a D/Aconverter.

Taking into account (1) and Fig. 2, the block diagram shownin Fig. 4 can be obtained, where gD/A is the transfer functionof the D/A conversion stage. From this diagram, the transferfunction between isensed and 〈iL 〉 is

isensed

〈iL 〉= Rs

Tsensor

1 + TsensorgD/A(3)

Tsensor being defined as

Tsensor = gcompC (z) . (4)

If the loop gain TsensorgD/A fulfills∥∥TsensorgD/A

∥∥ � 1, then

(3) becomes

isensed =Rs

gD/A〈iL 〉 . (5)

Neglecting delays, gD/A can be approximated by GD/A , andthus, (5) can be written as follows:

isensed ≈ Rs

GD/A〈iL 〉 . (6)

Therefore, the internal signal isensed is a digital representationof the average inductor current. The following sections estab-lish the appropriate values for the reference pulse width drefto ensure that the average inductor current can be measuredaccurately in both CCM and DCM.

A. Continuous Conduction Mode Operation

The waveforms in Fig. 3 correspond to CCM operation. Sim-ple geometrical considerations imply that dref = 0.5, i.e., when〈v+ 〉 = v− the width of the output pulse of the main comparatorequals 0.5. Thereby, in CCM operation (1) can be expressed asfollows:

dp =tp

Tsw= 0.5 + gcomp (〈v+ 〉 − v−) (7)

and a pulse width equal to 0.5 has to be used as the reference inthe sensor feedback loop to achieve the desired operation.

Fig. 5. Operating waveforms of the proposed current sensor in DCM.

Fig. 6. Dynamic model of the proposed sensor.

B. Discontinuous Conduction Mode Operation

Fig. 5 shows the operating waveforms when the inductor isoperating in DCM. Once again, geometrical considerations onFig. 5 lead to the following expression for dref :

dref = (D + Δ) ·(

1 − D + Δ2

)

. (8)

Equation (8) can easily be extended to CCM operation by sub-stituting Δ = 1 − D. Measurement of the quantity D + Δ re-quires detection of the zero-crossing instant of the inductorcurrent, which is the function of the DCM comparator Cdcmshown in Fig. 2.

This analysis demonstrates that an adjustment of the refer-ence signal of the sensor feedback loop allows an appropriatemeasurement of the average inductor current regardless of theconduction mode.

III. DYNAMIC MODEL

As the proposed sensor operates in closed loop, a dynamicanalysis is required to ensure its stability and dynamic perfor-mance during transients. Fig. 6 shows a dynamic model of theproposed sensor, which can be obtained from Fig. 4. The per-turbed variables are indicated with hats. The dynamic analysisperformed in this section is valid only for CCM operation, asadditional effects caused by the variation of dref that takes placein DCM operation have been neglected to simplify the analysis.However, the same methodology can be applied to DCM opera-tion in a straightforward manner. Note that the sampling periodof the Z-domain transfer functions is equal to the switchingperiod.

The complete transfer function for the comparator stage canbe expressed as follows:

gcomp (z) = Gcompz−1 (9)

3798 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012

with Gcomp being the value used in Section II for gcomp whenthe delay was neglected. As Gcomp depends on the current slope,its value changes with the converter topology. For instance, inthe case of the boost converter, (9) becomes

gcomp (z) =L

RsDTswVinz−1 (10)

D being the steady-state duty cycle, Vin the converter inputvoltage, L the inductance value, and Rs the sensor gain (in voltsper ampere). In the case of the buck converter, (9) becomes

gcomp (z) =L

Rs (1 − D) TswVoutz−1 (11)

Vout being the output voltage. Note that in both cases Gcompis expressed in V −1 , as expected from (2). In general the com-parator gain can be expressed as follows:

gcomp (z) =1

RsΔiLz−1 . (12)

As the Σ − Δ modulator inside the D/A operates at a muchhigher frequency than the rest of the loop, the dynamic behaviorof the low-pass filter can be neglected. Thereby, a simple zero-order hold (ZOH) model with gain can be used for the D/A

gD/A (z) = GD/Az−1 . (13)

The constant GD/A depends on the D/A implementation, i.e.,on the amplitude of the digital signal at the output of the Σ − Δmodulator.

The simplest C (z) that guarantees zero steady-state error isan integrator

C(z) =K

1 − z−1 . (14)

Substituting (10), (13), and (14) into (3)

Hsensor (z) =isensed

〈iL 〉=

RszGcompK(

z2 − z + GcompGD/AK) . (15)

The closed-loop poles of (15) can be used to derive stabilityconditions and to analyze the theoretical dynamic performanceof the proposed sensor. For instance, in the case of the boostconverter, stability is guaranteed if

K < Klimit,boost =1

GcompGD/A=

RsDTswVin

LGD/A(16)

while in the case of the buck converter the maximum K valueis

K < Klimit,buck =1

GcompGD/A=

Rs (1 − D) TswVout

LGD/A.

(17)Once again, in general the stability condition can be expressedas

K < Klimit =RsΔiLGD/A

. (18)

Equation (18) relates the dynamic performance of the sensorwith the design of the power stage; the inductor current rippleis the only power stage design parameter that determines theachievable bandwidth of the proposed sensor. Therefore, for a

Fig. 7. Bode diagram of the most representative transfer functions in the buckconverter design: GiL ,d and Hsensor are shown, the latter for different valuesof K .

certain inductor current ripple, the dynamic performance achiev-able is independent of the switching frequency, duty cycle, orinput or output voltage.

A. Design Example A: Buck Converter

In this section, the proposed current sensor is designed tomeasure the inductor current of a buck converter with the fol-lowing parameters: Vin = 12 V, Vout = 3.3 V, fsw = 250 kHz,L = 5.6 μH, C = 15 μF. The rated load is Rload = 0.33 Ω. Therest of the parameters are GD/A = 3.3 V/A and Rs = 0.2 Ω. Itwas assumed that the final goal was to design an inner currentloop: to do so, the loop gain, comprised as usual by the powerstage plant and the transfer function of the sensor, was analyzed.

The small-signal transfer function from the duty cycle tothe inductance current, GiL,d , and the transfer function of thesensor, Hsensor , given by (15), are plotted in Fig. 7. It can be ap-preciated that the cutoff frequency of Hsensor is beyond 10 kHz,and therefore, a relatively high bandwidth can be achieved inthe current loop. However, compared to a conventional analogaverage-current control design (in which Hsensor can be con-sidered constant), it can be seen that the proposed sensor addshigh frequency poles to the loop gain. The additional phaselag, which should be taken into account in the compensator de-sign, effectively reduces the achievable bandwidth compared totraditional analog average current-mode control.

B. Design Example B: Boost Converter

The proposed current sensor was designed to measure the in-put current in a dc–dc boost converter with the following param-eters: Vin = 12 V, Vout = 19 V, fsw = 100 kHz, L = 35 μH,C = 60 μF. The rated load was Rload = 8 Ω. The rest of theparameters were GD/A = 3.3 and Rs = 0.605 Ω. The small-signal transfer function from the duty cycle to the inductancecurrent GiL,d and the transfer function of the sensor given by

RODRIGUEZ et al.: AVERAGE INDUCTOR CURRENT SENSOR FOR DIGITALLY CONTROLLED SWITCHED-MODE POWER SUPPLIES 3799

Fig. 8. Bode diagram of the most representative transfer functions in the boostconverter design: GiL ,d and Hsensor are shown, the latter for different valuesof K .

(15) are plotted in Fig. 8. Once again, the sensor achieves a rel-atively high bandwidth but, as in the case of the buck converter,the additional high-frequency poles add extra phase lag.

Again, it should be noted that compared to a traditional analogaverage current-mode control [19], the sensor modifies the open-loop transfer function of the system. The compensator shouldbe designed including the effects of Hsensor , which implies thefollowing.

1) The bandwidth of the control loop will be limited atleast by the bandwidth of the sensor (BWclosed−loop <BWsensor).

2) For a given desired crossover frequency, additional phaselead needs to be provided to compensate for the phase lagintroduced by Hsensor .

The simulation and experimental results in the following sec-tions show that the proposed sensor is able to provide preciseand accurate measurements of the average inductor current andthat it can be successfully used in dc–dc converters as well as inac–dc PFC applications.

IV. SIMULATION RESULTS

A. DC–DC Boost Converter

A dc–dc boost converter operating in open-loop and the pro-posed sensor were simulated in Simulink. The power stage reac-tive components were: L = 35 μH, C = 60 μF and the switch-ing frequency was fsw = 100 kHz. The input and output volt-ages were Vin = 12 V and Vout = 19 V, respectively, while therated load was R = 8 Ω. Table I shows the remaining design pa-rameters. The D/A was simulated using a second-order Σ − Δoperating at 100 MHz, along with a first-order low-pass filterwith a cutoff frequency close to 200 kHz.

The current sensor compensator C (z) was chosen as in (14),and after that Sisotool was used to find a value of K that yieldedan appropriate phase margin and closed-loop bandwidth. A de-

TABLE IMAIN PARAMETERS USED IN THE SIMULATION OF THE DC–DC BOOST

sign with K = 0.1 was chosen, yielding a phase margin of 52◦

and bandwidth close to 10 kHz.Fig. 9(a) and (b) shows the sensor in steady state. Fig. 9(a)

shows the estimated digital current isensed once scaled, alongwith the actual inductor current iL and the average inductor cur-rent 〈iL 〉 obtained by low-pass filtering iL using a second-orderfilter. It can be seen that the scaled version of isensed preciselymatches the average inductor current. Fig. 9(b) shows the samewaveforms depicted in Fig. 9(a) but when the inductor operatesin DCM, it can be seen that the sensor still provides the ac-tual current, therefore, confirming the validity of the approachdescribed in Section II-B. As already mentioned, the requiredvalue of dref given by (8) was obtained by measuring the induc-tor conduction period: according to Fig. 5, the duration of suchinterval directly provides the quantity (D + Δ) Tsw .

Fig. 9(c) and (d) shows the sensor response under a load step.In spite of the noticeably underdamped response, the sensorkeeps track of the average current. Fig. 9(d) shows the responsein detail, where it can be observed the delay that takes place inthe current measurement process.

B. AC–DC Boost Power Factor Preregulator

A boost PFP and the current sensor were also simulated usingModelSim. Fig. 10 shows an schematic diagram of the system.Due to the discrete-time nature of ModelSim simulations, ap-propriate models were written in VHDL for the sensor low-passfilter and the power stage, following the approach describedin [20]. The power stage reactive components were: L = 3 mH,C = 220 μF and the switching frequency was fsw = 100 kHz.The input voltage was vac = 220 Vrms , f = 50 Hz, and the out-put voltage was around Vout = 400 V.

As the goal of the simulation was to show the use of thesensor in a conventional PFC application, only the inductorcurrent loop was closed, whereas the output voltage was leftunregulated. Therefore, the input voltage was scaled throughGin to obtain the inductor current reference, thus establishing thepower delivered by the PFP. The load was R = 450 Ω. Table IIshows the remaining design parameters.

Note that in this application the selection of the sensor gainhas to take into account the varying input voltage; theoreti-cally, at the input voltage zero crossings, the inductor currentripple would be zero, causing instability in the current sensoraccording to (18). However, in practice the maximum duty cy-cle is usually limited (and the input voltage never reaches zerodue to the presence of additional input capacitance), thus estab-lishing a lower limit for the minimum inductor current ripple.Fig. 11 shows the sensor transfer function for the minimumand maximum calculated inductor current ripple (minimum and

3800 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012

Fig. 9. Simulation results: (a) CCM steady-state operation; (b) DCM steady-state operation; (c) 100 % to 50 % load step; and (d) detailed view of the waveformin Fig. 9(c).

Fig. 10. Schematic diagram of the ac–dc boost PFP.

TABLE IIMAIN PARAMETERS USED IN THE SIMULATION OF THE AC–DC BOOST PFP

maximum values of Klim , respectively). Thus, a conservativedesign with K = 0.025 was selected, providing an useful band-width of the sensor of around 1 kHz. Therefore, to ensure an

Fig. 11. Transfer function of the current sensor for the minimum and maxi-mum values of Klim .

appropriate operation of the system, the bandwidth of the innercurrent-loop controller was selected to be around 1 kHz. Thecurrent loop compensator was designed following [21]. A dif-ferent approach based on adjusting K as a function of the inputvoltage can easily be implemented in a digital system, and mightbe able to maximize the sensor bandwidth. However, this paper

RODRIGUEZ et al.: AVERAGE INDUCTOR CURRENT SENSOR FOR DIGITALLY CONTROLLED SWITCHED-MODE POWER SUPPLIES 3801

Fig. 12. Boost PFP simulation results obtained using ModelSim: (a) input voltage, Vin ; (b) input (inductor) current, iL ; (c) sensed digital current, isensed [n];and (d) negative input of the main comparator, v−.

focused on the simplest possible implementation, and therefore,a fixed value of K was used.

Once again, the D/A was simulated using a second-orderΣ − Δ operating at 100 MHz, along with a first-order low-passfilter with a cutoff frequency of 200 kHz.

Fig. 12 shows the most representative operating waveforms.Fig. 12(a) and (b) shows the input voltage Vin and inductorcurrent iL , respectively. It can be seen that the sensor enablesPFC, achieving an almost sinusoidal input current. A slightdistortion is observed after the zero crossing of the input voltage.This distortion arises due to the limit established in the dutycycle, which causes the current compensator to saturate nearthe zero crossings. Fig. 12(c) shows the digital version of theaverage inductor current isensed . The negative input of the maincomparator, v−, i.e., the analog scaled version of the sensedcurrent, is shown in Fig. 12(d).

V. EXPERIMENTAL RESULTS

In this section, two scenarios that mimic Section IV are de-scribed: Section V-C shows a dc–dc boost converter and thesensor operating in open loop, whereas Section V-D shows anac–dc boost PFP. Section V-A describes the current sense cir-cuitry, common to both scenarios.

A. Current Sense Circuitry

Fig. 13 shows a simplified diagram of the inductor currentsense circuitry, which was built in a separate board and attachedto each corresponding power stage. A shunt resistor in serieswith the inductance was used as a current to voltage converter. Adual OPA2727 was then used to amplify the signal in two stages.After that, two low cost, precision comparators (TL3016 fromTexas Instruments) were required to implement the comparatorsCmain and Cdcm in Fig. 2: Cmain compares RsiL with v−, whileCdcm detects the zero crossing of the inductor current to allowDCM operation. Finally, the board included the first-order low-pass filter of the D/A converter. A 2 kΩ-220 pFRC filter wasused, yielding around 750-kHz cutoff frequency, low enoughto eliminate the high-frequency noise produced by the Σ − Δmodulator. Note that these values can be adjusted depending onthe FPGA clock frequency, the allowable ripple at the negativeinput of Cmain (which in turn depends on the current ripple),and the dynamic requirements of the current sensor.

B. Pulse Width Measurement and Reference Generator

Implementations of the pulse-width measurement block andthe reference generator are shown in Fig. 14(a) and (b), respec-tively. The pulse-width measurement block is a simple counterthat uses a high-frequency clock clk for improved resolution. It

3802 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012

Fig. 13. Simplified diagram of the current sense circuitry.

Fig. 14. (a) Implementation of the pulse width measurement system and (b)implementation of the reference generator.

is enabled by the input pulse and reset in every switching pe-riod. The reference generator is also based on a simple counterenabled at the beginning of the switching period and stopped bythe output of Cdcm . This counter is also reset in every switchingperiod. Note that Fig. 2 includes a multiplexer to select betweena fixed dref equal to 0.5 (for CCM operation) and the referencegenerator output (for DCM operation). The actual implementa-tion shown in 14(b) is slightly simpler, taking advantage of thefact that (8) is valid for both CCM and DCM operation.

Given that both counters use the internal high-frequency clockof the digital system, the time resolution of both blocks isTclk = 1/fclk , which can be expressed in terms of the equivalentnumber of bits, nb,eq , of dp and dref as

nb,eq = log2fclk

fsw. (19)

As an example, in the experiments presented in this section theclock frequency was 100 MHz, whereas the switching frequencywas set to a value slightly below 100 kHz, thus allowing exactly10 bits of resolution in both dp and dref . Note that the numberof bits of dp and dref determines the effective resolution of thesensor, i.e., the number of bits in isensed [n].

TABLE IIILOGIC RESOURCES USED BY THE REFERENCE GENERATOR AND THE PULSE

WIDTH MEASUREMENT BLOCKS

Fig. 15. Experimental dc–dc boost converter setup.

Table III shows a summary of the amount of logic resourcesrequired by each block. The results have been obtained usingQuartus II software, v. 10, and a Cyclone II EP2C35F672 FPGA.For the sake of comparison, the overall logic element usage rep-resents around 0.2 % of the available logic in the aforementionedFPGA.

C. DC–DC Boost Converter

A boost converter with the same parameters described inSection IV-A was built in the laboratory. This 12-V input, 19-Voutput, 50-W converter, designed to supply laptop computersfrom a 12-V battery, was used to test the proposed current sen-sor. Fig. 15 shows the experimental setup, where the additionalhardware board with the analog current sense circuitry is high-lighted. A 5-mΩ sense resistor was used, and a gain of 11 wasset in each of the amplification stages, thus providing an overallsense gain Rs equal to 0.605 V/A. The MOSFET and diode usedto build the power stage were a STP60N from STMicroelectron-ics and a 8TQ100 from Vishay Semiconductor, respectively.A commercial off-the-shelf inductor from Coilcraft was alsoused.

An Altera DE2 development board that includes a Cyclone IIFPGA was used to implement all the digital hardware. All therequired blocks were programmed in VHDL, and especial carewas taken with the synchronization of the different parts ofthe system to avoid additional delays in the sensor loop, whichmight compromise the dynamic performance of the system. Thevalue of K was set close to 0.1, to match as much as possiblethe simulation scenario described in Section IV. The remainingrequired hardware, as the digital pulse-width modulator usedto control the power MOSFET, and/or other auxiliary blocks,were also implemented in the FPGA. Fig. 16 shows steady-state measurements that were obtained to test the accuracy of

RODRIGUEZ et al.: AVERAGE INDUCTOR CURRENT SENSOR FOR DIGITALLY CONTROLLED SWITCHED-MODE POWER SUPPLIES 3803

Fig. 16. Steady-state measured average input current, 〈iL 〉, and v− (the analogscaled version of isensed ).

Fig. 17. Experimental results: (a) steady-state operation (14-Ω load); and(b) steady-state operation (10-Ω load).

the sensor. The average input current was measured using aprecision multimeter, along with an HP current shunt, model34330A. The internal resolution of the sensor, i.e., the resolutionchosen for isensed , was set to 10 bits. The worst-case errormeasured was less than 2 %. Thus, Fig. 16 demonstrates that thesensor is capable of accurately measuring the average inductorcurrent.

Fig. 17(a) and (b) shows both inputs of the comparator, signalsv+ = RsiL and v−, the analog scaled version of isensed , whenthe converter is in steady state and for two different load values.It can be seen that the average value of both signals is the same,as was predicted by (6), and that the sensor performs as expectedin steady state.

Fig. 18. Experimental results in DCM operation: (a) dref is kept constant andequal to 0.5; (b) dref is modified according to (8).

If the sensor is prepared to operate only in CCM then an errorarises when the converter enters in DCM. The boost converterused in this section, operating at 100 kHz, enters in DCM atvery low inductor current. Therefore, the error in the currentmeasurement is small compared with the rated current. In orderto better observe the error caused by the DCM operation, theswitching frequency was decreased to 50 kHz, thus allowingDCM operation to occur with relatively high inductor currentand increasing the relative error of the current measurement.

Fig. 18(a) shows the main waveforms when the converteroperates in DCM and dref = 0.5, i.e., only CCM operation of thesensor was allowed. The actual average input current was closeto 1.48 A, while the current measured by the sensor was 1.1 A,i.e., the relative error was close to 25 %. Fig. 18(b) shows theoperation of the system when dref was appropriately modifiedaccording to (8). The actual input current was then 1.49 A, andthe measured current was 1.514 A, i.e., the error dropped to1.6 %, a value consistent with the results shown in Fig. 16.

Finally, several load steps were carried out to test the dy-namic performance of the sensor. Fig. 19 shows the positive in-put of the comparator, v+ = iLRs , and the scaled version of thesensed current, v− = isensedGD/A , under 8–14 Ω and 14–8 Ωload steps, respectively. It can be seen that the sensor tracks theaverage inductor current, as expected. Furthermore, the resultsare in good agreement with those obtained in the simulationsshown in Section IV. Slightly higher damping and smaller set-tling time can be appreciated, probably caused by nonidealitiesthat were not appropriately accounted for in the simulations,e.g., the actual MOSFET and inductor parasitic resistances,

3804 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012

Fig. 19. iL and v− under various load steps: (a) 8–14 Ω; (b) 14–8 Ω.

Fig. 20. Boost PFP prototype (130 mm × 100 mm).

and also by a slightly smaller inductance value that was finallyused.

D. AC–DC Boost Power Factor Preregulator

A boost PFP with the same parameters described inSection IV-B, which is shown in Fig. 20, was built in the lab-oratory. The current sensor circuitry was the same described inSection V-A. In this case a 0.5-Ω sense resistor was used andthe overall gain of the amplification stage was set to 2, thus pro-viding an overall sense gain Rs equal to 1 V/A. The MOSFETand diode used to build the power stage were a IRFP27N60Kfrom Vishay and a RHRP860 from Fairchild Semiconductor,respectively. A custom inductor of the required value was builtusing a soft-saturation core, Kool-μ 77071.

It is interesting to note that, in an effort to minimize theamount of hardware required, the input voltage is acquired using

Fig. 21. Experimental results obtained with the boost PFP.

Fig. 22. Experimental results: (a) sensed input voltage and (b) sensed inductorcurrent.

a sigma-delta A/D converter, as described in [22]. This approachrequires only an additional comparator and a low-pass filter, andcan be easily extended to measure the output voltage. Therefore,the PFP presented here does not require conventional A/D chips;furthermore, it uses very few external components in addition tothe power stage, as the complete control and a major part of the

RODRIGUEZ et al.: AVERAGE INDUCTOR CURRENT SENSOR FOR DIGITALLY CONTROLLED SWITCHED-MODE POWER SUPPLIES 3805

sensing are carried out by digital means. The same Altera DE2development board was used to implement the digital hardware,including among other things the digital current control loopfor the converter, the pulse-width modulator and the Σ − Δmodulator used to measure the input voltage.

Fig. 21 shows an example of the results obtained for an outputpower of 240 W. The analog scaled version of isensed , 〈v−〉, isshown along with the line current and voltage. It can be seenthat sinusoidal input current was achieved, and that the resultsclosely matched the simulations presented in Section IV-B. Themeasured power factor was 0.999.

Fig. 22(a) shows the sampled input voltage, whereasFig. 22(b) shows the digital current. It can be seen that the inputvoltage was correctly sampled through the Σ − Δ A/D, and thatthe current sensor provided the correct sinusoidal waveform.

VI. CONCLUSION

An average inductor current sensor for digitally controlledSMPS has been presented in this paper. The proposed sensorallows the average inductor current to be precisely measuredwithout an expensive A/D converter. As it operates in a closed-loop manner, its dynamic performance and stability conditionswere analyzed in this paper, showing that it was capable ofreaching relatively high bandwidths. Its influence over the loopgain of the converter, by means of additional high-frequencypoles that add additional phase lag compared to conventionalanalog designs, was also highlighted.

Thorough simulations were presented to demonstrate the fea-sibility of the sensor concept, and experimental results wereobtained by means of a dc–dc boost converter prototype oper-ating in open loop, as well as using a boost PFP in closed-loopoperation.

The proposed sensor can help to simplify the hardware im-plementation of digitally controlled current-mode SMPS, and ithas been demonstrated in this paper that it is especially suitablefor digitally controlled PFC applications, as it enables a verysimple and hardware-effective realization.

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[1] D. Maksimovic, R. Zane, and R. Erickson, “Impact of digital control inpower electronics,” in Proc. 16th Power Semicond. Devices ICs, May2004, pp. 13–22, 2012.

[2] A. Peterchev, X. Jinwen, and S. Sanders, “Architecture and IC implemen-tation of a digital VRM controller,” IEEE Trans. Power Electron., vol. 18,no. 1, part 2, pp. 356–364, Jan. 2003.

[3] A. de Castro, P. Zumel, O. Garcıa, T. Riesgo, and J. Uceda, “Concurrentand simple digital controller of an AC/DC converter with power factorcorrection based on an FPGA,” IEEE Trans. Power Electron., vol. 18, no.1, pp. 334–343, Jan. 2003.

[4] H. Peng and D. Maksimovic, “Digital current-mode controller for DC-DCconverters,” in Proc. IEEE Appl. Power Electron. Conf. Expo., Mar. 2005,vol. 2, pp. 899–905.

[5] W. Stefanutti, E. Della Monica, E. Tedeschi, P. Mattavelli, and S. Saggini,“Reduction of quantization effects in digitally controlled dc-dc convertersusing inductor current estimation,” in Proc. IEEE Power Electron. Spec.Conf., Jun. 2006, pp. 1–7.

[6] O. Trescases, Z. Lukic, W. Tung, and A. Prodic, “A low-power mixed-signal current-mode DC-DC converter using a one-bit Δ − Σ DAC,” inProc. IEEE Appl. Power Electron. Conf. Expo., 2006, p. 5.

[7] P. Midya, P. Klein, and M. F. Greuel, “Sensorless current mode control-an observer-based technique for DC-DC converters,” IEEE Trans. PowerElectron., vol. 16, no. 4, pp. 522–526, Jul. 2001.

[8] Y. Qiu, X. Chen, and H. Liu, “Digital average current digital averagecurrent-mode control using current estimation and capacitor charge bal-ance principle for DC-DC converters operating in DCM,” IEEE Trans.Power Electron., vol. 25, no. 6, pp. 1537–1545, Jun. 2010.

[9] Z. Lukic, Z. Zhenyu, S. M. Ahsanuzzaman, and A. Prodic, “Self-tuningdigital current estimator for low-power switching converters,” in Proc.Appl. Power Electron. Conf., Feb. 2008, pp. 529–534.

[10] W. Stefanutti, P. Mattavelli, G. Spiazzi, and P. Tenti, “Digital controlof single-phase power factor preregulators based on current and voltagesensing at switch terminals,” IEEE Trans. Power Electron., vol. 21, no. 5,pp. 1356–1363, Sep. 2006.

[11] J. Sun and M. Chen, “Nonlinear average current control using partialcurrent measurement,” IEEE Trans. Power Electron., vol. 23, no. 4, pp.1641–1648, Jul. 2008.

[12] B. Mather and D. Maksimovic, “A simple digital power-factor correctionrectifier controller,” IEEE Trans. Power Electron., vol. 26, no. 1, pp. 9–19,Jan. 2011.

[13] F. J. Azcondo, A. de Castro, V. Lopez, and O. Garcıa, “Power factorcorrection without current sensor based on digital current rebuilding,”IEEE Trans. Power Electron., vol. 25, no. 6, pp. 1527–1536, Jun. 2010.

[14] H.-C. Chen, “Single-loop current sensorless control for single-phaseboost-type SMR,” IEEE Trans. Power Electron., vol. 24, no. 1, pp. 163–171, Jan. 2009.

[15] H.-C. Chen, C.-C. Lin, and J.-Y. Liao, “Modified single-loop currentsensorless control for single-phase boost-type SMR with distorted inputvoltage,” IEEE Trans. Power Electron., vol. 26, no. 5, pp. 1322–1328,May 2011.

[16] B. Mather and D. Maksimovic, “Single comparator based A/D converterfor output voltage sensing in power factor correction rectifiers,” in Proc.IEEE Energy Convers. Congr. Expo., Sep. 2009, pp. 1331–1338.

[17] K. I. Hwu and Y. T. Yau, “Applying a counter-based PFM control strategyto an FPGA-based SR forward converter,” in Proc. IEEE Region 10 TrendsDevelopments Converg. Technol. Conf., 2006, pp. 1–4.

[18] R. Schreier and G. Temes, Understanding Delta-Sigma Data Converters.Piscataway, NJ: IEEE Press, ch. 3, pp. 63–89.

[19] L. Dixon, “Average current mode control of switching power supplies,”Unitrode Design Seminars, no. 700, topic 5, 1990.

[20] F. J. Azcondo, A. de Castro, and C. Branas, “Course on digital electronicsoriented to describing systems in VHDL,” IEEE Trans. Ind. Electron., vol.57, no. 10, pp. 3308–3316, Oct. 2010.

[21] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics.Norwell, MA: Kluwer, 2001.

[22] V. M. Lopez, F. J. Azcondo, F. J. Dıaz, and A. de Castro, “Autotuningdigital controller for current sensorless power factor corrector stage incontinuous conduction mode,” in Proc. IEEE Workshop Control Model.Power Electron., 2010, pp. 1–8.

Miguel Rodrıguez (S’06) was born in Gijon, Spain,in 1982. He received the M.S. and Ph.D. degrees intelecommunication engineering both from the Uni-versity of Oviedo, Oviedo, Spain, in 2006 and 2011,respectively.

Since January 2011, he has been a Research Asso-ciate in the Colorado Power Electronics Center, Uni-versity of Colorado, Boulder. His research interestsinclude dc/dc conversion, digital control of switchedconverters, and power-supply systems for RFamplifiers.

3806 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012

Victor Manuel Lopez (S’10) was born inTorrelavega, Cantabria, Spain, in 1985. He receivedthe Electronics and Control Engineering degree fromthe University of Cantabria, Santander, Spain, in2009, where since then he has been working towardthe Ph.D. degree in the Department of ElectronicsTechnology, Systems and Automation Engineering.

His research interests include design, modeling,and digital control of topologies for power factor cor-rection applications.

Mr. Lopez received the IEEE/IEL ElectronicLibrary Award in 2009.

Francisco J. Azcondo (S’90–M’92–SM’00) re-ceived the Electrical Engineering degree from theUniversidad Politecnica de Madrid, Madrid, Spain, in1989, and the Ph.D. from the University of Cantabria,Santander, in 1993.

From 1990 to 1995, he was involved in the de-signing of highly stable quartz crystal oscillators.Since 1995, he has been an Associate Professor in theDepartment of Electronics Technology, Systems andAutomation Engineering, University of Cantabria.From February 2004 to August 2010, he was a Special

Member of the Department of Electrical, Computer, and Energy Engineering,University of Colorado, Boulder, and in the summer of 2006, he was a VisitingResearcher in the Department of Electrical and Computer Engineering, Univer-sity of Toronto, ON, Canada. His research interests include switch-mode powerconverters and their control for discharge lamps, electrical discharge machining,arc welding, and power factor correction applications.

Dr. Azcondo was the Chair of the IEEE Industrial Electronic Society andPower ELectronics Society Spanish Joint Chapter, from September 2008 to June2011. Since 2005, he has been an Associate Editor of the IEEE TRANSACTIONS

ON INDUSTRIAL ELECTRONICS in the field of Power Electronics.

Javier Sebastian (M’87–SM’11) was born inMadrid, Spain, in 1958. He received the M.Sc. degreefrom the Polytechnic University of Madrid, Madrid,Spain, in 1981, and the Ph.D. degree from the Uni-versity of Oviedo, Gijon, Spain, in 1985.

He was an Assistant Professor and an AssociateProfessor with both the Polytechnic University ofMadrid and the University of Oviedo. Since 1992,he has been with the University of Oviedo, where heis currently a Professor. His research interests includeswitching-mode power supplies, modeling of dc-to-

dc converters, low-output-voltage dc-to-dc converters, and high-power-factorrectifiers.

Dragan Maksimovic (M’89–SM’04) received theB.S. and M.S. degrees in electrical engineering fromthe University of Belgrade, Belgrade, Yugoslavia,in 1984 and 1986, respectively, and the Ph.D. de-gree from the California Institute of Technology,Pasadena, in 1989.

From 1989 to 1992, he was with the Universityof Belgrade. Since 1992, he has been with the De-partment of Electrical, Computer and Energy Engi-neering, University of Colorado, Boulder, where heis currently a Professor and the Director of the Col-

orado Power Electronics Center (CoPEC). His current research interests includemixed-signal integrated circuit design for control of power electronics, digitalcontrol techniques, as well as energy efficiency and renewable energy applica-tions of power electronics.

Dr. Maksimovic received the 1997 National Science Foundation CAREERAward, the IEEE Power Electronics Society Transactions Prize Paper Awardin 1997, the IEEE Power Electronics Society Prize Letter Awards in 2009 and2010, the Holland Excellence in Teaching Awards in 2004 and 2011, and theUniversity of Colorado Inventor of the Year Award in 2006.