The Design of an 8-bit CISC CPU Based on FPGA

Yunjie Zhang, Lei Bao Electronic & Information Engineering Department

Tianjin Institute of Urban Construction Tianjin, China

e-mail:zhangyunjietj@163.com

Abstractwith the development of FPGA, the design of digital electronic circuits has entered a new era, which make it possible for designers to customize their own special CPU. So it is a great significance to design an economic and applicable CPU core based on FPGA for the cost reduction and the possession of intellectual property. Based on the relevant knowledge on the principles of computer composition, the paper designed and implemented an 8-bit CISC CPU by using top-down approach, completed all of the functional modules using the hardware description language VHDL and EDA technology. It is designed, compiled and simulated under the integrated development environment of Quartus II, and after that it is downloaded to the FPGA experimental platform for units and system testing. Finally, the validity of the design was verified and the simulation result of test program for the designed CPU is presented. The experiment result shows that the functional modules are successful in performing their individual functions, and the CPU as a whole can correctly execute all of the instructions. Thereby, it proves to achieve the goal as formerly designed. The research of this paper makes contributions to the design of the more complex CPU based on FPGA and readers may refer to it according to their demands.

Keywords- CPU;CISC;FPGA ;EDA;VHDL; Electronic design automation; simulation

I. INTRODUCTION In nowadays, embedded system has been widely applied in

many kinds of electronic equipments. Meanwhile, the 8-bit CISC CPUs are widely used in embedded system. As the core of embedded system, the CPUs performance directly determines the performance of the whole system. So it is a great significance to design an 8-bit CISC CPU core for the cost reduction and the possession of intellectual property [1] [6]. With the rapid development of FPGA, it is possible to make designers customize their own special CPU. We can design CPU soft-core using hardware description language (such as VHDL), and then simulate and synthesize it using EDA tools such as Quartus II. And after that, we can download it to the FPGA and apply it to our embedded system.

Based on the relevant knowledge on the principles of the CPU composition, the paper designed an 8-bit CISC CPU by using top-down approach, completed all of the functional modules using the hardware description language VHDL and EDA technology. The functional modules include the control module, memory module, arithmetic and logic module, the general register group, the program counter, address registers, instruction register, timing components, input device, as well as output device [2][8]. It is designed, compiled and simulated under the integrated development environment of Quartus II,

and after that it is downloaded to the FPGA experimental platform for units and system testing.

The paper is organized as follows. In section II, the paper introduces the architecture of the 8-bit CISC CPU. In section III and IV, main logic components/modules of the CPU internal structure are described in detail and how the logic components can work collaboratively is thoroughly discussed. The implementation and simulation of the CPU with basic functions will be shown in Section V followed by short conclusion and future work in Section VI.

II. MAIN FUNCTIONS OF THE CPU CPU is the most important component in a computer, and

the primary functions of it are executing program code stored in the main memory and completing the tasks submitted by the user. The primary functions of the CPU are induced as follows [3]: (1) Instruction Control; (2) Operation Control; (3) Timing Control; (4) data process. All of the concrete functions are embodied in the instruction system. The instruction system of this 8-bit CPU contains 5 machine instructions, as shown in the table I.

TABLE I. INSTRUCTION SYSTEM

mnemonic symbols

operation codes

address codes

functional specification

IN 20H INPUTR0 ADD addr 40H XXH R0+[addr]R0 STA addr 60H XXH R0[addr] OUT addr 80H XXH [addr]BUS JMP addr A0H XXH addrPC

Among the instructions in the table, IN instruction is a one-word length instruction, and the rest of them are all double-word length instructions. The function of IN instruction is transferring data from input device to register R0. The function of OUT instruction is transferring the data from memory cell addressed by the lower instruction word to output device and displaying it. The function of ADD is adding the data from R0 and from memory cell addressed by the lower instruction word, and then transferring the result to R0. The function of STA instruction is transferring data from R0 to memory cell addressed by the lower instruction word. The function of JMP instruction is making program jump to an entry point of the main memory that is addressed by the lower instruction word.

978-1-4244-6252-0/11/$26.00 2011 IEEE

III. DESIGN OF THE DATA PATH

A. Structure of the data path The basic structure of the CPU generally consists of data

path and controller [1]. Data path is for processing data information, which represents the structure and layout of the CPU as a whole. The data path and instruction system provide necessary basis for controller design. Different data path structure has a direct impact on the running speed of the CPU. The structure of the data path designed in this paper is shown in Figure 1. The functional modules of it mainly include data bus(DB), arithmetic and logic unit(ALU), memory module(RAM), general register(R0), program counter(PC), address registers(AR), instruction register(IR), data buffer register(DR1,DR2), timing pulse generator, input device(SWICH), as well as output device(LED).

Figure 1. The structure of the data path

Data path of single bus is adopted in the design, therefore the data and address share the same bus [9]. In order to avoid the data conflict occurred in the bus, it is through tristate logic gate to connect to data bus for the out ports of the most modules. Data path of single bus is convenient for extension; however, both the data and the instructions are all transferring through the same bus. So the assignment of the data bus should be made in a proper way.

B. Design of the data path with VHDL and LPM The design of the data path is processed in the integration

environment of Quartus II. The ALU is designed in VHDL; however, all kinds of registers, the RAM, the PC and the tristate logic gate could be designed through calling the LPM (Library Parameterized Modules) provided by Quartus II. As for timing pulse generator, it is designed by 4 D-type Flip flops and its Pulse-width is regulated by the timing source.

Using the approach of top-down and the method of modular design, in the top schematic of system it calls and links the symbols of all kinds of functional modules through the single bus. Besides, the Corresponding control signals of the functional modules is marked in the top schematic. Consequently, the whole circuit of the CPU is accomplished. Top-level schematic of the data path is shown in figure 2:

Figure 2. Top-level schematic of the data path

IV. DESIGN OF THE CONTROLLER Controller is the command center of CPU and control all

kinds of signals used in the data path to control data transferring or data processing are sent from controller. The main function of it is generating the various operation control signals, which make the data path be established correctly and the instructions be fetched and executed cyclically [4][5]. There are two ways for controller design, which are hardwired controlling and micro program controlling. By comparing the two methods, the first is widely used. So in this paper, the controller adopts micro program controlling.

A. structure of the micro program controller Micro program controller is mainly composed with control

memory and micro address forming unit (uAR). The structure of it is shown in Figure 3. The control memory is used to store all of the micro programs that correspond to the instruction system. It could be designed through calling the LPM (Library Parameterized Modules) provided by Quartus II.

Figure 3. Structure of the micro program controller

The function of the micro address forming unit is forming the address of the next micro instruction. During forming the address, the way of forming the address is not the same when micro instructions are performed in the sequence and in the branch. Any way the next address field of the last micro instruction and the operation code of current micro instruction together determine the address of the next micro instruction. During a machine cycle, the combination of a group of micro commands which have certain function is defined a micro

instruction and the combination of a group of micro instructions is defined a segment of micro program. The function of one machine instruction is implemented by a corresponding segment of micro program.

B. Format of the micro instruction The length of the micro instruction format is 24 bits, which

is composed of operation controlling fields and address fields of the next micro instruction. The operation controlling fields are divided into a lot of little operation controlling field and each of them represents a micro command. The format of the micro instruction is shown as table II. Among the fields, 7 bits are assigned to sequential control of micro instructions and 17 bits are assigned to operation controlling fields. As for 7 bits sequential control fields, 1 bit is assigned to P field and the rest 5 bits are assigned to the address fields of the next micro instruction .

TABLE II. FORMAT OF THE MICRO INSTRUCTION

24-19 18 17 16 15 14 13 12

S3 S2 S1 S0 M Cn LOAD WE LDR0 LDDR1 LDDR2 LDIR LDAR

11 10 9 8 7 6 5 4-0 ALU-B R0-B SW-B PC-B RAM-B LDPC P1 uA4-uA0

C. Flow chat of micro programs Based on the machine instruction and micro instruction, the

flow chat of micro programs should be designed. The flow chat of micro programs is shown in Figure 4. At the same time, operating codes of program instructions are used to decide the first address of micro-program. Therefore, Reasonable arrangements of the program instructions operating code can reduce the complexity in circuit design. At last, the addresses of all the micro instructions are confirmed which have been marked in the flow chat.

00

0A

09

01

00

1D

OUT

1C STORE

18 14 0C

0A

01

00

00

00 09

08 04 INC SUB ADD IN

PCBUS,BUSAR PC+1

RAMBUS BUSIR

P1

SWDR1

DR1+DR2R0

SWR0

R0 DR2 0E

0D

SWDR1

DR1*DR2R0

R0 DR2

00

15

R0DR1

DR1+1R0

00

19

SWAR

R0 RAM

00 00

RAMBUS

SWAR

Figure 4. Flow chat of micro programs

In the flow chat of micro programs, a box represents one micro instruction. If one operate should be performed, the corresponding field would be set 1, otherwise 0. When the micro instruction is sent to data path from control memory, the

corresponding module will work correctly. The machine instruction is interpreted and executed after the IR received it. That is to say, it will execute the corresponding micro program segment. In accordance with the 3 higher bits (IR7-IR5), several branches produced. Each of the branches presents one machine instruction. Finally, all of the codes of the micro instructions are obtained.

V. SIMULATION AND IMPLEMENTATION BASED ON FPGA The 8-bit CISC CPU, which is composed of the data path

and the controller, is designed and compiled under the integrated development environment of Quartus II. After that the simulation for the process of the machine instructions is performed [10]. To meet the requirement of the simulation, a section of assembly language code should be given. The function of the code fragment mainly includes receiving an 8-bit data from input device (SWITCH), adding it with the data from a cell of the main memory, returning the result to another cell of the main memory, sending the result to output device (LED), and jump back to the beginning. The assembly language testing code is listed as follow:

IN; input a data from SWITCH ADD 10H; add the data of R0 with the data from RAM STA 11H; store the result to RAM OUT 11H; send the result to LED from RAM JMP 00H; jump back to the beginning

In accordance with the instruction format, the assembly language testing code is translated into machine language code which is written into the RAM as binary form. The machine language code corresponding with the assembly language testing code is as follows:

00100000; IN 01000000 00010000; ADD 10H 01100000 00010001; STA 11H 10000000 00010001; OUT 11H 10100000 00000000 ; JMP 00H

Besides of the schematic file, a wave file should be established which including many excitation signals. in accordance with the excitation signal, the function simulation of the CPU could be performed after the machine language code is written into the RAM. The function simulation waveforms are stated as figure 5:

Figure 5. Function simulation waveforms

In the figure 5, it indicates the execution flow of 5 machine instructions, and 2 instructions of that is explained as follows:

Machine cycle 1: the 0001141 micro instruction in the micro address of 00H is executed, and the corresponding

operations include 00AR, PC=PC+1=1. When the cycle is gone, the next micro address is 01H.

Machine cycle 2: the 00020A0 micro instruction in the micro address of 01H is executed, and the corresponding operations include 20HIR, P1=1. When the cycle is gone, the next micro address is 04H. The next micro address is not sequential because the branch entrance of micro programs is different.

After the design is complied, a netlist file would be produced. If there are no problems in the process of the function simulation, the netlist could be downloaded into the FPGA development board which is named cyclone EP1C12Q240C8. The board-level hardware test is made on the FPGA development platform. The hardware test result shows the 8-bit CISC CPU can execute the testing code segment composed of some machine instructions rapidly and accurately.

VI. CONCLUSION By using top-down approach and modular design method,

an 8-bit CISC CPU is designed and implemented based on FPGA, which has achieved the expected goals through the simulation and verification. For the designed CPU, The architecture is still nonpipelined; in addition, both the arithmetic functions and the execution speed are limited. However, this design can be read easily, updated easily and extended freely, which can be reused in many other SOC designs. In different situations, CPU core could be costumed for industrial application. The 8-bit CPU is the most important part of a SOC system which has the widespread application on many domains at present. Despite that the design of the CPU is too simple to have any immediate applications it could form the basis of a SOC system. It is of great significance for the cost reduction and the possession of intellectual property.

REFERENCES [1] Xing Yuhua, Wang Ru, An Optimized Design of MCU in CPU Soft-

core Based on the FPGA, The Eighth International Conference on Electronic Measurement and Instruments(ICEMI 2007), China,2007. China, pp.16-29

[2] Li Jingpeng, An optimized design of MCU including predication, Microelectronics and computer, vol.23, pp.25-27, 2006

[3] Pan Song, Pan Ming, Principles of Modern Computer Architecture. Science Press, 2007.

[4] Pan Song, Huang Jiye, EDA Tecnologey and VHDL, Tsinghua University Press, 2002

[5] Zhang Kai, Tang Zhizhong, design and implement of 16-bit general CPU, Computer Engineering and Applications, vol.32, pp.116-117, 2003.

[6] William Stallings. The Structure of Computer. Tsinghua Publishing Company China, 2000

[7] Wayne Wolf, Modern VLSI Design, Printice Hall, 2001 [8] Tian Hong-li, Yan Hui-qiang, Geng Heng-shan, Liu Su, Design and

implementation of 8 bit micro-controller, Computer Engineering and Applications, vol.46, pp.60-63, 2010

[9] WANG Peilin, Design of an 8-bit CISC CPU based on FPGA, Coal Technology, Vol.29, pp.10, 2010

[10] Qi Mei, Zhang Peng, Dong Ye, Chang Lei, Design and Realization of Model Machine Based on CPLD Combinational Logic Controller, Research and exploration in labortaory, vol.29, pp.7, 2010

/ColorImageDict > /JPEG2000ColorACSImageDict > /JPEG2000ColorImageDict > /AntiAliasGrayImages false /CropGrayImages true /GrayImageMinResolution 200 /GrayImageMinResolutionPolicy /OK /DownsampleGrayImages true /GrayImageDownsampleType /Bicubic /GrayImageResolution 300 /GrayImageDepth -1 /GrayImageMinDownsampleDepth 2 /GrayImageDownsampleThreshold 2.00333 /EncodeGrayImages true /GrayImageFilter /DCTEncode /AutoFilterGrayImages true /GrayImageAutoFilterStrategy /JPEG /GrayACSImageDict > /GrayImageDict > /JPEG2000GrayACSImageDict > /JPEG2000GrayImageDict > /AntiAliasMonoImages false /CropMonoImages true /MonoImageMinResolution 400 /MonoImageMinResolutionPolicy /OK /DownsampleMonoImages true /MonoImageDownsampleType /Bicubic /MonoImageResolution 600 /MonoImageDepth -1 /MonoImageDownsampleThreshold 1.00167 /EncodeMonoImages true /MonoImageFilter /CCITTFaxEncode /MonoImageDict > /AllowPSXObjects false /CheckCompliance [ /None ] /PDFX1aCheck false /PDFX3Check false /PDFXCompliantPDFOnly false /PDFXNoTrimBoxError true /PDFXTrimBoxToMediaBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXSetBleedBoxToMediaBox true /PDFXBleedBoxToTrimBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXOutputIntentProfile (None) /PDFXOutputConditionIdentifier () /PDFXOutputCondition () /PDFXRegistryName () /PDFXTrapped /False

/CreateJDFFile false /Description > /Namespace [ (Adobe) (Common) (1.0) ] /OtherNamespaces [ > /FormElements false /GenerateStructure false /IncludeBookmarks false /IncludeHyperlinks false /IncludeInteractive false /IncludeLayers false /IncludeProfiles true /MultimediaHandling /UseObjectSettings /Namespace [ (Adobe) (CreativeSuite) (2.0) ] /PDFXOutputIntentProfileSelector /NA /PreserveEditing false /UntaggedCMYKHandling /UseDocumentProfile /UntaggedRGBHandling /UseDocumentProfile /UseDocumentBleed false >> ]>> setdistillerparams> setpagedevice