2011-12 OTA gm Id.pdf
Transcript of 2011-12 OTA gm Id.pdf
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B. E. Boser 1
Analog Design Using
gm/Id and ft Metrics
Bernhard E. Boser
Copyright © 2011 Bernhard Boser
Analog design using gm/Id and ft metrics
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B. E. Boser 2
Overview
• Traditional analog design methodologies typically require iteration
– “Square Law” design equations are inaccurate for submicron devices
– Depend on poorly defined parameters: mCox, Vth, Vdsat, …
– Difficult to achieve an “optimum” (e.g. minimum power)
• gm/Id-based design
– Links design variables (gm, ft, Id, …) to specification (bandwidth, power)
– Employs design charts to accurately size transistors
Analog design using gm/Id and ft metrics
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B. E. Boser 3
Motivation: A design example
Specifications:
• Small signal gain: av = vo/vi = 5
• Bandwidth: B ≥ 10MHz
• Source resistance: Rs = 1MW
• Load capacitance: CL = 5pF
• Minimum power dissipation
Analog design using gm/Id and ft metrics
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B. E. Boser 4
Design Approaches
Design equations (Square-Law model)
Difficulties
• Sub-micron transistors are not well
described by these equations
• Non-obvious relation of model
parameters to design specification
• Leads to many iterations
• What is the minimum power, anyway?
Analog design using gm/Id and ft metrics
212
. ...
Wd ox GS THL
Wm ox GS THL
GS ox
I C V V
g C V V
C C WL
etc
m
m
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B. E. Boser 5
Natural Variables for Analog Design
Id
VDSVGS
idvgs vdsCgs
• Transconductance gm
• Current Id
• Efficiency gm/Id
• Capacitance Cgs, …
• Transit frequency ft = gm/2pCgs
Analog design using gm/Id and ft metrics
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B. E. Boser 6
Example
Specifications:
• Small signal gain: av = vo/vi = 5
• Bandwidth: B ≥ 10MHz
• Source resistance: Rs = 1MW
• Load capacitance: CL = 5pF
• Minimum power dissipation
Design constraints
• Low frequency gain
• Pole at input
• Pole at output
Analog design using gm/Id and ft metrics
av LgmR
1 1
2s gs
pin CR Bp
1 1
2L L
pout BR C
p
2
1
2
minimize
m
GS
d
L
s
g
BRC
I
BCp
p
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B. E. Boser 7
Design Constraints and Objectives
Design constraints
Analog design using gm/Id and ft metrics
Design objectives
1. High current efficiency
to minimize power
2. Small Cgs high fT
to meet bandwidth
constraint
2 1.57 mS
116 fF
2
minimize
m
sGS
d
Lg
R
I
BC
BC
p
p
m
d
g
I
2m
tgs
gf
Cp
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B. E. Boser 8
Transit Frequency fT
Analog design using gm/Id and ft metrics
NMOS (simulation)
fT versus gm/Id tradeoff Compromise
• high gm/Id for low power
• high ft for low Cgs
Design choice
• Maximum Cgs to meet
specification at
minimum power: • minimum ft • minimum L
• maximum gm/Id
,min
,min
,max
15.7 GHz2
m
t
gs
gf
Cp
15.7 GHz
14 V-1
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B. E. Boser 9
Transistor Current Efficiency gm / Id
Analog design using gm/Id and ft metrics
• Weak Inversion
• Good current efficiency
• High output voltage range
• Low ft • Large transistors
(low )sat
dV
• Strong Inversion
• Poor current efficiency
• Low output voltage range
• High ft • Small transistor
5 10 15 20
400m 200m 133m 100m
1 [ V ]m dg I
2 [ V ]
m dg I
Low
gm/Id
High
gm/Id
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B. E. Boser 10
Completing the Design: Transistor Sizing
Analog design using gm/Id and ft metrics
114 V and 16 GHz
112 A
A12.4 (from chart)
m
9 m
mT
d
md
m d
d
d
d
gf
I
gI
g I
I
W
IW
I W
m
m
12.4 A/m
14 V-1
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B. E. Boser 11
Verification: (1) Bias
Analog design using gm/Id and ft metrics
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B. E. Boser 12
Verification: (2) Specification
• Bias is as designed
• Gain and bandwidth
slightly below spec
• Design ignored
transistor ro and self-
loading
• Adjust by choosing a
slightly higher ft
Analog design using gm/Id and ft metrics
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B. E. Boser 13
Summary
Analog design using gm/Id and ft metrics
Silicon “Square Law”
based design SPICE Model
gm/Id
based design
Simple
“Square Law”
Equations
Complicated
Equations
(BSIM, PSP, …)
Complicated
Physics
gm/Id & ft
Charts
(process specific)
• Accurate
• Good for verification
• Unsuitable for
design
• Popular (textbooks)
• Poor accuracy
• Requires iterations
• Difficult to achieve
optima
• Good accuracy
• Simple equations
• Transistor data
from charts
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B. E. Boser 14
NMOS Transit Frequency fT
Analog design using gm/Id and ft metrics
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B. E. Boser 15
PMOS Transit Frequency fT
Analog design using gm/Id and ft metrics
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B. E. Boser 16
Extrinsic Capacitances Cgd and Cdd
Analog design using gm/Id and ft metrics
NMOS PMOS
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B. E. Boser 17
NMOS Current Density
Analog design using gm/Id and ft metrics
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B. E. Boser 18
PMOS Current Density
Analog design using gm/Id and ft metrics
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B. E. Boser 19
NMOS Intrinsic Gain gm ro
Analog design using gm/Id and ft metrics
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B. E. Boser 20
PMOS Intrinsic Gain gm ro
Analog design using gm/Id and ft metrics
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B. E. Boser 21
Intrinsic Gain gm ro
Analog design using gm/Id and ft metrics
NMOS PMOS
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B. E. Boser 22
OTA Design Example
Specifications
• Voltage gain Av = 2
• Dynamic range DR ≥ 72dB
• Settling accuracy ed ≤ 100ppm
• Settling time ts ≤ 10ns
Analog design using gm/Id and ft metrics
+
vid
-
+
vod
-
Cs
Cs
Cf
Cf
CL
CL
• Switched capacitor gain stage
(switches not shown)
• Applications: A/D converters, filters, …
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B. E. Boser 23
Circuit Topology
Analog design using gm/Id and ft metrics
vid
vod
vi
Ro
Gmvx
CoCx
vo
CL
Cf
Csvx
VDD
Vip Vim
Vom - Vod + Vop
ITIT/2
MN1a MN1b
MP1a MP1bMPB
• Fully differential OTA
• Common mode and
• cascodes (for gain) not shown
• Differential mode half circuit
• Large & small signal models
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B. E. Boser 24
Design Flow
1. Determine feedback factor
2. Determine CL to meet dynamic range requirement
3. Determine gm to meet settling requirement
4. Pick transistor characteristics based on analysis
– Channel length L
– Current efficiency gm/ID (or ft)
5. Determine bias currents and transistor sizes
– ID (from gm and gm/ID)
– W (from ID/W, current density chart)
Analog design using gm/Id and ft metrics
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B. E. Boser 25
(1) Feedback Factor
• Open feedback loop
• Cx is amplifier input capacitance (Cgs + …)
– Small Cx large feedback factor b
– Large Cx low transistor ft requirement higher gm/Id reduced current
– Typically Cx = (⅓ … 1) x (Cs + Cf) (shallow optimum)
Analog design using gm/Id and ft metrics
1
1
x f
xo f s xv
f
v C
Cv C C CA
C
b
vi
Ro
Gmvx
CoCx
vo
CL
Cf
Csvx
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B. E. Boser 26
(2) Dynamic Range
Dynamic range:
Minimum load capacitance:
Analog design using gm/Id and ft metrics
CLtotbvo
vo
MP
MN
4kTgpgmp
4kTgngmn
R
1
mn
Rg
b
22,
4 11
mp do nmn
mn d Ltot
g Iv RkT g
f g I j RCg
2,
11
with 1
mpo n
mn
Ltot L f
Ltot
gk
C
C
Tv
g
C C
g
b
b
Output resistance:
Noise density:
Sampled noise:
2,max
2 1mp
Ltotmn o
g DRC kT
g V
g
b
21,max2
2,
o
o n
VDR
v
choose for low noisemp mn
d d
g g
I I
PMOS
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B. E. Boser 27
(3) Settling
Analog design using gm/Id and ft metrics
Gm
Vout
Cf
Cs
Cin
Vstep
CL
Vin(t)
0
0 2 4 6 8 100
0.2
0.4
0.6
0.8
1
t/
Vout/V
out,id
eal
Dynamic Error ed(t) Static Error e0
Settling time ts
/0
0
Step response: ( ) 1 with 1
ts Ltotout step
f mn
C T Cv t V e
C T g
b
/std e
e
for single pole
response
Solve for transconductance: lnLtot d
mns
Cg
t
e
b
ideal
response
static
error
dynamic
error
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B. E. Boser 28
(4) Transistor Channel Length, gm/Id and ft
Analog design using gm/Id and ft metrics
NMOS PMOS
L 180 nm 250 nm Ln,min reduces power
gm/Id 12 V-1 8 V-1 gmp/Id < gmn/Id (noise)
ft 19.7 GHz 3.78 GHz Cgsn < Cs + Cf
Id/W 18.7 A/m 7.06 A/m
• Reduce gm/Id of NMOS if Cgsn < Cs + Cf
• ft and Id/W obtained from charts
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B. E. Boser 29
(5) Bias Currents and Transistor Sizes
Analog design using gm/Id and ft metrics
ota1.mcd
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B. E. Boser 30
Verification: (1) Test Bed
Analog design using gm/Id and ft metrics
OTA OTA in Feedback Loop
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B. E. Boser 31
Verification: (2) Bias
Analog design using gm/Id and ft metrics
So far, so good …
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B. E. Boser 32
Verification: (3) Dynamic Range
Analog design using gm/Id and ft metrics
perfect!
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B. E. Boser 33
Verification: (4) Settling Time
Analog design using gm/Id and ft metrics
• Dynamic settling error target met
• Large static error ~10%
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B. E. Boser 34
Openloop Gain
Analog design using gm/Id and ft metrics
• Openloop gain only Avo ~ 50
• To = b Avo = 11
• Add cascodes to increase
low frequency gain
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B. E. Boser 35
Generic gm/Id-based Design Flow
1. Determine gm from design objectives (dynamic range, bandwidth, …)
2. Pick L
– Short channel high ft (high speed)
– Long channel high intrinsic gain, good matching, …
3. Pick gm/ID or ft
– Large gm/ID low power, large signal swing
– Small gm/ID high ft (high speed)
4. Determine ID (from gm and gm/ID)
5. Determine W (from ID/W, current density chart)
• Adapt to design specifics
Analog design using gm/Id and ft metrics
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B. E. Boser 36
Acknowledgements
• Prof. Boris Murmann
• Prof. Paul Gray
• Prof. Ali Niknejad
• Prof. Elad Alon
• Many generations of students
Analog design using gm/Id and ft metrics