A Turbo Co/Decoder implementation

for next generation DVB-S2

S.Benedetto1, T.Botticchio

2, P.Burzigotti

2, R.Degaudenzi

3, A.Martinez

3, G.Montorsi

1, F.Richichi

2

and P. Tabacco4.

1 DELEN, Politecnico di Torino, Corso Duca degli Abruzzi 24

Phone: +39 011 5644099 fax: +39 011 5644000, sergio.benedetto@polito.it, guido.montorsi@polito.it

2 Space Engineering S.p.A., via dei Berio 91, 00155 Roma Italy

Phone. +39 06 225951, Fax. +39 06 2280739, botticchio@space.it, burzigotti@space.it, richichi@space.it

3 TOS-ETC, ESA/ESTEC, Keplerlaan 1, Postbus 299, 2200 AG Noordwijk (The Netherlands)

Phone. +31 715654227, Fax. +31 715654596 rdegaude@xrsun0.estec.esa.nl,

Phone. +31 715654943, Fax. +31 715654596 Alfonso.Martinez@esa.int

4 DSP SYSTEMS, via dell'Orsa Maggiore 21, 00144 Roma Italy, mc4759@mclink.it

Abstract

Present work describes the algorithmic design and show the performance of a Turbo

Decoder aimed for low Eb/No working points (near Shannon limit) that was purposely

design to work in a pragmatic approach with the following constellations QPSK, 8PSK,

16APSK, 16QAM. This Turbo Codec is based on a pure Turbo Codes implementation

without the need of additional Reed Solomon Outer Codec.

1 Overview

Turbo codes, first introduced in 1993, are a new way to construct concatenated codes able to

achieve near Shannon-limit error correction in terms of BER. The presence of large interleavers and

iterative feedback decoding allow reaching these results thanks to relatively simple structure.

In a first issue turbo codes have been presented in parallel fashion, made up by two RSCs

(Recursive Systematic Codes) and an interleaver. The progress of the study gets possible different

choices in number, type and concatenation of coders to obtain solutions with different performances

and complexity (both during encoding and decoding phase). Today a serial concatenation seems to

allow better performance, yielding lower error floors than parallel concatenated codes (PCCC).

Also, they usually employ constituent encoders with lower complexity (less states) leading to a

remarkably simpler decoding algorithm.

In order to improve the bandwidth efficiency it is also possible to cascade a high-level modulator,

as alternative to traditional TCM (trellis code modulation).

In the following Figure 1 an general scheme for a codulator (coder and modulator) is depicted.

Particularly, in our study-case the encoder is a TURBO encoder, the source produces equally

probable binary symbols (0/1), the modulator is a QPSK, 8PSK, 16PSK or 16QAM.

Figure 1: Codulator scheme

The quantities shown in the previous Figure 1 are related by the following relationships:

Rs transmission rate of the source

Re =Rs/rc encoded stream rate

Rm = Re/M = Rs/(Mrc) = Rs/r baud rate

The parameter rc characterizes the encoder in terms of bandwidth and error correcting capability; it

means how much redundancy is introduced.

2 Logic Structure

The presence of a multilevel modulation involves a first choice about the turbo encoder: in literature

both "pragmatic" and "ad-hoc" encoders are present. The bottom refers to turbo-coder related to the

(known) modulation, with a direct mapping of encoder outputs to the constellation points. Being

assigned a source rate and the code rate rc, the modulation and the mapping rule are selected

together to obtain the prefixed channel symbol rate Rm.

A "pragmatic" solution, instead, is completely independent from the modulation and, then, from Rm,

with a major flexibility: it is possible to fix the code rate and modulation independently; the correct

channel symbol rate is achieved with an appropriate puncturing pattern. The advantage of a

"pragmatic" solution lies in its flexibility, being sources with different rates accepted without

needing for heavy modification. The present design of Turbo is aimed to work with different

modulation (QPSK, 8PSK, 16APSK, 16QAM) achieving a number of spectral efficiency, but just

the puncturer has to be modified. The payment is a slightly lower performance.

In the present paper we refer to a "pragmatic" SCCC1 solution, characterized by the presence of an

outer 16-state convolutional coder, a puncturer, an interleaver and an inner differential encoder, a

pure Turbo without needing for concatenated code (such Reed-Solomon).

The main purpose of the interleaver is to avoid error patterns. After the corrections in one

dimension (first decoder) the remaining errors should be spread becoming correctable error patterns

in the second dimension (second decoder). The error correction capability of turbo code will

approach that of product code.

1 Serially Concatenated Convolutional Code

Input Register

size K

Outer

(Convolutional)

Encoder

rate 1/2

Interleaver

Inner

(Differential)

Encoder

rate 1/1

Modulationrow-column

InterleaverPuncturer

Figure 2: Codulator scheme.

The Turbo is made out of two convolutional codes serially concatenated using 16-states (outer

code) and 2-states (inner code). A triangular, asymmetric S-random interleaver with fixed length

12000 bits is used. The structure for different supported coding rates and modulation is shown in

the following Table 1.

Table 1. Different modulation parameters design.

ModulationFEC Rate

[r]

Spectral

efficiency

[�] (bps/Hz)

Channel symbols

per block [F]

Information bits

per block [K]

1/2 0.994 6000 5996QPSK

3/4 1.491 6000 8996

2/3 1.988 4000 79968-PSK

5/6 2.486 4000 9996

3/4 2.983 3000 899616-APSK

(16-QAM) 7/8 3.480 3000 10496

Table 2. Target Eb/N0 for different spectral efficiencies with 8PSK modulation.

Code rate SpectralEfficiency

Eb/N0Standard

[dB]

Capacity Const.Capacity

1 dB worsethan const.

capacity

Target Eb/N0 [dB](2 dB overstandard)

2/3 2 6.45 2.77 3.14 4.14 4.45

3/4 2.25 7.33 3.67 4.04 5.04 5.33

4/5 2.4 7.75 4.29 4.65 5.65 5.75

In order to set the performance specifications for the project, we have evaluated the Eb/N0 in dB

required to obtain a “quasi error free” information flow at the input of the MPEG multiplexer. We

based on the DVB standard document [2] but since in our case the spectral efficiencies are different

from the DVB standard (lacking Reed-Solomon encoder), we have interpolated linearly the values

reported in [2].

An example is summarized in Table 2 where the 3rd

column represent the Eb/N0 given by the

standard, the 4th

column the value of Eb/N0 induced by capacity, the 5th

the block-size constrained

bound for interleaver size 12,000 and BER=10-10

, the 6th

the values at 1 dB from constrained

capacity with block size 12,000, and the 7th

the agreed objectives of Eb/N0 yielding a 2 dB gain

with respect to the standard.

3 Encoder

This section simply reports the chosen encoders constituting TURBO. The outer encoder is the first

that bits meet, while the outer is just before the channel interleaver.

3.1 Inner differential encoder

z-1U=0

U=1

S0

S1

S0

S1 1

0

1

0

S={S0,S

1} C={C

0} U={U

0}r = 1/1 k

0=1 , n

0=1

t=k t=k+1

C0

U0

Figure 3. 2-states Systematic Encoder for rate 1/1.

The choice of so a simple inner encoder is made in orders to minimize the presence of floor during

decoding. It can be shown that the outer code rate (ro) must be as lower as possible, then inner code

rate (ri) as greater as possible: 0*rrr ic = .

As the inner code rate is 1/1 it prevents this code be systematic.

3.2 Outer convolutional encoder

The scheme in Figure 4 represents the recursive convolutional encoder. It is a 16-states machine with

a code rate fixed to 1/2.

z-1

r = 1/2

C0

U0

z-1 z-1 z-1

C1

Figure 4. 16 states Recursive Systematic Encoder for rate 1/2.

4 Decoder

In literature a number of decoding algorithm are known, but just ML (Maximum Likelihood) and

MAP (Maximum A Posteriori) are implemented for their performance; both of them are studied to

be implemented in turbo decoders.

The ML algorithm, known also as Viterbi algorithm minimizes the probability of code word error

but not the single symbol error. During the decoding process only the probability of most likely

sequences is calculated and compared to obtain survivor for the sequent step. No information about

the symbol is calculated but just that of the whole sequence. Even if solutions, such as SOVA, were

proposed to modify and to improve the original ML algorithm making possible the exchange of

"soft" information about the single symbol probability, they still remain sub-optimal solution.

The MAP, instead, is a more complicated algorithm (then with a major implementation complexity)

that points to the minimization of symbol error through the maximization of the a-priori knowledge

of single symbol probability.

The basic feature of turbo decoders is the feedback of information elaborated during the process. A

complete decoding is carried out after a number of decoding iteration on the same block of input

symbols.

From soft

channel

interleaver

SISOINNER

(differential) DE-

INTERLEAVER

INTERLEAVER

P(C2,I)

P(U2,O)

SISOOUTER

(convolutional)

P(C2,O)

P(C1,I)

P(C1,O)

P(U1,O)

P(U2,I)

P(Ci,I/O) = A PRIORI PROBABILITY of coded bits I/O from i-th SISO

P(Ui,I/O) = A PRIORI PROBABILITY of information bits I/O from i-th SISO

6 bit quantization

8 bit quantization

NOT used

6

88 8

8

8

P(U1,I)

DE-

PUNCTURER

PUNCTURER8

Figure 5: SISO interconnection to exchange extrinsic information.

The constituent blocks, labeled SISO (Soft Input - Soft Output), implement a recursive exchange of

information one to other in order to have the knowledge on information bits grown. No hard

decision is made during the decoding process but "soft" information is calculated that is a

"weighted" decision.

The SISO block accepts as input the a priori probability of information bits and coded bits from a

previous estimation and outputs their update version toward the next block.

The APP algorithm is based on the calculation of probabilities associated to trellis. Particularly, the

scope of the decoder is to allow a decision based on comparison of the probability that bit is 1 and

the probability that bit is 0. It is possible to obtain that comparison one shot simply modifying the

original algorithm and propagating llr2 values.

5 Implementation

The Turbo Codec was implemented using the architecture and the fast prototyping system shown

below.

The Codec implementation had a maximum rate of 2Mbps with 7 iterations.

Changing the Coder rate we could experience at 400Kbps up to 30 iterations.

2 log likelihood ratio, defined as

( )( )���

�����

=

=

0

1log

uP

uP

c1 πΙ

c0

RAM

1

RAM

2

RAM

3

MUXMUX MUXMUX

αβ1

M

U

X β2

M

U

X

πO

llr(c1 )

llr(c0 )

RAM

α

π(c)

π(c)

π(c)

αk

ΙΝΙ

27

27

27

8

8

192

2727 27

192192

192

192

192

88

192

Figure 6. SISO memory architecture.

∆MAX-MIN

M

U

X

MS

B

LUTCORR α

k+1(s)

βk-1

(s)

ACS - PEπk(c)

αk(s)

βk(s)

αk(s)

βk(s)

MAX

πk(c)

9

12 12

9

12 12

12 12 12

Figure 7. ACS Processor Element (ACS-PE).

FPGA1

Connection

FPGA

MS1

0x482000 - 0x482FFF

DSP 6

SHARC

SHARK6

BOARD

prog bus

SIM

M

FPGA3

PC LPT1

interface

(Frame Sync)

MS1

0x481000 - 0x481FFF

FPGA5

Soft

Demodulator

MS1

0x480000 - 0x480FFF

FPGA6

UART inteface

BER Meter

MS0

/ 5 I,Q

IQ_vaild

start_read

/ 24 llr

llr_valid

llr_ready

fs_sync

/ 24 llr

sta

rt_re

ad

llr_valid

llr_re

adyd

ecoded_out

decoded_out_

valid

SIM

M

/16 data, /16 addr, / 3 csb, rdb, wrbprog bus

decoded_out

decoded_out_valid

/16 p

rog_data

/16 p

rog_addr

pro

g_csb

pro

g_rd

b

pro

g_w

rb

clk 20 MHz

clk 20 MHz clk 20 MHz

clk

20 M

Hz

decoded_out

decoded_out_

valid

UART

R

A

M

R

A

M

FPGA

ALTERA

EP20K1500E-

1XALTERA

DSP BUILDER

PROFESSIONAL

DEVELOPMENT BOARD

SISO+

Interleaver+

De-Interleaver

:

2

40 MHz

MS

2

External PC

Figure 8.Shark6 board.

6 Performances

The Turbo Codec performance measured from the HW demonstrator is shown for rate 2/3 and 4/5

in terms of BER, FER and PER.

BER/EbNo 2/3

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

3.0

0

3.1

0

3.2

0

3.3

0

3.4

0

3.5

0

3.6

0

3.7

0

3.8

0

3.9

0

4.0

0

4.1

0

4.2

0

4.3

0

4.4

0

4.5

0

EbNo

ME

AS

UR

ED

BE

R

Figure 9 Rate 2/3 performances

STATISTICS 2/3

0.00001

0.0001

0.001

0.01

0.1

1

3.0

0

3.1

0

3.2

0

3.3

0

3.4

0

3.5

0

3.6

0

3.7

0

3.8

0

3.9

0

4.0

0

4.1

0

4.2

0

4.3

0

4.4

0

EbNo

FER

PER

vPER

Figure 10 Rate 2/3 performances

BER/EbNo 4/5

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

4.6

5

4.7

0

4.7

5

4.8

0

4.8

5

4.9

0

4.9

5

5.0

0

5.0

5

5.1

0

5.1

5

5.2

0

5.2

5

5.3

0

5.3

5

5.4

0

5.4

5

5.5

0

5.5

5

5.6

0

5.6

5

5.7

0

5.7

5

EbNo

ME

AS

UR

ED

BE

R

Figure 11. Rate 4/5 performances

STATISTICS 4/5

0.0000001

0.000001

0.00001

0.0001

0.001

0.01

0.1

1

4.5

0

4.6

0

4.7

0

4.8

0

4.9

0

5.0

0

5.1

0

5.2

0

5.3

0

5.4

0

EbNo

FER

PER

vPER

Figure 12. Rate 4/5 performances

7 Conclusion

The designed and implemented Turbo Codec is aimed for close to Shannon Limits performances

uniformly with the Pragmatic approach for the QPSK, 8-PSK, 16-APSK, 16-QAM digital

modulation approaches. The Codec has been implemented using off the shelf HW fast prototyping

systems and could be used for the next generation DVB-S2 application with an overall 2dB

improvement with respect to DVB-S1 (first generation).

8 List of Acronyms

APP A Posteriori Probability

RSC Recursive Systematic Code

SCCC Serially Concatenated Convolutional Code

SISO Soft Input Soft Output

SOVA Soft Output Viterbi Algorithm

9 References Documents.

[1] S.Benedetto, D.Divsalar, G.Montorsi, F.Pollara, "A Soft-Input Soft-Output APP Module for

iterative Decoding of Concatenated Codes", IEEE Communication Letters, Vol.1, NO.1, January

1997.

[2] Digital Viedo Broadcasting (DVB): Framing structure, channel coding and modulation for

Digital Satellite News Gathering (DSNG) and other contribution applications by satellite. European

Telecommunication Standard, prEN 301 210, January 1998.