20-port, 10GbE Switch Chip On-Chip Code API

Confidential

MB8AA3020

20-port, 10GbE Switch Chip

On-Chip Code API

MB8AA3020

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Fujitsu Microelectronics America, Inc.

Confidential

Revision: 1.5

Last Updated: June, 2007

Document #: 10GE-RM-21250-6/2007

Copyright © 2005, 2006, 2007 Fujitsu Laboratories of America, Inc. All rights reserved.

This document contains confidential information and trade secrets of Fujitsu Laboratories of America, Inc. which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission of Fujitsu Laboratories of America, Inc. Use of copyright notice is precautionary and does not imply publication or intent thereof.

All information contained in this document is subject to change without notice. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness.

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Table of Contents

1. Overview ..........................................................................................................................................................................1

1.1 General Description...................................................................................................................................................1

2. Functional Description.......................................................................................................................................................2

2.1 Packet Format ..........................................................................................................................................................2

3. Message Description...........................................................................................................................................................6

3.1 Message List .............................................................................................................................................................63.2 Message..................................................................................................................................................................10

Appendix A.........................................................................................................................................................................42

A.1 RAW Ethernet ....................................................................................................................................................... 42

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On-Chip Code API


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1. Introduction

1.1 General Description

This specification describes On-Chip Code API for the next generation Fujitsu 10Gbps Ethernet switch chip, AXEL-X MB8AA3020. The On-Chip code communicates with AXEL-X Driver for initialization, handling management protocols, transferring frames, performing MAC address Table, VLAN Table updates and support network management functions.

The management packets to be processed by Management are as follows:

• BPDU for the spanning tree protocol

• GVRP for the virtual LAN

• ICMP for the switch control such as ping

• SNMP for the network management such as statistics monitoring and switch reset

• IGMP / MLD Snooping

• sFLOW

• BCN (Backward Congestion Notification)

Figure 1: An Example of Software Configuration

On-Chip Code messages are categorized into followings:

•

Register Get/Set:

AXEL-X Core Register, PCS Register, MDIO, I2C

•

Memory Get/Set:

AXEL-X On-Chip Firmware Memory

•

Table Search/Learn/Delete/Flush/Get:

VLAN Table, MAC Address Table

•

Statistics Get/Clear:

Port, Priority, Flow Control, VLAN

• Packet Send/Receive

•

Trap:

Link Up/Down, Error

•

Protocol:

Ping, Sync, Restart

NIC Driver

On-Chip Code API

AXEL-X

AXEL-X On-Chip Code

AXEL-X Driver

API

Layer 2 Software

OS

for Management

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2. Functional Description

2.1 Packet Format

AXEL-X driver on a remote host communicates with On-Chip Code through Ethernet. The packet format is defined as follows:

• Type: Protocol Type for AXEL-X Packet (default value is 88B5h)

• Code: Massage code, even number for Request, odd number for Reply

• Length: The length of the message in bytes (optional data length)

• Flag / Status: Protocol Flag for Request and Status for the Reply, 0 for success, others for fail (Status is filed in Reply)

• Identifier: Identifier (Process Id of the sending process)

• Sequence number: Sequence number of the message

• Optional Data: Optional data which depends on the message code

Figure 2: Packet Format

Status Encoding

Table 1 shows encoding of the Status field in Reply packets.

Table 1. Encoding of Status Field

Encoding Message Name Notes

0 Success

-1 Busy

-2 Sequence Error

-3 Deferred For Split transaction

-4 Unexpected Message

-5 Illegal Message Undefined Message Code

-6 Not Supported Not supported in the on-chip code

-7 Restart Notification On-chip code re-started

others reserved

DA SA Type Code Length IdentifierSequenceNumber

OptionalData /

PaddingFCS

6 6 2 2 2 2 2 4

Flag /

2

Status

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Flag Encoding

Table 2 shows encoding of the Flag field in Request packets. This field is valid only in the messages which allow Split transactions. The messages include I2C Register Get / Set / Set with Bit Enable, MDIO Op, and MAC Table Flush.

An Example of Split transaction is shown below.

In the following example, the first I2C Register get initiates read operation on I2C bus. The second I2C Register Get checks completions of the read operation. In this case, the operation is still ongoing and Deferred status is returned. In the third I2C Register Get, the read operation on I2C bus have been completed and the read data is returned. Here a1, a2 are addresses, d1 and d2 are data, N1, N2, …are sequence numbers.

Re-transmission Protocol

A packet drop could happen in Request or Reply. When a time-out occurred or a sequence error is detected, packet(s) will be re-transmitted.

AXEL-X driver on a host and On-Chip Code have following variables:

• send_next: next sequence number to send (sender)

• send_una: sequence number unacknowledged (sender)

• recv_next: next sequence number to receive (receiver)

Table 2. Encoding of Flag Field

Encoding Description Notes

0 No Split Transaction

1 Split Transaction Start

2 Split Transaction End

Host AXEL-X On-Chip CodeI2C Register Get (Start, a1, N1) I2C Register Get (Success, xx, N1)

Register Get (Success, d2, N2)

I2C Register Get (Deferred, xx, N3)

I2C Register Get (End, a1, N4) I2C Register Get (Success, d1, N4)

Register Get (a2, N2)

I2C Register Get (End, a1, N3)

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Examples of the re-transmission are shown below.

AXEL-X driver can send multiple Requests to On-Chip Code before Replies are coming back. However the number of outstanding Requests is limited by the Reply queue length RepQlen (=1) at On-Chip Code.

This is because the Reply message needs to be re-transmitted from the Reply queue when a message is not reversible. For example, Register Get on a register with RC (Read Clear) attributes clears the register and not reversible.

Therefore a following guideline needs to be followed:

Guideline) If a message is not reversible and it is the problem, limit outstanding Requests to RepQlen.

• Register Get on RC/RW1C are not reversible.

• Register Set are not reversible.

• Statistics Collection is not the problem even it reads registers with RC attributes.

• Register Set followed by Register Get to the same address is not the problem.

The Reply queue is reset when SYNC message is received. The PING message is not kept in the Reply queue.

Case 1) Request is lostHost Link AXEL-X On-Chip Codesend_next send_una status status recv_next 1 1 1 2 Req(1) x(lost) time-out Req(send_una) Req(1) Reply(1) Reply(1) 2Case 2) Reply is lostHost Link AXEL-X On-Chip Codesend_next send_una status status recv_next 1 1 1 2 Req(1) Req(1) Reply(1) 2 x(lost) time-out Req(send_una) Req(1) Reply lost Reply(1) 2 Reply(1) 2

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Handling of Interrupts

On-Chip Code is handling a hardware interrupt and generates a Trap report to Host. There are three category in the interrupts. Handlings of the interrupt is different depending on the type.

Category 1)

No error or non-fatal error interrupts which does not require service by Host

Most of the Trap reports on no error or non-fatal error interrupts belong to this category. When an interrupt occurs, On-Chip Code masks or disable the corresponding interrupt, clear the interrupt and generate a Trap. Upon the reception of a reply from Host, it unmask or enable the interrupt.

Category 2)

No error or non-fatal error interrupts which requires service by Host

Port Security, Statistics Carry, Link Failure and Output Queue Status Traps belong to this category. For example, Port Security Trap requires a decision made by Host on an incoming frame for further operation. When an interrupt occurs, On-Chip Code mask or disable the corresponding interrupt and generate a Trap, which we call Service Required Trap. When a reply from Host is returned, it leaves the interrupt masked. Therefore Host is required to do an appropriate analysis and then clear and unmask the interrupt.

Category 3)

Fatal error interrupts

When a fatal error interrupt occurs, On-Chip Code logs the error and restarts by resetting chip. After initialization completes, On-Chip Code sends a corresponding trap report to Host.

Examples of the restart are shown below.

Case 1) Restart by ME HaltHost Link AXEL-X On-Chip Code

Case 2) Restart by ME Halt and Message Crossover

ME Halt is detected

Reset Chip and Restart

ME Halt Trap Restart Complete

Reply

SyncReply

Host Link AXEL-X On-Chip Code

ME Halt is detected

Reset Chip and Restart

ME Halt TrapRestart Complete

Reply

Sync

Reply

Register Get

Replyw Restarted

Register Get

time-out

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3. Message Description

Message List

Table 3 shows a list of messages for On-Chip Code API.

Table 3. List of Messages

Page Category Message Name Code Initiator Length Notes

10 Register Access Register Get 10 (Request) 11 (Reply)

Driver 8*n n = # of Reg

10 Register Set 12 (Request) 13 (Reply)


11 Register Set with Bit Enable 14 (Request)15 (Reply)


11 PCS Register Get 20 (Request) 21 (Reply)


12 PCS Register Set 22 (Request) 23 (Reply)


12 PCS Register Set with Bit Enable 24 (Request)25 (Reply)


13 MDIO Op 1 40 (Request) 41 (Reply)

Driver 4*n Use Port 1n = # of Reg

MDIO Op 2 50 (Request) 51 (Reply)


13 I2C Register Get 1 60 (Request) 61 (Reply)


14 I2C Register Set 1 62 (Request) 63 (Reply)


14 I2C Register Set with Bit Enable 1 64 (Request)65 (Reply)


15 I2C Register Get 2 70 (Request) 71 (Reply)


15 I2C Register Set 2 72 (Request) 73 (Reply)


16 I2C Register Set with Bit Enable 2 74 (Request)75 (Reply)


16 Memory Access Memory Get (for debug / customization) 80 (Request) 81 (Reply)

Driver 4*n n = # of Addr

17 Memory Set (for debug) 82 (Request) 83 (Reply)

Driver 4*n n = # of Addr

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17 Table Access MAC Table Search 1 100 (Request)101 (Reply)

Driver 16 use Reg Set 1

18 MAC Table Learn 1 102 (Request)103 (Reply)


18 MAC Table Delete 1 104 (Request)105 (Reply)


19 MAC Table Flush 1 106 (Request)107 (Reply)


19 MAC Table Get 1 108 (Request)109 (Reply)

Driver 8+12*n use Reg Set 1n = # of entry

20 MAC Table Read 1 (for debug) 110 (Request)111 (Reply)


20 MAC Table Write 1 (for debug) 112 (Request)113 (Reply)


MAC Table Search 2 120 (Request)121 (Reply)


MAC Table Learn 2 122 (Request)123 (Reply)


MAC Table Delete 2 124 (Request)125 (Reply)


MAC Table Flush 2 126 (Request)127 (Reply)


MAC Table Get 2 128 (Request)129 (Reply)


MAC Table Read 2 (for debug)

130 (Request)131 (Reply)


MAC Table Write 2(for debug)

132 (Request)133 (Reply)


21 VLAN Table Search 140 (Request)141 (Reply)

Driver 24

21 VLAN Table Learn 142 (Request)143 (Reply)

Driver 24

22 VLAN Table Read (for debug) 144 (Request)145 (Reply)

Driver 24

22 VLAN Table Write (for debug) 146 (Request)147 (Reply)

Driver 24

23 Statistics Collection Statistics Get 200 (Request)201 (Reply)

Driver 8+x*#port+y*#monVLAN+z

27 Statistics Clear 202 (Request)203 (Reply)

Driver 8

27 Packet Transfer Packet Send 300 (Request)301 (Reply)

Driver 8+n (Request)8 (Reply)

28 Packet Receive 302 (Request)303 (Reply)

AXEL-X 8+n (Request)8 (Reply)

28 Packet Receive Traffic Monitoring 304 (Request)305 (Reply)

AXEL-X 8+n (Request)8 (Reply)


(Continued)


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29 Trap CM MBE 500 (Request)501 (Reply)

AXEL-X 8 Reported after Reset

29 Drop Queue MBE 502 (Request)503 (Reply)


30 Output Queue MBE 504 (Request)505 (Reply)


30 Tag MBE 506 (Request)507 (Reply)


31 ME Halt 510 (Request)511 (Reply)


31 Statistics Carry 520 (Request)521 (Reply)

AXEL-X 8

32 MAC Table MBE 522 (Request)523 (Reply)

AXEL-X 8

32 VLAN Table MBE 524 (Request)525 (Reply)

AXEL-X 8

32 Drop Queue SBE 526 (Request)527 (Reply)

AXEL-X 8

32 SM Tag MBE 528 (Request)529 (Reply)

AXEL-X 8

33 SM Tag SBE 530 (Request)531 (Reply)

AXEL-X 8

33 Output Queue SBE 532 (Request)533 (Reply)

AXEL-X 8

33 Tag SBE 534 (Request)535 (Reply)

AXEL-X 8

33 IBUF Tag MBE 536 (Request)537 (Reply)

AXEL-X 8

34 IBUF Tag SBE 538 (Request)539 (Reply)

AXEL-X 8

34 Port Interrupt 540 (Request)541 (Reply)

AXEL-X 8

34 Link Failure 542 (Request)543 (Reply)

AXEL-X 8

34 MST MBE 544 (Request)545 (Reply)

AXEL-X 8

35 MST SBE 546 (Request)547 (Reply)

AXEL-X 8

35 MAC Table SBE 548 (Request)549 (Reply)

AXEL-X 8

35 VLAN Table SBE 550 (Request)551 (Reply)

AXEL-X 8


(Continued)


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Notes:

• “(message name) 2” has the same format with “(message name) 1” other than message code unless specified. Please see “(message name) 1” for the message format.

• For a message which includes multiple entries, entries are executed in order. For example, Memory Get read data from Address 1, then read data from Address 2, and so on.

35 Trap (Continued) CM SBE 552 (Request)553 (Reply)

AXEL-X 8

36 Output Queue Status 570 (Request)571 (Reply)

AXEL-X 8

36 Configuration Traffic Monitoring Get 800 (Request)801 (Reply)

Driver 16

37 Traffic Monitoring Set 802 (Request)803 (Reply)

Driver 16

38 Congestion Notification Get 810 (Request)811 (Reply)

Driver 40

39 Congestion Notification Set 812 (Request)813 (Reply)

Driver 40

40 Configure 10G Port 900 (Request)901 (Reply)

Driver 4

40 Protocol Ping 0 (Request)1 (Reply)

Driver 0

40 Sync 2 (Request)3 (Reply)

Driver 0

41 Restart 4 (Request) Driver 0


(Continued)


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Message

Name:

Register Get

Code:

10 (Request) / 11 (Reply)

Purpose:

Read AXEL-X Core Register value(s).

Field Description:

•

Address: Register address

•

Data: Register value (filled in Reply)

Register Get

Name:

Register Set

Code:


Purpose:

Write value(s) into AXEL-X Core Register(s).

Field Description:

•


•

Data: Register value to be written

Register Set

Code (10 or 11)

Length (8*n)

Identifier Sequence Number

Address 1 reserved

Data 1

0 15 16 31

...

Address n reserved

Data n

Status

Type Code (12 or 13)

Length (8*n)


Address 1 reserved

Data 1

0 15 16 31

...

Address n reserved

Data n

Type

Status

On-Chip Code API


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Name:

Register Set with Bit Enable

Code:


Purpose:

Write masked value(s) into AXEL-X Core Register(s).

Field Description:

•


•

Data: Register value to be written

•

Bit Enable: Data Bit Enable

Register Set with Bit Enable

Note:

AXEL-X read a register and write back a masked data into the register.

Name:

PCS Register Get

Code:


Purpose:

Read AXEL-X PCS Register value(s).

Field Description:

•


•

Port: 5 bit Port number

•

Data: Register value (filled in Reply)

PCS Register Get

Code (14 or 15)

Length (12*n)


Address 1 reserved

Data 1

0 15 16 31

...

Address n reserved

Data n

Bit Enable 1

Bit Enable n

Type

Status

Code (20 or 21)

Length (8*n)


Address 1 reserved

Data 1

0 15 16 31

...

Address n reserved

Data n

Port

Port

reserved

reserved

Type

Status

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Name:

PCS Register Set

Code:


Purpose:

Write value(s) into AXEL-X PCS Register(s).

Field Description:

• Address: Register address

• Port: 5 bit Port number

• Data: Register value to be written

PCS Register Set

Name: PCS Register Set with Bit Enable

Code: 24 (Request) / 25 (Reply)

Purpose: Write masked value(s) into AXEL-X PCS Register(s).

Field Description:

• Address: Register address

• Port: 5 bit Port Number

• Data: Register value to be written

• Bit Enable: Data Bit Enable

PCS Register Set with Bit Enable

Note: AXEL-X read a register and write back a masked data into the register.

Code (22 or 23)

Length (8*n)


Address 1 reserved

Data 1

0 15 16 31

...

Address n reserved

Data n

Port

Port

reserved

reserved

Type

StatusCode (24 or 25)

Length (12*n)


Address 1 reserved

Data 1

0 15 16 31

...

Address n reserved

Data n

Bit Enable 1

Bit Enable n

Port

Port

reserved

reserved

reserved

reserved

Type

Status

On-Chip Code API

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Name: MDIO Op 1


Purpose: Perform MIDO operation(s) at an external MIDO bus.

Field Description:

• ST: 00 for 10G MDIO, 01 for GMII/MII MDIO

• OP: 00 Address (10G only), 01 Write, 10 Read (GMII/MII), Post-read-increment address (10G), 11 Read (10G only)

• PRTAD: 5 bit Port Address

• DEVAD: 5 bit Device Address

• TA: should be 10 for both GMII/MII and 10G

• MIDO Address / Data: Register Address / Data (Data is filled in Reply)

MDIO Op 1

Name: I2C Register Get 1


Purpose: Read I2C Register value(s).

Field Description:

• Address: 16 bit Start Address


• BL: 2 bit Byte Length, 0 = 4 bytes, 1 = 2 bytes, 2 = 1 byte

• P: Packet Error Checking (PEC)

• Data: Register value (filled in Reply)

• N: NACK Received (filled in Reply)

• E: CRC Error (filled in Reply)

I2C Register Get 1

Code (40 or 41)

Length (4*n)


DEVAD MDIO Address / Data

0 15 16 31

...

PRTADOP

Type

Flag / Status

TAST

DEVAD MDIO Address / DataPRTADOP TAST


...


1

2

3

n

Code (60 or 61)

Length (8*n)


Data 1

0 15 16 31

...

Data n

DEVADAddress 1 N BLP 0

Address n

E

DEVADN BLP 0E

Type

Flag / Status

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Name: I2C Register Set 1


Purpose: Write value(s) into AXEL-X I2C Register(s).

Field Description:



• BL: 2 bit Byte Length, 0=4 bytes, 1=2bytes, 2=1byte


• Data: Register value



I2C Register Set 1

Name: I2C Register Set with Bit Enable 1


Purpose: Write masked value(s) into AXEL-X I2C Register(s).

Field Description:









I2C Register Set with Bit Enable 1


Code (62 or 63)

Length (8*n)


Data 1

0 15 16 31

...

Data n


Address n

E

DEVADN BLP 0E

Type

Flag / Status Code (64 or 65)

Length (12*n)


Data 1

0 15 16 31

...

Data n


Address n

E

DEVADN BLP 0E

Type

Flag / Status

Bit Enable 1

Bit Enable n

On-Chip Code API


Name: I2C Register Get 2


Purpose: Read I2C Register value(s).

Field Description:





• AL: Address Length, 0 = 1 byte, 1 = 2 bytes

• Data: Register value (filled in Reply)



I2C Register Get 2

Name: I2C Register Set 2


Purpose: Write value(s) into AXEL-X I2C Register(s).

Field Description:









I2C Register Set 2

Code (70 or 71)

Length (8*n)


Data 1

0 15 16 31

...

Data n


Address n

E

DEVADN BLP 0E

Type

Flag / Status

AL

AL

Code (72 or 73)

Length (8*n)


Data 1

0 15 16 31

...

Data n


Address n

E

DEVADN BLP 0E

Type

Flag / Status

AL

AL

MB8AA3020


Name: I2C Register Set with Bit Enable 2


Purpose: Write masked value(s) into AXEL-X I2C Register(s).

Field Description:










I2C Register Set with Bit Enable 2


Name: Memory Get


Purpose: Get memory data from the On-Chip Firmware Memory for debug and customization.

Field Description:

• Address: 16 bit Memory address

• Data: 16 bit word addresses by “Address” (filled in Reply)

Memory Get

Note: AXEL-X has valid address in [0x0000, 0x3fff]

Code (74 or 75)

Length (12*n)


Data 1

0 15 16 31

...

Data n


Address n

E

DEVADN BLP 0E

Type

Flag / Status

Bit Enable 1

Bit Enable n

AL

AL

Code (80 or 81)

Length (4*n)


Address 1

Data 2

0 15 16 31

...

Address n

Address 2

Type

Status

Data 1

Data n

On-Chip Code API


Name: Memory Set


Purpose: Set memory data in the On-Chip Firmware Memory for debug only.

Field Description:

• Address: 16 bit Memory address

• Data: 16 bit word addresses by “Address”

Memory Set

Note: AXEL-X has valid address in [0x0000, 0x3fff]

Name: MAC Table Search 1


Purpose: Search an entry in the MAC Address Table.

Field Description:

• MAC Address: 48 bit MAC Address to be searched

• VLAN ID: 12 bit VLAN ID for the MAC Address

• S: Static (filled in Reply)

• V: Valid (filled in Reply)

• Port Vector: 24 bit Port Vector (filled in Reply)

• MAC Table Information: Bit [0] =1 Success, 0 Fail , Bit [17:31] Entry address (filled in Reply)

MAC Table Search 1

Note: LS and MS Word, ex. 00:01:02:03:04:05LS Word ≤ 00_01_02_03, MS Word ≤ 04_05

Code (82 or 83)

Length (4*n)


Address 1

Data 2

0 15 16 31

...

Address n

Address 2

Type

Status

Data 1

Data n

Code (100 or 101)

Length (16)


MAC Address LS Word

MAC Address MS Word

0 15 16 31

reserved VLAN IDS

Port Vector

MAC Table Information

reserved

V

Type

Status

MB8AA3020


Name: MAC Table Learn 1


Purpose: Learn an entry in the MAC Address Table.

Field Description:



• S: Static

• V: Valid (filled in Reply)

• Port Vector: 24 bit Port Vector

• MAC Table Information: Bit [0] = 1 Success, 0 = Fail, Bit [17:31] Entry address (filled in Reply)

MAC Table Learn 1

Note: If the MAC address to learn already exists in the MAC Table, MAC Table Learn fails.

Name: MAC Table Delete 1


Purpose: Delete an entry in the MAC Address Table.

Field Description:



• MAC Table Information: Bit [0] =1 Success, 0 = Fail, Bit [17:31] Entry address (filled in Reply)

MAC Table Delete 1

Code (102 or 103)

Length (16)


MAC Address LS Word

MAC Address MS Word

0 15 16 31

reserved VLAN IDS

Port Vector


reserved

V

Type

Status

Code (104 or 105)

Length (16)


MAC Address LS Word

MAC Address MS Word

0 15 16 31

reserved VLAN ID


reserved

Type

Status

On-Chip Code API


Name: MAC Table Flush 1


Purpose: Flush entries by port vector in the MAC Address Table.

Field Description:

• D: Delete Dynamic entry only

• Port Vector: 24 bit Port Vector to compare

• MAC Table Information: Bit [0] = 1 Success, 0 = Fail, Bit [17:31] Entry address (filled in Reply)

MAC Table Flush 1

Note: MAC Table Flush cannot flush an entry with pv = 0 which can be registered by management for filtering purpose. MAC Table Delete should be used to delete the entry with pv = 0.

Name: MAC Table Get 1


Purpose: Get valid entries in the MAC Address Table.

Field Description:

• Entry Address: 15 bit Start Entry address

• Count: 5 bit # of Valid Entry to be read

• Count Return: 5 bit actual # of Valid Entry which were read (filled in Reply)

• Entry Data: MAC Address, VLAN ID, S(Static), V (Valid), Port Vector (filled in Reply)

• MAC Table Information: Bit [0] = 1 Success, 0 = Fail, Bit [17:31] Last Entry address (filled in Reply)

MAC Table Get 1

Notes:

• AXEL-X reads multiple entries until the count is reached, end of table is reached, or an error is encountered. It returns actual number of valid entries found as Count Return.

• MAC Table Information reflects the last entry read. Therefore Fail result may be returned when Count Return is less than Count.

• VLAN ID = 0 is returned in SVL (Shared VLAN Learning) mode.

Code (106 or 107)

Length (16)


reserved

reserved

0 15 16 31

reserved (12bits)D

Port Vector


reserved

Type

Flag / Status

Code (108 or 109)

Length (8+12*n)


MAC Address LS Word n

MAC Address MS Word n

0 15 16 31

VLAN ID n

Port Vector n


MAC Address LS Word 1

MAC Address MS Word 1 VLAN ID 1S

Port Vector 1

reservedV

...

Entry Address Count (n)

reserved

S reservedV

reserved

CountReturn

Status

Type

0 000000

MB8AA3020


Name: MAC Table Read 1


Purpose: Read entries in the MAC Address Table for debug only.

Field Description:


• Count: 5 bit # of Entry to be read

• Entry Data: MAC Address, VLAN ID, S(Static), V (Valid), Port Vector, ECC (filled in Reply)


MAC Table Read 1

Note: AXEL-X reads multiple entries until the count is reached or an error is encountered.

Name: MAC Table Write 1


Purpose: Write entries into the MAC Address Table for debug only.

Field Description:


• Count: 5 bit # of Entry to be written

• Entry Data: MAC Address, VLAN ID, S(Static), V (Valid), Port Vector, ECC


MAC Table Write 1

Note: AXEL-X writes multiple entries until the count is reached or an error is encountered.

Code (110 or 111)

Length (8+12*n)




0 15 16 31

VLAN ID n

Port Vector n




Port Vector 1

reservedV

...

Entry Address reserved Count

ECC

S reservedV

ECC

Type

Status

0

Code (112 or 113)

Length (8+12*n)




0 15 16 31

VLAN ID n

Port Vector n




Port Vector 1

reservedV

...

Entry Address reserved Count

ECC

S reservedV

ECC

Type

Status

0

On-Chip Code API


Name: VLAN Table Search


Purpose: Search an entry in the VLAN Table.

Field Description:

• V: Valid Bit (filled in Reply)

• VLAN ID: 12 bit VLAN ID

• USE: USE Bit per Port (filled in Reply)

• TAG: Tagging Bit per Port (filled in Reply)

• M: VLAN Mirroring Bit per entry (filled in Reply)

• Port State: MSTP Port State 2 bits per port (filled in Reply)

• VLAN Table Information: Bit [0] = 1 Success, 0 = Fail (filled in Reply)

VLAN Table Search

Name: VLAN Table Learn


Purpose: Learn an entry in the VLAN Table.

Field Description:

• V: Valid Bit


• USE: USE Bit per Port

• TAG: Tagging Bit per Port

• M: VLAN Mirroring Bit per entry

• Port State: MSTP Port State 2 bits per port


VLAN Table Learn

Code (140 or 141)

Length (24)


0 15 16 31

reserved

VLAN ID

M

USE

VLAN Table Information

reserved

TAG

Port State 23 to 16

Port State 15 to 0

reserved

Type

Status

reserved V reserved

Code (142 or 143)

Length (24)


0 15 16 31

reserved

VLAN ID

M

USE


reserved

TAG

Port State 15 to 0

Port State 23 to 16reserved

Type

Status

reserved V reserved

MB8AA3020


Name: VLAN Table Read


Purpose: Read an entry in the VLAN Table for debug only.

Field Description:

• V: Valid Bit (filled in Reply)


• R: Memory (RAM) ID Bit

• USE: USE Bit per Port (filled in Reply)

• TAG: Tagging Bit per Port (filled in Reply)

• M: VLAN Mirroring Bit per entry (filled in Reply)

• Port State: MSTP Port State 2 bits per port (filled in Reply)

• ECC: 8 bit ECC (filled in Reply)

• VLAN Table Information: Bit [0] =1 Success, 0 = Fail (filled in Reply)

VLAN Table Read

Name: VLAN Table Write


Purpose: Write an entry into the VLAN Table for debug only.

Field Description:

• V: Valid Bit


• USE: USE Bit per Port

• TAG: Tagging Bit per Port

• M: VLAN Mirroring Bit per entry

• Port State: MSTP Port State 2 bits per port

• ECC: 8 bit ECC


VLAN Table Write

Code (144 or 145)

Length (24)


0 15 16 31

reserved

VLAN ID

M

USE


reserved

TAG

Port State 15 to 0


ECC

Type

Status

reserved V reserved R

Code (146 or 147)

Length (24)


0 15 16 31

reserved

VLAN ID

M

USE


reserved

TAG

Port State 15 to 0


ECC

Type

Status

reserved V reserved

On-Chip Code API


Name: Statistics Get


Purpose: Get Port / Priority / Flow control / VLAN / Host Statistics.

Field Description:

• P: Port Statistics which includes Priority and Flow Control statistics.

• V: VLAN Statistics Packet counts and Byte counts per VLAN (up to 32 VLANs)

• D: Device Statistics which includes Host Monitoring and Learn Drop Statistics.

• PV: Port select for Port Statistics.

• Monitored VLAN: Monitored VLAN vector for VLAN Statistics.

• Port Statistics: Port Statistics, x bytes * # of ports selected in PV (filled in Reply if P = 1)

• VLAN Statistics: VLAN Statistics y bytes * # of Monitored VLAN (filled in Reply if V = 1)

• Device Statists: Device Statistics z bytes (filled in Reply if D = 1)

Statistics Get

Code (200 or 201)

Length(8+x*#port+y*MonVLAN+z)


0 15 16 31

reservedP

Port Statistics (x*#port, x = 340 bytes)

Device Statistics (z = 16 bytes)

PV

VLAN Statistics (y*#monitored VLAN, y = 24bytes)

V D

Monitored VLAN

Type

Status

MB8AA3020


Table 4 shows Port, VLAN and Device statistics to be returned in the Reply message.

Table 4. Statistics Counters

StatisticsByte

Offset AXEL-X Register Name Register Address Note

Port 0 Statistics Counter TRC64 base+480h

4 Statistics Counter TRC127 base+484h


12 Statistics Counter TRC511 base+48ch



24 Statistics Counter TRMGVC base+498h

28 Statistics Counter RXBYTC base+49ch

32 Statistics Counter RXPKTC base+4a0h

36 Statistics Counter RXFCSC base+4a4h

40 Statistics Counter RXMCAC base+4a8h

44 Statistics Counter RXBCAC base+4ach

48 Statistics Counter RXCFC base+4b0h

52 Statistics Counter RXPFC base+4b4h

56 Statistics Counter RXUOC base+4b8h

60 Statistics Counter RXALNC base+4bch

64 Statistics Counter RXFLRC base+4c0h

68 Statistics Counter RXCDEC base+4c4h

72 Statistics Counter RXCSEC base+4c8h

76 Statistics Counter RXUNDC base+4cch

80 Statistics Counter RXOVRC base+4d0h

84 Statistics Counter RXFRGC base+4d4h

88 Statistics Counter RXJBRC base+4d8h

92 Statistics Counter RXDRPC base+4dch

96 Statistics Counter TXBYTC base+4e0h

100 Statistics Counter TXPKTC base+4e4h

104 Statistics Counter TXMCAC base+4e8h

108 Statistics Counter TXBCAC base+4ech

112 Statistics Counter TXPFC base+4f0h

116 Statistics Counter TXTOC base+510h

120 Statistics Counter TXDRPC base+514h

124 Statistics Counter TXJBRC base+518h

128 Statistics Counter TXFCSC base+51ch

132 Statistics Counter TXCFC base+520h

136 Statistics Counter TXOVRC base+524h

On-Chip Code API


Port (Continued) 140 Statistics Counter TXUNDC base+528h

144 Statistics Counter TXFRGC base+52ch

148 Statistics Counter RXPFC_P0 base+540h



160 Statistics Counter RXPFC_P3 base+54ch




176 Statistics Counter RXPFC_P7 base+55ch

180 Statistics Counter TXPFC_P0 base+560h



192 Statistics Counter TXPFC_P3 base+56ch




208 Statistics Counter TXPFC_P7 base+57ch

212 Statistics Counter RXPFC_TR0 base+580h



224 Statistics Counter RXPFC_TR3 base+58ch




240 Statistics Counter RXPFC_TR7 base+59ch

244 Statistics Counter RxPriority0Pkts base+600h

248 Statistics Counter RxPriority0Bytes base+604h


256 Statistics Counter RxPriority1Bytes base+60ch







Table 4. Statistics Counters (Continued)

StatisticsByte


MB8AA3020


Port (Cont’d) 284 Statistics Counter RxPriority5Pkts base+628h






308 Statistics Counter FWpkts base+680h

312 Statistics Counter FLDpkts base+684h

316 Statistics Counter VLANDrops base+688h

320 Statistics Counter FULLDrops base+68ch

324 Statistics Counter STMDrops base+690h

328 Statistics Counter EDDrops base+694h

332 Statistics Counter CMDrops base+698h

336 Statistics Counter PortLearnDrops base+69ch

VLAN 0 Statistics Counter VLANunicastPkts 0 0400h ex. Monitor VLAN 0

4 Statistics Counter VLANunicastBytesL 0 0404h

8 Statistics Counter VLANunicastBytesH 0 0408h

12 Statistics Counter VLANMulticastPkts 0 040ch

16 Statistics Counter VLANMulticastBytesL 0 0410h

20 Statistics Counter VLANMulticastBytesH 0 0414h

Device 0 Statistics Counter Hostinpkts 0300h

4 Statistics Counter Hostoutpkts 0304h

8 Statistics Counter HostoutErrors 0308h

12 Learn Drop Count Register 0134h

Table 4. Statistics Counters (Continued)

StatisticsByte


On-Chip Code API


Name: Statistics Clear


Purpose: Clear Port / Priority / Flow control / VLAN / Host Statistics.

Field Description:

• P: Port Statistics which includes Priority and Flow Control statistics.

• V: VLAN Statistics Packet counts and Byte counts per VLAN (up to 32 VLANs)

• D: Device Statistics which includes Host Monitoring and Learn Drop Statistics.

• PV: Port select for Port Statistics.

• Monitored VLAN: Monitored VLAN vector for VLAN Statistics.

Statistics Clear

Name: Packet Send


Purpose: Send a Packet.

Field Description:

• Inbound Length: Value for Inbound Length Register (Status update in Reply)

• Inbound Destination: Value for Inbound Destination Register (Status update in Reply)

• Packet Data: Form DA to FCS (FCS value will be replaced by AXEL-X)

Packet Send

Note: Lower 23 bits of Inbound Length Register can be changed with this API.

Code (202 or 203)

Length (8)


0 15 16 31

reservedP PVV D

Monitored VLAN

Status

Type

Code (300 or 301)

Length (8+n for Request,


0 15 16 31

Packet Data (n)

Inbound Length

8 for Reply)

Inbound Destination

Type

Status

MB8AA3020


Name: Packet Receive


Purpose: Receive a Packet (other than Traffic Monitoring Packet).

Field Description:

• Outbound Length: Value of Outbound Length Register

• OBUF Frame Information: Value of OBUF Frame Information Register

• Packet Data: Form DA to FCS (AXEL-X checks FCS auto-matically and shows the result in Outbound Length Register)

Packet Receive

Name: Packet Receive Traffic Monitoring


Purpose: Receive a Traffic Monitoring Packet.

Field Description:

• Outbound Length: Value of Outbound Length Register

• OBUF Frame Information: Value of OBUF Frame Information Register

• Packet Data: Form DA to FCS (AXEL-X checks FCS auto-matically and shows the result in Outbound Length Register)

Packet Receive Traffic Monitoring

Code (302 or 303)



0 15 16 31

Packet Data (n)

Outbound Length

8 for Reply)

OBUF Frame Information

Type

Status

Code (304 or 305)



0 15 16 31

Packet Data (n)

Outbound Length

8 for Reply)

OBUF Frame Information

Type

Status

On-Chip Code API


Name: CM MBE


Purpose: Report MBE in CM Buffer.

Field Description:

• CM Buffer Error Log: Value of CM Buffer Error Logging Register

CM MBE

Note: AXEL-X logs a fatal error and reset chip. This message is sent after initialization.

Name: Drop Queue MBE


Purpose: Report MBE in Drop Queue.

Field Description:

• Drop Queue Error Log: Value of Request Drop Queue Error Logging Register

Drop Queue MBE


Code (500 or 501)

Length (8)


0 15 16 31

CM Buffer Error Log

Type

Status

reserved

Code (502 or 503)

Length (8)


0 15 16 31

Drop Queue Error Log

Type

Status

reserved

MB8AA3020


Name: Output Queue MBE


Purpose: Report MBE in Output Queue.

Field Description:

• Port Number: 5 bit Port number

• Output Queue Error Log: Value of Output Queue Error Logging Register

Output Queue MBE


Name: Tag MBE


Purpose: Report MBE in Tag Memory.

Field Description:

• Tag memory Error Log: Value of Tag Memory Error Logging Register

Tag Memory MBE


Code (504 or 505)

Length (8)


0 15 16 31

Output Queue Error Log

Type

Status

reserved Port

Code (506 or 507)

Length (8)


0 15 16 31

Tag Memory Error Log

Type

Status

reserved

On-Chip Code API


Name: ME Halt


Purpose: Report ME Halt by the execution of ME Halt instruction or Watch Dog Timer fault.

Field Description:

• ME Status Register: Value of ME Status Register.

• ME IRQ Wake-up 0 Register: Value of ME IRQ Wake-up 0 Register.

ME Halt


Name: Statistics Carry


Purpose: Report Carry in Statistics Counters.

Field Description:

• P: Carry in Port Statistics which includes Priority and Flow Control statistics.

• V: Carry in VLAN Statistics

• D: Carry in Device Statistics which includes Host Monitoring, Learn Drop Statistics.

• PV: Port Vector for Port Statistics Carry.

• VLAN: VLAN vector for VLAN Statistics Carry.

Statistics Carry

Notes:

• VLAN vector Bit n corresponds to Monitor VLAN n.

• This trap is a Service Required Trap.

Code (510 or 511)

Length (8)


0 15 16 31

ME IRQ Wake-up 0 Register

Type

Status

ME Status Register

Code (520 or 521)

Length (8)


0 15 16 31

Type

Status

VLAN

PVreservedP V D

MB8AA3020


Name: MAC Table MBE


Purpose: Report MBE in MAC Table.

Field Description:

MAC Table Error Log: Value of MAC Address Table Error Logging Register

MAC Table MBE

Name: VLAN Table MBE


Purpose: Report MBE in VLAN Table.

Field Description:

• VLAN Table Error Log: Value of VLAN Table Error Logging Register

VLAN Table MBE

Name: Drop Queue SBE


Purpose: Report SBE in Drop Queue.

Field Description:

• Drop Queue Error Log: Value of Request Drop Queue Error Logging Register

Drop Queue SBE

Name: SM Tag MBE


Purpose: Report MBE in Stream Memory Tag.

Field Description:

• Stream Memory MBE Status: Value of Stream Memory MBE Status Register

SM Tag MBE

Code (522 or 523)

Length (8)


0 15 16 31

MAC Table Error Log

Type

Status

reserved

Code (524 or 525)

Length (8)


0 15 16 31

VLAN Table Error Log

Type

Status

reserved

Code (526 or 527)

Length (8)


0 15 16 31

Drop Queue Error Log

Type

Status

reserved

Code (528 or 529)

Length (8)


0 15 16 31

Stream Memory MBE Status

Type

Status

reserved

On-Chip Code API


Name: SM Tag SBE


Purpose: Report SBE in Stream Memory Tag.

Field Description:

• Stream Memory SBE Status: Value of Stream Memory SBE Status Register

SM Tag SBE

Name: Output Queue SBE


Purpose: Report SBE in Output Queue.

Field Description:


• Output Queue Error Log: Value of Output Queue Error Logging Register

Output Queue SBE

Name: Tag SBE


Purpose: Report SBE in Tag Memory.

Field Description:

• Tag memory Error Log: Value of Request Tag Memory Error Logging Register

Tag SBE

Name: IBUF Tag MBE


Purpose: Report MBE in IBUF Tag.

Field Description:

• IBUF MBE Log: Value of IBUF MBE Logging Register

IBUF Tag MBE

Code (530 or 531)

Length (8)


0 15 16 31

Stream Memory SBE Status

Type

Status

reserved

Code (532 or 533)

Length (8)


0 15 16 31

Output Queue Error Log

Type

Status

reserved Port

Code (534 or 535)

Length (8)


0 15 16 31

Tag Memory Error Log

Type

Status

reserved

Code (536 or 537)

Length (8)


0 15 16 31

IBUF MBE Log

Type

Status

reserved

MB8AA3020


Name: IBUF Tag SBE


Purpose: Report SBE in IBUF Tag.

Field Description:

IBUF SBE Log: Value of IBUF SBE Logging Register

IBUF Tag SBE

Name: Port Interrupt


Purpose: Report Port Interrupt other than Link Failure.

Field Description:


• Port IRQ Status: Value of Port IRQ Status Register

Port Interrupt

Note: Port Security Trap and Link Fault Trap are Service Required Traps.

Name: Link Failure


Purpose: Report Link Failure.

Field Description:


• Port IRQ Status: Value of Port IRQ Status Register

Link Failure

Note: This is a Service Required Trap.

Name: MST MBE


Purpose: Report MBE in MST.

Field Description:

• MST Error Log: Value of MST Error Logging Register

MST MBE

Code (538 or 539)

Length (8)


0 15 16 31

IBUF SBE Log

Type

Status

reserved

Code (540 or 541)

Length (8)


0 15 16 31

Port IRQ Status

Type

Status

reserved Port

Code (542 or 543)

Length (8)


0 15 16 31

Port IRQ Status

Type

Status

reserved Port

Code (544 or 545)

Length (8)


0 15 16 31

MST Error Log

Type

Status

reserved

On-Chip Code API


Name: MST SBE


Purpose: Report SBE in MST.

Field Description:

• MST Error Log: Value of MST Error Logging Register

MST SBE

Name: MAC Table SBE


Purpose: Report SBE in MAC Table.

Field Description:

• MAC Table Error Log: Value of MAC Address Table Error Logging Register

MAC Table SBE

Name: VLAN Table SBE


Purpose: Report SBE in VLAN Table.

Field Description:

• VLAN Table Error Log: Value of VLAN Table Error Logging Register

VLAN Table SBE

Name: CM SBE


Purpose: Report SBE in CM Buffer.

Field Description:

• CM Buffer Error Log: Value of CM Buffer Error Logging Register

CM SBE

Code (546 or 547)

Length (8)


0 15 16 31

MST Error Log

Type

Status

reserved

Code (548 or 549)

Length (8)


0 15 16 31

MAC Table Error Log

Type

Status

reserved

Code (550 or 551)

Length (8)


0 15 16 31

VLAN Table Error Log

Type

Status

reserved

Code (552 or 553)

Length (8)


0 15 16 31

CM Buffer Error Log

Type

Status

reserved

MB8AA3020


Name: Output Queue Status


Purpose: Report Output Queue Status.

Field Description:

• Output Queue Status: Value of Output Queue Status Register

Output Queue Status

Note: This is a Service Required Trap.

Name: Traffic Monitoring Get


Purpose: Get the traffic monitoring configuration.

Field Description:

• Enable Vector: 24 bit Enable Vector, 0 Disable, 1 Enable

• Random Polynomial Function: 32 bit Random Polynomial Function (filled in Reply)

• Random Seed: 32 bit Random Seed (filled in Reply)

• Recovery Timer: 16 bit Recovery Timer (filled in Reply)

Traffic Monitoring Get

Note: When multiple bit is set in the Enable Vector, the lowest significant bit is used to report the parameters.

Code (570 or 571)

Length (8)


0 15 16 31

Output Queue Status

Type

Status

reserved

Code (800 or 801)

Length (16)


Reserved

0 15 16 31

Type

Status

Enable Vector

Random Polynomial Function

Random Seed

Reserved Recovery Timer

On-Chip Code API


Name: Traffic Monitoring Set


Purpose: Set the traffic monitoring configuration.

Field Description:


• Random Polynomial Function: 32 bit Random Polynomial Function

• Random Seed: 32 bit Random Seed

• Recovery Timer: 16 bit Recovery Timer

Traffic Monitoring Set

Note: Multiple ports can be set simultaneously by setting multiple bits in the Enable Vector.

Code (802 or 803)

Length (16)


Reserved

0 15 16 31

Type

Status

Enable Vector

Random Polynomial Function

Random Seed

Reserved Recovery Timer

MB8AA3020


Name: Congestion Notification Get


Purpose: Get the congestion notification configuration.

Field Description:


• Output Queue Threshold: 32 bit Output Queue Threshold (filled in Reply)

• BCN Payload Size: 16 bit BCN Payload Size (filled in Reply)

• BCN Interval: 16 bit BCN Interval (filled in Reply)

• BCN Redirection/Mirror Vector: 24 bit BCN Redirection/Mirror Vector (filled in Reply)

• BCN DA[0:3]: 32bit BCN DA[0:3] (filled in Reply)

• BCN DA[4:5]: 16bit BCN DA[4:5] (filled in Reply)

• BCN SA[0:1]: 16bit BCN SA[0:1] (filled in Reply)

• BCN SA[2:5]: 32bit BCN SA[2:5] (filled in Reply)

• BCN Ethertype: 16 bit BCN Ethertype (filled in Reply)

• BCN Version: 16bit BCN Version (filled in Reply)

• BCN Priority: 3 bit BCN Priority (filled in Reply)

• BCN Option: 16 bit BCN Option (filled in Reply)

• BCN Global Chip ID: 8 bit BCN Global Chip ID (filled in Reply)

Congestion Notification Get

Note: When multiple bit is set in the Enable Vector, the lowest significant bit is used to report the parameters.

Code (810 or 811)

Length (40)


Enable Vector

0 15 16 31

Type

Status

Output Queue Threshold

BCN Payload Size BCN Interval

BCN Redirection / Mirror Vector

BCN DA[0:3]

BCN DA[4:5] BCN SA[0:1]

BCN GlobalChip ID Reserved

Reserved

Reserved

BCN SA[2:5]

BCNPriority

BCN Ethertype BCN Version

BCN OptionReserved

On-Chip Code API


Name: Congestion Notification Set


Purpose: Set the congestion notification configuration.

Field Description:


• Output Queue Threshold: 32 bit Output Queue Threshold

• BCN Payload Size: 16 bit BCN Payload Size

• BCN Interval: 16 bit BCN Interval

• BCN Redirection/Mirror Vector: 24 bit BCN Redirection/Mirror Vector

• BCN DA[0:3]: 32bit BCN DA[0:3]

• BCN DA[4:5]: 16bit BCN DA[4:5]

• BCN SA[0:1]: 16bit BCN SA[0:1]

• BCN SA[2:5]: 32bit BCN SA[2:5]

• BCN Ethertype: 16 bit BCN Ethertype

• BCN Version: 16bit BCN Version

• BCN Priority: 3 bit BCN Priority

• BCN Option: 16 bit BCN Option

• BCN Global Chip ID: 8 bit BCN Global Chip ID

Congestion Notification Set

Note: Multiple ports can be set simultaneously by setting multiple bits in the Enable Vector.

Code (812 or 813)

Length (40)


Enable Vector

0 15 16 31

Type

Status

Output Queue Threshold

BCN Payload Size BCN Interval

BCN Redirection / Mirror Vector

BCN DA[0:3]

BCN DA[4:5] BCN SA[0:1]

BCN GlobalChip ID Reserved

Reserved

Reserved

BCN SA[2:5]

BCNPriority

BCN Ethertype BCN Version

BCN OptionReserved

MB8AA3020


Name: Configure 10G Port


Purpose: Configure one 10G Port.

Field Description:

• Port Number: 0 to 19 (10G port number)

• Port Operation: 0 Disable 10G Port, 1 Enable 10G Port

Configure 10G Port

Name: Ping


Purpose: Ping.

Field Description:

Ping

Notes:

• This message is excluded from the sequence check in AXEL-X and the expecting sequence number is not incremented.

• AXEL-X sends Ping back to the source station using Inbound Destination Function.

Name: Sync


Purpose: Synchronization Protocol.

Field Description:

Sync

Notes:

• AXEL-X keeps track of sequence to secure protocol. For example, Register Set is not done when the sequence number for the Identifier skips.

• When the sequence error occurs, non zero value is returned in the Status field.

• With the reception of this message, AXEL-X resets the sequence tracking and initialize the expecting sequence number with a value given in the Sequence Number field and increment it. Therefore Host should send a first request message with sequence number 1 when the Sequence Number field of Sync is 0.

• After Sync is received, AXEL-X initialize the sending sequence number for the requests (Trap or Packet Receive). Therefor AXEL-X sends a first request with sequence number 0 when the Sequence Number field of Sync is 0. Host is not required to check the sequence number.

• On-Chip Code uses this Identifier in the Packet Receive and Trap messages.

Code (900 or 901)

Length (4)


Port Number

0 15 16 31

Type

Status

Port Operation

Code (0 or 1)

Length (0)


0 15 16 31

Type

Status

Code (2 or 3)

Length (0)

Identifier Sequence Number (0)

0 15 16 31

Type

Status

On-Chip Code API


Name: Restart

Code: 4 (Request)

Purpose: Restart by resetting chip.

Field Description:

• S: Sticky Clear. 0 = not clear sticky information. 1 = clear sticky information.

Restart

Note: No Reply message is returned. Therefore Host needs to send Ping message to check the completion of the initialization.

Code (4)

Length (4)


0 15 16 31

Type

Status

Sreserved

MB8AA3020


Appendix A.A.1 RAW EthernetTwo Linux hosts can communicates each other on the Ethernet layer using RAW socket (AF_PACKET with SOCK_RAW). From the programmer’s point of view, it is similar to UDP. The differences are:

• The parameters for the function used to create a socket

• Instead of IP addresses, MAC addresses are used

• The data link header needs to be created manually

Figure 4: Ethernet Frame (IEEE 802.3)

DestMAC SrcMAC TypeTCP / UDP

User DataData Link Header CRC

FCS

(14 octets) (46 - 1500 octets) (4 octets)

(6 octets) (6 octets) (2 octets) (4 octets)

IP

Ethernet

Physical

Confidential

FUJITSU MICROELECTRONICS AMERICA, INC.Corporate Headquarters1250 East Arques Avenue, M/S 333, Sunnyvale, California 94085-5401Tel: (800) 866-8608 Fax: (408) 737-5999E-mail: [email protected] Web Site: http://us.fujitsu.com/micro

©2006 Fujitsu Microelectronics America, Inc. All rights reserved.

All company and product names are trademarks or registered trademarks of their respective owners.

Printed in U.S.A. 10GE-RM-21250-6/2007

20-port, 10GbE Switch Chip On-Chip Code API

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