2 VLSI Design

8/8/2019 2 VLSI Design

1/35

VLSI Design


2/35

VLSI DesignVLSI Design


3/35

Integrated CircuitsIntegrated Circuits

Numb er of applications needs Integratedcirc u its s u ch as :

High perfor m ance co m pu ting.Teleco mmu nications.

Cons um er Electronics.

First transistor First IC


4/35

For infor m ation services there are i m portantcharacteristics that mu st b e achieved

Increasing need for very high processing power and b andwidth (i.e. to handle real-ti m e video).

N eed for m ore personalized (which m eansdevices b e m ore intelligent to answer individ u alde m ands & mu st b e porta b le to allow m oreflexib ility/m ob ility)

Why do we need Integration?Why do we need Integration?


5/35

To achieve the previo u s characteristics m ore &m ore co m plex f u nctions are req u ired.

SOSO ,the need to integrate these f u nctions in as m all syste m /package is also increasing .

Why do we need Integration? (Cont.)Why do we need Integration? (Cont.)


6/35

Levels of integrationLevels of integration

Level of integration is m eas u red b y the N o. of logic gates in a chip.

SSI (2-20 gate)

MSI (20-200 gate)

LSI (200-2000 gate)

VLSI (2000-500,000 gate)

ULSI (500,000-10,000,000 gate)

1964

1967

1972

1978

1989


7/35

Integration ProvidesIntegration Provides

Less area/vol um e

Less power cons um ption

Higher speed

Significant cost saving

Less testing req u ire m ents as syste m level

Higher relia b ility (du e to i m proved interconnections)


8/35

T rend of integrationT rend of integration

In early 1980s m inimum feat u re size of 0.3 m expectedaro u nd year 2000.

Bu t the act u al develop m ent was m inimum length of 0.25 m was reached b y year 1994.

Numb er of co m ponents per chip increase year b y year.

Minimum feat u re size( transistor length or interconnectlength) decrease year b y year.


9/35

M oores LawM oores Law

The n umb er of transistors that can b e integrated on asingle IC grows exponentially with ti m e.

Feat u re size has shr u nk b y 0.7 ti m es every 3 years.

Intels Gordon Moore in early 80s predicted thatthis trend wo u ld contin u e

Cost of printing process has grown m odestly

Th u s, cost per f u nction has dropped exponentially

No. of transistors do

uble every 3 years( recently 2.3 years)


10/35

M oores Law (Cont.)M oores Law (Cont.)

Cost of m an u fact u ring ICs have re m ained flat bu tdesign cost has not

At each new generations, each gate cost a b ou t 1/ 2what it did 3 years a go.


11/35


12/35

Tec h nologiesTec h nologies

Bipolar (BJT)TTL, Schottky

ECL

Du al J u nction, c u rrent controlled devicesN MOS,PMOS

CMOSSingle J u nction voltage controlled devices

GaAs (typically JFETs)


13/35

Why CM OS Tec h nolog y ?Why CM OS Tec h nolog y ?

Sim ple (low cost)

Sm all area and low power(High Density)

Wafer size: 8 inch

chip size: 1.5 X 1.5 c m


14/35

Wh at Are On ICs?Wh at Are On ICs?

Cond u cting layers which for m wires

Many layers of wires (4-5 m etal layers) which has

electrical properties su

ch as resistance andcapacitance

Contacts and ins u lators b etween layers

Transistors (free things that fit u nder the wires)


15/35

VLSI DesignVLSI Design

Major steps

specification;architect u re;

logic design;

circu it design ;

layou t (physical design). ).


16/35

s ystem specification

Functional

(arc h itecture) Design

Functional verification

Logic Design

Logic Verification

Circuit Design

Circuit Verification

P hy sical Design

La yout Verification

Layo u tRepresentation

Circ u it

Representation

Logic(gate-Level)Representation

BehavioralRepresentation

Transistors

gates+ registers

Device


17/35

Design complexit yDesign complexit y

Regardless of the size of the project, red u cing theco m plexity of IC i m prove the prospects of s u ccess.

Som e Classical techniq u es of red u cing the co m plexityare:

Hierarchy

Regu larity

Modu larity

Locality


18/35

1 . Design Hierarc hy1 . Design Hierarc hy

Its dividing a m od u le into s ub -m od u les and thenrepeating this operation on the s ub -m od u les u ntil theco m plexity of s m aller parts b eco m es m anagea b le.

In the physical do m ain when getting the f u nctionalb locks, this will provide a val u a b le g u idance of the

act u al realization on chip (approxi m ate size & shape).


19/35

add4

add addaddadd

carry s umcarry s ums umcarrys umcarry

or and and and andor or or


20/35

2 . Regularit y2 . Regularit y

Means that the hierarchical deco m position is not onlysim ple bu t also similar b locks.

Extendedu

se of regu

larity sim

plifies the design process

Regu larity can exist at all levels of design hierarchy

Transistor level : u nifor m sized transistors si m plifies the design

Logic Level :identical gate str u ctu res can b e u sed


21/35

3 . M odularit y3 . M odularit yVario u s b locks which m ake u p larger syste m mu st havewell-defined functions and interfaces.

Each b lock or m od u le can b e designed relativelyindependent since theres no ambiguit y a b ou t thef u nction and interface of these b locks

All of the b locks can b e co mb ined at the end of thedesign process to for m a larger syste m .


22/35


23/35

VLSI Design St ylesVLSI Design St yles

Fu ll Cu sto m Mask Design

Standard Cell Design

Gate Arrays

Progra mm a b le Logic

DesignInvest m entIncreasing (for a givenapplication)


24/35

1 . Full custom design1 . Full custom design

Designers hand draws geo m etries which specifytransistors and other devices for an integratedcirc u it (transistor/circ u it level).

Sm allest die area (high transistors density)

Very high developm

ent cost.

Design ti m e can b e very long and so fa b rication ti m e(at least 6-8 weeks).


25/35

Mem ory chips are the m ost pop u lar designs done with

f u ll cu sto m designs.

The first c u sto m chip cost is very high bu t each oneafter is mu ch cheaper so high vol um e prod u cts isdesigned ( m e m ory chips, m icro-processors).

Mask layo u t of Penti um IIm icro-processor


26/35

2 . Standard Cell Design2 . Standard Cell Design

Alm ost like the f u ll cu sto m design bu t co mm only u sedlogic cells are developed ,characterized and stored instandard cell li b rary.

Standardization is achieved at the logic or f u nction level(transistor).

Exam

ple on standard cell contents :SSI logic: nand, nor, xor, inverters, bu ffers, latches, registers.MSI logic: decoders, encoders, adders, co m parators

Mem ories: RAM, ROM


27/35

To ena b le a u tom ated place m ent and ro u ting of inter-cellconnections , each cell layo u t has fixed height so cellscan b e a bu tted side- b y-side.

Standard cell row

Standard cell


28/35

3 .3 . Gate arra ysGate arra ys

The design is m apped onto an array of transistorswhich is already created on a wafer

GA im ple m entation req u ire two-step m an u fact u ring :

Array of u nco mm itted transistors on the GA chip(m an u fact u re)

Defining the m etal interconnects b etween thetransistors of array( u ser)


29/35

Unco mm ittedcell

Co mm itted cell4-inp u t (N OR)


30/35

4 . FPGA4 . FPGAWhat does 'Field Programmable' mean?What does 'Field Programmable' mean?

A typical integrated circuit (IC ) performs a particularfunction defined at the time of manufacture .

A program written by someone other than the devicemanufacturer defines the FPGAs function .

Depending on the particular device, the program is:

- 'burned as part of a board assembly process

- loaded from an external memory each time thedevice is powered up


31/35

Fo u r m ain categories of FPGA c u rrently availa b le :

Sy mm etric array Row- b ased

H ierarchical PLDSea-of-gates

Logicb lock

interconnections

Logicb lock

interconnections


32/35

Cu rrently there are fo u r technologies in u se :

Static RAM cells

Anti-Fu se

EPROM/EEPROM transistors

Connection are m ade u sing transistors,trans m ission gates or mu ltiplexers controlledb y SRAM cells (deter m ine logic f u nctions & interconnections).

Resides in high-i m pedance state,or can b e progra mm ed into low-i m pedance (f u sed)

Sa m e m ethod as EPROM m e m ories.


33/35

The FPGA has 3 config u ra b le ele m ents :

Configu ra b le Logic Block (CLB)Inpu t/O u tpu t Block (IOB)

Interconnections


34/35

CLBCLB

Provides the f u nctional ele m ents for constr u cting u sers logic.

May b e physically i m ple m ented u sing LUT, mu ltiplexers andgates.

IOBIOB

Provides the interface b etween the package pins and internalsignal lines.


35/35

Programmable interconnectionsProgrammable interconnections

Provide ro u ting paths to connect the inp u ts and o u tpu ts of CLBand IOB .

Com posed of m etal seg m ents with progra mm a b le switching

points to im

plem

ent the desired rou

ting

2 VLSI Design

Documents

Transcript of 2 VLSI Design