2 Universal Gate

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DIGITAL ELECTRONICS (331102) 9 | Page SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT)) PRACTICAL: 02 REALIZING NAND AND NOR GATE AS UNIVERSAL GATE LOGIC 1.0 OBJECTIVES Universal Gates : NAND and NOR gates How to implement AND, OR and NOT gate using NAND Gate. How to implement AND, OR and NOT gate using NOR Gate. Equivalent Gates 2.0 ‘NAND’ GATE NAND is the contraction of AND NOT gates. It has two or more inputs and only one output i.e. Y = A · B. When all the inputs are HIGH, the output is LOW. If any one or both the inputs are LOW, then the output is HIGH. The Logic symbol and the truth table of NAND gate is as shown here. The small circle (or bubble) represents the operation of inversion. The NAND gate is equivalent to an OR gate with the bubble at its inputs which are as shown.

description

study of universal gates in digital electronics

Transcript of 2 Universal Gate

Page 1: 2 Universal Gate

DIGITAL ELECTRONICS (331102)

9 | P a g e SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))

PRACTICAL: 02

REALIZING NAND AND NOR GATE AS UNIVERSAL

GATE LOGIC

1.0 OBJECTIVES

Universal Gates : NAND and NOR gates

How to implement AND, OR and NOT gate using NAND Gate.

How to implement AND, OR and NOT gate using NOR Gate.

Equivalent Gates

2.0 ‘NAND’ GATE

NAND is the contraction of AND – NOT

gates.

It has two or more inputs and only one

output i.e. Y = A · B.

When all the inputs are HIGH, the output

is LOW. If any one or both the inputs are

LOW, then the output is HIGH.

The Logic symbol and the truth table of

NAND gate is as shown here.

The small circle (or bubble) represents the operation of inversion.

The NAND gate is equivalent to an OR gate with the bubble at its inputs which are

as shown.

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DIGITAL ELECTRONICS (331102)

10 | P a g e SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))

3.0 ‘NOR’ GATE

NOR is the contraction of OR – NOT gates.

It has two or more inputs and only

one output i.e. Y = A + B.

When all the inputs are LOW, the

output is HIGH. If any one or both

the inputs are HIGH, then the

output is LOW.

The Logic symbol and the truth

table of NOR gate is as shown

here.

The small circle (or bubble)

represents the operation of inversion.

The NOR gate is equivalent to an AND gate with the bubble at its inputs which are

as shown.

4.0 UNIVERSAL GATES :

A universal gate is a gate which can implement any Boolean function without

need to use any other gate type.

The NAND and NOR gates are universal gates.

In practice, this is advantageous since NAND and NOR gates are economical and

easier to fabricate and are the basic gates used in all IC digital logic families.

In fact, an AND gate is typically implemented as a NAND gate followed by an

inverter not the other way around!!

Likewise, an OR gate is typically implemented as a NOR gate followed by an

inverter not the other way around!!

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DIGITAL ELECTRONICS (331102)

11 | P a g e SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))

5.0 NAND GATE AS A UNIVERSAL GATE :

To prove that any Boolean function can be implemented using only NAND gates,

we will show that the AND, OR, and NOT operations can be performed using only

these gates.

IMPLEMENTING INVERTER USING NAND GATE :

The figure shows two ways in which a NAND gate can be used as an

inverter (NOT gate).

1. All NAND input pins connect

to the input signal A gives an

output A’.

2. One NAND input pin is

connected to the input signal

A while all other input pins

are connected to logic 1. The

output will be A’.

IMPLEMENTING AND USING NAND GATE :

An AND gate can be replaced

by NAND gates as shown in

the figure (The AND is replaced

by a NAND gate with its output

complemented by a NAND gate inverter).

IMPLEMENTING OR USING NAND GATE :

An OR gate can be replaced by

NAND gates as shown in the

figure (The OR gate is replaced by

a NAND gate with all its inputs

complemented by NAND gate

inverters).

Thus, the NAND gate is a universal gate since it can implement the AND,

OR and NOT functions.

6.0 NOR GATE AS A UNIVERSAL GATE :

To prove that any Boolean function can be implemented using only NOR gates,

we will show that the AND, OR, and NOT operations can be performed using only

these gates.

IMPLEMENTING INVERTER USING NOR GATE :

The figure shows two ways in

which a NOR gate can be used

as an inverter (NOT gate).

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DIGITAL ELECTRONICS (331102)

12 | P a g e SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))

All NOR input pins connect to the input signal A gives an output A’.

One NOR input pin is connected

to the input signal A while all

other input pins are connected

to logic 0. The output will be A’.

IMPLEMENTING OR USING NOR GATE :

An OR gate can be replaced by

NOR gates as shown in the

figure (The OR is replaced by a

NOR gate with its output

complemented by a NOR gate inverter)

IMPLEMENTING AND USING NOR GATE :

An AND gate can be replaced by

NOR gates as shown in the

figure (The AND gate is replaced

by a NOR gate with all its inputs

complemented by NOR gate

inverters)

7.0 EQUIVALENT GATES :

The shown figure summarizes important cases of gate equivalence. Note that

bubbles indicate a complement operation (inverter).

A NAND gate is equivalent to

an inverted-input OR gate.

An AND gate is equivalent to an

inverted-input NOR gate.

A NOR gate is equivalent to an

inverted-input AND gate.

An OR gate is equivalent to an

inverted-input NAND gate.

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DIGITAL ELECTRONICS (331102)

13 | P a g e SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))

Two NOT gates in series are same

as a buffer because they cancel

each other as A’’ = A.

8.0 EXERCISE

8.1 Can we construct Ex-OR gate using a NAND gate?

8.2 Can we construct Ex-NOR gate using a NOR gate?

8.3 Which law can be applied to construct the Universal Gate.

9.0 ASSIGNMENTS

9.1 Why NAND & NOR gates are called universal gates???

9.2 What is meant by universal logic gate?

9.3 Construct Ex-OR gate using NOR gate.

9.4 Construct Ex-NOR gate using NAND gate.

Grades for Exercise: .................................................

Grades for Assignment: .................................................

Signature of Lab Co-ordinators: .................................................