2. MOS: Transfer Function, Bias, and Small Signal Model

ECE 102, Winter 2011, F. Najmabadi

Reading: Sedra & Smith: Secs. 5.4 & 5.5(Also see Sec. 4.3.7)

NMOS Characteristic Equations

For PMOS: vGS→ vSG, vDS→ vSD, vtn→ |vtp|, k’n→ k’p, and iD flowing OUT of the drain

PMOS

NMOS Transfer Function

For vGS < Vtn , NMOS is in cutoff:

NMOS Transfer Function

o For vGS > Vtn as vGS ↑ → iD ↑ → vDS ↓

o (NMOS in saturation as we started with vDS = VDD > vGS – Vtn )

o iD and vDS can be found from

NMOS Transfer Function

o As vGS increases vDS becomes smaller until at point B where vDS = vGS – Vtn .

o For larger vGS NMOS is in triode

Exercise: Find VGS|B and VDS|B

NMOS Transfer Function

A combination of constant VGS and a signal (vgs)

Bias Bias

A combination of constant VGS and a signal (vgs)

Bias

Bias and signal

Bias and signal

Response to the signal appears to be linear!

Bias and signal

A linear transfer function for the Signal!

vgs

vds

vGS = VGS + vgs

vDS = VDS + vds

iD = IDS + id

Signal and response

Bias

An Analogy

Total Height, Hb = Bias (HB) + response to signal (hb) Complicated correlation between total height, Hb , and weight

of the boat. Simple correlation between hb and added weight

Hb = HB

Boat

Pool

Bias

Added Weight(signal)

HbHB

Bias + signal

hb

Response

Bias: HB

Bias + Signal: Hb

Signal & response to signal: hb

Bias: VGS , VDS , ID , VRD

Bias + Signal: vGS , vDS , iD , vRD Signal &

response to signal: vgs , vds , id , vrd

Added Weight(signal)

Hb

HB

Bias + signal

hb

Non-linear correlations among Bias + Signal: vGS , vDS , iD , vRD Simple (and linear) correlation between signal and response to the

signal: vgs , vds , id , vrd

Important Points!

Signal: We want the response of the circuit to this input.

Bias: State of the system when there is no signal (current and voltages in all elements).o Bias is constant in time (may vary extremely slowly compared to

signal)o Purpose of the bias is to ensure that MOS is in saturation at all times.

Response of the circuit and elements within to the signal is different that the response of the circuit and its elements to Bias (or to Bias + signal):o Different transfer function for the circuito Different iv characteristics for the elements, i.e. relationships among

vgs , vds , id is different than relationships among vGS , vDS , iD .

Limitations and Constraints

Floating Boat analogy Boat should float at all

times!o Sufficient water in the pool

o Cannot put too much weight (depends on the depth of the water!)

Transistor MOS should be in saturation

at all times!o Bias point in Saturation*

o Signal amplitude cannot become too large (depends on Bias point!)*

* Equations are for NMOS!

VGS > VtnVDS > VGS - Vtn

vGS = VGS + vgs > VtnvDS = VDS + vds > VGS + vgs- Vtn

Procedure:

1. How to establish a Bias point (bias is the state of the system when there is no signal).o Stable and robust bias point should be resilient to variations in k’,

Vt , … due to temperature and/or manufacturing variability.

2. Find the iv characteristics of the elements for the signal (which can be different than their characteristics equation for bias). o This will lead to different circuit configurations for bias versus

signal

3. Compute circuit response to the signalo Focus on fundamental MOS amplifier configurations

BIAS(Ensure that MOS is in saturation at all times,

Important parameters are ID and VDS )

Bias with Gate Voltage

ID = 0.5 k’n (W/L) (VGS – Vtn)2

VDS = VDD – RD ID

This method is NOT desirable as k’, Vt , … are not “well-defined” as bias point (i.e., ID and VDS) can change due to temperature and/or manufacturing variability.o See Exercise 5.33

Bias with Source Degeneration

Resistor Rs provides negative feedback

Basic Arrangement

VGS = VG – RS ID

Bias with one power supply

VGS = VG – RS ID

Bias with two power supplies

VGS = VSS – RS ID

(KVL: 0+ VGS + RS ID – VSS = 0)

Resistor Rs provides negative feedback

VGS = VG – RS ID

ID = IS = 0.5 k’n (W/L) (VGS – Vtn)2

o If ID ↑ (because k’n ↑ or Vtn ↓ ) VGS ↓ ID ↓

o If ID ↓ (because k’n ↓ or Vtn ↑ ) VGS ↑ ID ↑

ID Eq.VGS Eq.

VGS Eq. ID Eq.

Negative Feedback:

Feedback is most effective if RS ID >> VGS as

0 = – VGS + VG – RS ID ≈ VG – RS ID or ID ≈ VG /RS

Basic Arrangement

Example: Find Bias point for Vt =1 V, k’ W/L = 1 mA/V2

GS-KVL: VG = VGS + RS ID

ID = 0.5 k’n (W/L) (VGS – Vtn)2

7 = VGS + 5 (VGS – 1)2

VGS = 2 V , VS = VG – VGS = 5 V

VG = (7)/(7+8) X 15 = 7 V

DS-KVL: 15 = VDS + (RS + RS )ID

VDS = 5 V , VD = VS + VDS = 10 V

Impact of RS: if Vt = 1.5 V (50% change), ID = 0.455mA (9% change)

VD = 10 V

VS = 5 V

VG = 7 V

Bias in ICs Resistors take too much space on the chip

A “robust” bias has ID and VDS that do not change. One can force ID to be constant using a current source.

VG = 0

ID = I

VGS is set by

I = ID = 0.5 k’n (W/L) (VGS – Vtn)2

VDS = VD – VS

VD = VDD – RD ID

VS = VG – VGS = – VGS

Current Mirrors (or Current Steering Circuits)

Identical MOS:Same k’n and Vt

Circuit works as long as Q2 is in saturationVDS2 > VGS - Vt

Q1 is always in saturationVDS1 = VGS > VGS - Vt

Since VGS1 = VGS2 = VGS :

An implementation of a Current Mirror

Identical MOS:Same k’n and Vt

Circuit works as long as Q2 is in saturationVDS2 > VGS - Vt

Bias point of Q1 is uniquely set by:

Since VGS1 = VGS2 = VGS :

Examples of Current Steering circuits

Current steering circuit can bias several transistors A PMOS current mirror

An implementation of current steering circuit to bias several transistors in an IC

SMALL SIGNAL MODEL

2. Find the iv characteristics of the elements for the signal (which can be different than their characteristics equation for bias).

This will lead to different circuit configurations for bias versus signal

Bias and signal

RD: VRDIRD = ID

MOS: VGS, ID, VDS

VDD: VDD

RD: vRD = VRD + vrdiRD = iD = ID + id

MOS: vGS = VGS + vgsvDS = VDS + vds

iD = ID + id

VDD: VDD

“Signal-only” circuit is different!Bias

Signal only

RD: vrdird = id

MOS: vgs, id, vds

No signal here!

Signal Model for linear circuit elements Independent voltage source (e.g., VDD)

o No signal: effectively grounded

Independent current sourceo No signal: effectively open circuit (Careful about current mirrors as they

are NOT “ideal” current sources, channel width modulation was ignored!)

Resistors, capacitors, inductoro Remain the same:

Dependent sourceso Remain the same with the control parameter related to the signal!

Non-linear Elements: o Different!

iR = IR + irvR = VR + vr = RIR + vrvR = R iR = R (IR + ir ) = RIR + R irvR = RIR + vr = RIR + R irvr = R ir

Diodes: signal response is non linear but can be linearized when signal is small

vD

iD

VD

ID

vd

id?

vd

id R = nVT/ID

Formal derivation of small signal model

f(∙)aAA xXx += aAA yYy +=

)( AA xfy =

( ) ( ) ...!2

)()()( 2)2(

)1( +−⋅+−⋅+= AAA

AAAA XxXfXxXfXf

...!2

)()()( 2)2(

)1( +⋅+⋅+= aA

aAA xXfxXfXf

aAA xXfXf ⋅+≈ )()( )1(

)( AA XfY =

f(∙)AX AY

g(∙)Ax Ay

2)2(

)1(

!2)()( a

AaA xXfxXf ⋅>>⋅

)()(2 )2(

)1(

A

Aa Xf

Xfx ⋅<<

Small signal means:

aAaa xXfxgy ⋅== )()( )1(

Derivation of diode small signal model

−⋅= 1T

DnVv

SD eIi

−⋅= 1)( TnV

x

S eIxf

−⋅== 1)( T

DnVV

SDD eIVfI

dT

SDd

T

nVV

Sd

VxT

nVx

SdDd v

nVIIv

nVeIv

nVeIvVfi

T

D

D

T

⋅

+=⋅

⋅

=⋅

⋅

=⋅=

=

)()1(

dT

Dd

T

SDd v

nVI

vnV

IIi ⋅

≈⋅

+=

vd

id R = nVT/ID

D

dd r

vi =D

TD I

nVr ≈

Derivation of MOS small signal model

f(∙, ∙)Ax

AzAy

f(∙, ∙)AX

AZAY

aAA xXx +=

aAA yYy +=

),( AAA yxfz =

),( AAA yxfz =

...)(),()(),(),(,,

+−⋅∂

∂+−⋅

∂∂

+= AAYX

AAYX

AA Yyy

yxfXxx

yxfYXfAAAA

aYX

aYX

A yy

yxfxx

yxfZAAAA

⋅∂

∂+⋅

∂∂

+≈,,

),(),(

aYX

aYX

a yyfx

xfz

AAAA

⋅∂∂

+⋅∂∂

=,,

),( AAA YXfZ =

AAa Zzz −=

Derivation of MOS small signal model

iG = 0iD = 0.5 k’n (W/L) (vGS – Vtn)2 (1 + λ vDS) = f (vGS , vDS)iD = f (x, y) with x ↔vGS and y ↔ vDS

dsVV

gsVV

d vyfv

xfi

DSGSDSGS

⋅∂∂

+⋅∂∂

=,,

Do I

r⋅

=λ

1tnGS

Dm VV

Ig−⋅

=2

For λ vDS << 10=

+⋅=

g

o

dsgsmd

irvvgi

MOS “circuit” small signal model0 and =+⋅= g

o

dsgsmd i

rvvgi

PMOS circuit model for small signals is identical to NMOS in gm formula replace VGS – Vtn with VSG - |Vtp|

Do I

r⋅

=λ

1

tnGS

Dm VV

Ig−⋅

=2

1)(

2>>

−=

tnGSom VV

rgλ

id

PMOS “circuit” small signal model is identical to NMOS

0 and =+⋅= go

sdsgmd i

rvvgi

For PMOS small signal model, id flows into the drain

Do I

r⋅

=λ

1

tpSG

Dm VV

Ig−⋅

=2

id

vsg gmvsg

id

=