2. COMPUTER and MICROPROCESSOR ARCHITECTUREyildiz.edu.tr/~sedef/verdigi dersler_files/Memories and...

1

2.1 General Computer Architecture

Computer is a machine that can receive, transmit, store, andmanipulate information.

A computer consists of:

1) Central unit2) Memory unit3) Input/Output unit4) Buses 5) Address decoding unit

Figure 2-1 depicts the typical basic block diagram for almost all busoriented digital computer system.

2. COMPUTER and MICROPROCESSOR

ARCHITECTURE

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COMPUTER and MICROPROCESSOR

ARCHITECTURE

CPU

or

MPU

RAM

ROM

PIA, ACIA

Peripheral Interfaces

Peripheral

Devices

Address Bus (output)

Data Bus (Input/Output)

Control Bus (output)

Displays

Keyboards

Printers

Scanners

Disk drives

ADC/DAC

Central Unit Input/Output Unit Memory Unit

Address

Decoder

: Chip Select, low active input

CS CS

ROM

CS CS

CS

Address

Decoding Unit

PIA: Peripheral Interface Adapter, is used for parallel data transfer

ACIA: Asynchronous Communication Interface Adapter is used for

serial data transfer

RAM: Random Access Memory, is used for data storage, volatile memory

ROM: Read Only Memory, is used for program storage, nonvolatile memory

Y0

Y1

Y2

Parallel or Serial

Communication

Figure 2-1 The basic block diagram of a digital computer system

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ARCHITECTURE

1) Central Unit

The central unit (CPU/MPU) controls the flow of information betweenitself and the memory or input/output equipment.

2) Memory Unit

The memory unit in a computer system stores the data and instructionsof the programs.

The memory devices directly accessible by the CPU/MPUconsist of semiconductor Integrated Circuits (ICs) called

RAM (Random Access Memory) and

ROM (Read Only Memory).

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ARCHITECTURE

There are two features that distinguish RAM and ROM:

1. RAM is read/write memory

while

ROM is read-only memory;

and

2. RAM is volatile, (the contents are lost when power is removed)

while

ROM is nonvolatile(the contents are not lost whenpower is removed).

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ARCHITECTURE

3) Input/Output Unit (I/O)

The main purpose of the input/output unit is to allow themicroprocessor to communicate directly with people or with anothercomputer or machine.

The most familiar types of I/O equipment are,

a) input units: switches, keyboard, mouse, scanner, sensors,

microphone, photosensitive device.

b) output units: LEDs, LED display, video display, CRT, LCD, relays, solenoids, printer, speakers, motors.

c) input/output units: disk drives, tape drives, USB-flash disk.

Typical microprocessor I/O equipment includes: 1. Analog-to-Digital Converter (ADC),2. Digital-to-Analog Converter (DAC).

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ARCHITECTURE

4) Buses

A bus is a collection of wires.

The busses carry address, data, and control information between thevarious unit.

The bus consist of three parts:

a) Address Bus (output)

b) Data Bus (input/output)

c) Control Bus (output)

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ARCHITECTURE

• All bus-oriented digital computer systems use the same three buses toprocess information.

• The size of a bus, known as its width, is important because itdetermines how much information can be transmitted at one time.

For example,a 8-bit data bus can transmit 8 bits of data, whereasa 16-bit address bus can transmit 16 bits of address.

• Every bus has a clock speed measured in MHz.

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ARCHITECTURE

a) Address Bus

• The address bus points to the location of the information.

• Address buses are present and basically the same in allmicroprocessors. They are incorporated into the system to address thememory and the I/O equipment.

• Address buses in various microprocessors differ only in width.

The most common number of address connections available today is 16,with some of the newer microprocessors containing either 20 or 24connections.

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ARCHITECTURE

• Most address buses are three-state connections, which will go to theirhigh-impedance state at some time during normal microprocessoroperation.

• An n-bit address bus is addressed 2n address locations from 0 to 2n-1,(0N2n-1). Where, N is any address location.

Example:16-bit address bus (n=16) is addressed216=26x210=64x1024=64K=65536 address locations from 0 to 65535 (Decimal), or 0000H to FFFFH (Hex).

NOTE:1 K=210 =1024 = 1 Kilo (K)1 M=220=210210 =10241024=KK=1048576 = Mega (M)

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ARCHITECTURE

0000H

FFFFH

64K

For example (n=16 bit), an 16-bit

address bus [A0-A15] is addressed

216=65536=64K address locations

(N) from (0 to 216 -1).

i.e.

(0N65535) decimal or

(0000NFFFF) Hex.

Where, N is any address location.

Address (Lower)

Address (Upper)

Memory

Address

Locations

0001H0002H

FFFEHFFFDH

.

.

.

N

.

.

.

.

.

.

.

.

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ARCHITECTURE

b) Data Bus

• The data bus carries the information (data).

• The data bus is typically a bidirectional bus that may, in someprocessors, also be multiplexed with some other information.

• If an external buffer is required on this bus, it takes the form of abidirectional bus buffer or bus transceiver (74LS245 IC).

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ARCHITECTURE

c) Control Bus

• The control bus controls the direction, flow, source and destination ofthe information.

The control bus is one of the most important buses in the system, sinceit actually controls the memory and I/O equipment (units).

• Each microprocessor in production today has a slightly different controlbus configuration.

• The most important control bus signals are theread and write signals,since these are the basic functions of the memory and the input/outputcircuitry.

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ARCHITECTURE

5) Address Decoding Unit

• An address decoder is a digital circuit (combinational logic circuit) thatindicates that a particular area of memory is being addressed by themicroprocessor.

• In other words, an address decoder is a digital circuit that decodes thememory address presented on the address bus by the microprocessor toselected memory devices.

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4. MEMORY INTERFACE

Q: What is memory?

A: Memory is a device in a computer system that stores the data and instructions of the programs.

• Generally, memories are organized into a hierarchy according to theiroperation speed and storage capacity.

• Figure 4-1 shows the memory hierarchy in computer systems.

• Memory devices are applied as the buffer memory and the mainmemory both of which are required to operate at relatively high speed.

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MEMORY INTERFACE

Integrated Circuit (IC)

Memory

or

Semiconductor Memory

RAM

ROM

Dynamic

Static

Mask ROM

PROM

EPROM

EEPROM

Flash

MEMORY

MOS

MOS/BJT

MOS

BJT

MOS

MOS

MOS

Volatile

Memory

Non-Volatile

Memory

4.1 Characteristics of IC Memory Devices

Figure 4-2 Classification of semiconductor memories

MOS: Metal Oxide Semiconductor

BJT: Bipolar Junction Transistor

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MEMORY INTERFACE

• Both types (ROM and RAM) have many of the same features, includingaddress connections, data bus connections, and similar controlconnections.

Data Bus Connections (Input/output)

D0, D1, D2, . . . , Dm-1

Word Size is m bits

Memory Device

Control Bus Connections (Input)

i.e. CS1 Chip Select signal (Low active) or

CS2 Chip Select (High active)

OE, Output Enable (for read from memory device, Low active)

WR Write (for write to memory device)

Address Bus Connections (Input)

A0, A1, A2, . . . , An-1

Memory Capacity is 2n Word size, (2nxm)

mn

10101110

11101010

01111010

Example: Word size is m=8 bits=1 Byte

of memory (numeric binary data)

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MEMORY INTERFACE

• There are two features that distinguish Random Access Memory (RAM)and Read Only Memory (ROM):

1) RAM is read/write memory while ROM is read-only memory; and

2) RAM is volatile, (the contents are lost when power is removed) whileROM is nonvolatile.

• The ROM and the RAM are the two general categories of memorydevices in common use today (see figure 4-2).

• The ROM is commonly used to store programs and long-term datanonvolatilely;

• The RAM stores temporary data, since it is a volatile memory.

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MEMORY INTERFACE

4.2 Some Integrated Circuit Memories

EPROMs: SRAMs:

2716, 2KB memory size 6116, 2KB memory size

2732, 4KB “ ---

2764, 8KB “ 6264, 8KB “

27128, 16KB “ ---

27256, 32 KB “ 62256, 32KB “

27512, 64 KB “ ---

EEPROM: FLASH MEMORY:

2864 (Atmel) 28F001 (Intel)

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MEMORY INTERFACE

4.3 Address Decoding Circuits

• An address decoder is a digital circuit that indicates that a particulararea of memory is being addressed, or pointed to, by themicroprocessor.

• In other words, an address decoder is a digital circuit that decodes thememory address presented on the address bus by the microprocessor toselected memory or I/O devices.

• In other words, an address decoder is a simple combinational logiccircuit used to decode the memory address.

• In other words, an address decoder is a logic circuit that takes thememory address from the MPU and decodes a unique range ofaddresses that are used to select memory or I/O devices.

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MEMORY INTERFACE

[A0 – A15]

From MPU Address Bus

Decoder Output(s), usually low active

Yi (i=0, 1, 2, 3, ..., p-1)

Address

Decoder

Combinational

Logic CircuitFrom MPU Control Bus

i.e. VMA for 6802 MPU

To Memory or I/O Device Chip Select (CS) or Chip Enable (CE) Inputs.

FIGURE 4-3.1 Block diagram of an address decoding circuit

• Most address decoders have one or more outputs that become active fora particular area (segment) of memory.

p

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MEMORY INTERFACE

4.4 Memory Map and System Memory

Q: What is a Memory Map?

A: Memory map is a drawing of the proposed structure of the memorysystem.

• The first step in developing any system memory is the memory map.

• A memory map illustrates which segments are to be used for ROM, RAMand I/O devices.

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MEMORY INTERFACE

• For example, the memory map of a small memory system (64K)consisting of m segments of devices (i.e. ROM, RAM, I/O).

FFFFH

0000H

Memory Map

64KAn 16-bit address bus[A0-A15] isaddressed 216=65536=64Kaddress locations (N) from(0 to 216 -1).

(0N65535) or (0000HNFFFFH)Where, N is any address location.

Device 0

Device 2

Device p

Device 1

No devices in these segments

Address

Address

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MEMORY INTERFACE

Example-1: Develop a memory system that uses two memory devices

(i.e. 2 KB-RAM and 4 KB-ROM). Location of this devices are shown inthe following memory map.

64K

Memory Map

Device 1

Device 027FFH

2000H

AFFFH

A000H

FFFFH

0000H

2K

4K

No device in this segment

No device in this

segment

No Device in this segment

30K

8K

20K

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MEMORY INTERFACE

Addres Decoding

Circuit

?

Y0

Y1

To Device 0

Chip select input

To Device 1

Chip select input

(2000H-27FFH)

(A000H-AFFFH)

FIGURE 4-3.2 Block diagram of an address decoding circuit of Example-1

[A0 – A15]


From MPU Control Bus

i.e. VMA, E

for 6802 MPU

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MEMORY INTERFACE

TYPE ADDRESS A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Y0 Y1

2000H 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

DEVICE 0 27FFH 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1

2KB 2000H-27FFH 0 0 1 0 0 X X X X X X X X X X X 0 1

A000H 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

DEVICE 1 AFFFH 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1

4KB A000H-AFFFH 1 0 1 0 X X X X X X X X X X X X 1 0

1 0

DEVICE Decoder OutputsMPU ADDRESS BUS

0 1

12 bits (212=4K) Don’t Cares.MPU Address pins are connected to DEVICE 1 address inputs.

11 bits (211=2K) Don’t Cares.MPU Address pins are connected to DEVICE 0 address inputs.

The first four bits of

the address bus pins are connected to address decoder inputs.These address pins are decoded by the address decoder circuit.

The first five bits of the

address bus pins are connected to address decoder inputs.These address pins are decoded by the address decoder circuit.

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MEMORY INTERFACE

A15

A14

A13

A12

A11

To DEVECE 0

Chip Select input

Decoder Output

2000H-27FFH

Active Low

Decoder

Address

Inputs

(5-bits)

Or Equivalent Dual Circuit

Decoder Output

2000H-27FFH

Active Low

74LS30 NAND

A15

A14

A13

A12

A11

Decoder

Address

Inputs

(5-bits)

To DEVECE 0

Chip Select input

74LS04 Inverter

Note: 74LS30 IC is 8-inputs NAND gate. Therefore Last 3-inputs of the NAND gate must be connected to logic 1 (i.e. +5V).

FIGURE 4-3.3 Basic circuit for decoding addresses between 2000H-27FFH

Y0

Y0

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MEMORY INTERFACE

A15

A14

A13

A12

Decoder Output

A000H-AFFFH

Active LowTo DEVECE 1

Chip Select Input

Decoder

Address

Inputs

(4-bits)

Or Equivalent Dual Circuit

74LS20 NAND

A15

A14

A13

A12

Decoder Output

A000H-AFFFH

Active LowTo DEVECE 1

Chip Select input74LS04

74LS04 Inverter

Decoder

Address

Inputs

(4-bits)

Note: 74LS20 IC is 4-inputs NAND gate.

FIGURE 4-3.4 Basic circuits for decoding an address beginining with an“A” hexadecimal (i.e A000H-AFFFH)

Y1

Y1

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MEMORY INTERFACE

DEVICE 1

4KBADDRESS DECODER

DEVICE 0

2KB

CS1CS0

A0..A10 D0..D7

ADDRESS BUS [A0..A15]

11

DATA BUS [D0..D7] 8

A0..A11 D0..D7

12

74LS20

NAND74LS04

Inverter

A15

A13

A12

A14

74LS30

NAND

74LS04

Inverter

A14

A15

A13

A12

A11

2000H-27FFH

Active Low

A000H-AFFFH

Active Low

8 8

Y0

Y1

FIGURE 4-3.5 Block diagram of memory system

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MEMORY INTERFACE

Integrated Decoder Circuits (74LS138/74LS139)

• In most applications, more than one memory device is usually requiredfor system operation.

• It would be extremely wasteful to use an eight-input NAND gate (orother logic gates) for each memory device.

• To avoid such waste, a decoder, selected from the variety in productionby the IC houses, is used.

• An extensive search for the ideal decoder suggests that for manyapplications the 74LS138, 3-to-8 line and 74LS139 2-to-4 line decodersare ideal. In fact, after examining many pieces of microprocessor basedequipment, it appears that entire industry has also discovered thisdevices.

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MEMORY INTERFACE

• Figure 4-3.6 and Figure 4-3.7 depicts these decoders along witha truth table describing its operation.

• These decoders have active low outputs that become active onlywhen all of the enable inputs are at their active levels.

• Whenever these devices are enabled, the 3-bit (A, B, C selectinputs) or 2-bit (A1, B1 or A2, B2 select inputs) binary numberspresent at the address inputs causes one of the output pins tobecome active.

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MEMORY INTERFACE

74LS138 Connection Diagrams 74LS139 Connection Diagrams

FIGURE 4-3.6 Connection diagrams of decoders

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MEMORY INTERFACE

74LS138 Truth Table 74LS139 Truth Table

FIGURE 4-3.7 The 74LS138 3-to-8 line and the 74LS1392-to-4 line decoder truth tables

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MEMORY INTERFACE

74LS138 Connection Diagrams 74LS139 Connection Diagrams

FIGURE 4-3.8 The 74LS138 3-to-8 line and the 74LS1392-to-4 line decoder connection diagrams

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MEMORY INTERFACE

Example-2: Develop a memory

system that uses eight 2 KBmemory devices (i.e. 2 KB-RAM or 2KB-ROM). Location of this devicesare shown in the following memorymap.

DEVICE 4

2000H to 27FFH (2K)

DEVICE 5

2800H to 2FFFH (2K)

DEVICE 6

3000H to 37FFH (2K)

DEVICE 7

3800H to 3FFFH (2K)

DEVICE 0

0000H to 07FFH (2K)

DEVICE 1

0800H to 0FFFH (2K)

DEVICE 2

1000H to 17FFH (2K)

DEVICE 3

1800H to 1FFFH (2K)

2K

NO DEVICE

(EMPTY)

4000H to FFFFH (48K)

48K

16K

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MEMORY INTERFACE

IC

Addres Decoding

Circuit

?

To Device 0

Chip select input

To Device 1

Chip select input

FIGURE 4-3.9 – Block diagram of an address decoding circuit ofExample-2

(0000H-07FFH)

Yo

(0800H-0FFFH)

Y1

(3800H-3FFFH)

Y7 To Device 7

Chip select input

[A0 – A15]


From MPU Control Bus

i.e. VMA for 6802 MPU

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MEMORY INTERFACE

TYPE ADDRESS A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0000H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DEVICE 0 07FFH 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1

2KB 0000H-07FFH 0 0 0 0 0 X X X X X X X X X X X 0 1 1 1 1 1 1 1

0800H 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

DEVICE 1 0FFFH 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

2KB 0800H-0FFFH 0 0 0 0 1 X X X X X X X X X X X 1 0 1 1 1 1 1 1

1000H 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

DEVICE 2 17FFH 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1

2KB 1000H-17FFH 0 0 0 1 0 X X X X X X X X X X X 1 1 0 1 1 1 1 1

3800H 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0

DEVICE 7 3FFFH 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2KB 3800H-3FFFH 0 0 1 1 1 X X X X X X X X X X X 1 1 1 1 1 1 1 0

1 0

DEVICE Decoder OutputsMPU ADDRESS BUS

0 1 1 1 1 1 1

1 1 1 1 1

1

1

1 1 0 1 1 1 1 1

1 1 1 1 1 1 1 0

A11, A12, A13 are connected to decoder output-select inputs (A, B, C) respectively.

A14, A15 are connected to decoder Chip-Enable/Select inputs (G2A’, G2B’).

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MEMORY INTERFACE

FIGURE 4-3.10 Block diagram of memory system

DEVICE 7

2KB

DEVICE 1

2KB

CS7

A0..A10 D0..D7

ADDRESS BUS [A0..A15]

11

DATA BUS [D0..D7] 8

A0..A10 D0..D7

118 8

A12

A11

A13

A15

A14

DEVICE 0

2KB

CS0

A0..A10 D0..D7

118

A

B

C

G2A

G2B

G1+5 V

(i.e. logic 1)

or VMA

from 6802

MPU

Y0

Y1

Y2

Y7

CS1

74LS138

3-to-8 line

DECODER

2. COMPUTER and MICROPROCESSOR ARCHITECTUREyildiz.edu.tr/~sedef/verdigi dersler_files/Memories and...

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