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2.3 Build sequential

logic circuitCombinational logic circuit

Sequential logic circuit

Flip-flop

Build flip-flop using logic gates1


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Objectives:

Define sequential logic circuit.

Differentiate between combinational logic circuit andsequential logic circuit.

Describe flip - flop.

Identify various types of flip-flops.

Build SR, JK, T and D flip

flop using logic gates. Draw the symbol and truth table of SR, JK, T and D flip

flop.

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2

3

4

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Sequential & Combinational

logic circuitDefine sequential logic circuit.

Differentiate between combinational logic circuit andsequential logic circuit.

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2

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Difference betweenCombinational & Sequential logic circuit

Basic building

blocks include:

Basic building blocks

include FLIP-FLOPS:

Combinational Logic Circuits

Sequential Logic Circuits

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Sequentiallogic circuit

Sequential logic is the type of digital system

that does not only depend on current input, butalso the previous history of the system.

For that reason sequential logic requires

memory elements to function.

The building blocks used to construct devicesthat store data are called flip-flops.

S

C

R

Q

Q'

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Sequent ial circuit have loop s

these enable curcuits to receive feedback

Sequential logic circuit

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Combinationallogic circuit

Combinational logic is an interconnection of

logic gates to generate a specificities logicfunction where the inputs result in an

immediate output, having no memory or

storage capabilities.

There are function only based on theirinputs, and NOTbased on clocks.

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Combinational circuit is combination

of various logic gates

Combinational logic circuit

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Flip-Flop

Describe flip - flop.3

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Flip-Flop

"Flip-flop" is the common name given to two-state

deviceswhich offer basic memory for sequentiallogic operations.

Flip-flops are heavily used for digital data storage and

transfer and are commonly used in banks called

"registers" for the storage of binary numericaldata.

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Flip-Flop

Flip-flop are basic storage/memory elements.

Flip-flop are essentially 1-bit storage devices.

Types of flip-flops are:

1. SR Flip-flop

2. JK Flip-flop

3. D Flip-flop

4. T Flip-flop

Application of flip-flop:

1. Counter 4. Logic controller

2. Register 5. Frequency Divider

3. Memory

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SR Flip-Flop


Build SR, JK, T and D flip flop using logic gates.

Draw the symbol and truth table of SR, JK, T and D flipflop.

4

5

6

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SR Flip-Flop

The simplest binary storage device.

SR Flip-flop have 2 inputs (SET & RESET)and 2outputs (Q & Q).

NOTE: Q & Q are complimentsof each other

The SR flip flop is sometimes referred to as an SR

latch. The Term latch refers to its use as a

temporary memory storage device.

S

R

Q

Q'

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SR Flip-Flop

Symbol:

SR Flip-flop (Active HIGH)

NOR gateSR Flip-flop (Active HIGH)

Symbol14


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SR Flip-Flop

Symbol:

SR Flip-flop (Active LOW)

NAND gateSR Flip-flop (Active LOW)

Symbol15


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SR Flip-Flop

Truth Table:

SR Flip-flop

(Active HIGH)

S R Q Q'

0 0 NC NC No change. Latchremained in present state.

1 0 1 0 Latch SET.

0 1 0 1 Latch RESET.

1 1 0 0 Invalid condition.

S' R' Q Q'

1 1 NC NC No change. Latchremained in present state.

0 1 1 0 Latch SET.

1 0 0 1 Latch RESET.

0 0 1 1 Invalid condition.

S

R

Q

Q'

S

R

Q

Q'

SR Flip-flop

(Active LOW)16


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SR Flip-Flop

Timing Diagram:

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What is the mode of operation of the SR flip-flop (set, reset or hold)?

What is the output at Q from the SR flip-flop (active LOW inputs)?

Mode of operation = ?

?HL

Low

Reset

IQ Test!

Mode of operation = ??L

H

Mode of operation = ??

HH

High

HighHold

Set

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Clock

SR Flip-FlopIdentify various types of flip-flops.



4

5

6

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Clock Flip-flops: synchronous bistable devices

Output changes state at a specified point on a

triggering input called the clock.

Change state either at thepositive edge (rising edge) or

at the negative edge (falling edge)of the clock signal.

Positive

edges

Negative edges

Clock signal

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ClockSR Flip-Flop

The Clocked SR Flip Flop likeSR flip-flop but with

extra third input of a standard clock pulse. The output of Q and NOT Q will not change

(despite making changes to the inputs Set & Reset)

in a Clocked RS Flip-flop Until receiving a signal

from the clock.

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Clock SR Flip-Flop

Symbol:

Clock SR Flip-flop (+ve EDGE)

Combination gateClock SR Flip-flop (+ve EDGE)

Symbol22


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SQ

Q'

CLK

Pulse

transitiondetector

R

Positive-going transition

(rising edge)

CLK

CLK'

CLK*

CLK'

CLK

CLK*

Negative-going transition

(falling edge)

CLK'

CLK

CLK*

CLK

CLK'

CLK*

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Clock SR Flip-Flop

Truth Table:

S-R flip-flop: on the triggering edgeof the clock pulse,

S=HIGH and R=LOW is a SET state

R=HIGH (and S=LOW) is a RESET state

If both SR inputs LOW a NO change

If both SR inputs HIGH a INVALID

Truth table of positive edge-triggered S-R flip-flop:

X = irrelevant (dont care)

= clock transition LOW to HIGH

S R CLK Q(t+1) Comments0 0 X Q(t) No change

0 1 0 Reset1 0 1 Set1 1 ? Invalid

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Clock SR Flip-Flop

Timing Diagram:

How if we add clock as input?Please draw the output waveform for me

(Positive edge triggered)

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D Flip-Flop




4

5

6

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D Flip-Flop

Truth Table:

D flip-flop: single input D (data)

D=HIGH a SET state

D=LOW a RESET state

Q follows D at the clock edge.

D flip-flop formed by add NOT gate between SR input.

D

C

Q

Q'

S

C

R

Q

Q'

CLK

D D CL K Q(t+1) Comments

1 1 Set0 0 Reset = clock transition LOW to HIGH

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D Flip-Flop

Symbol:

D Flip-flop (+ve EDGE)

Combination gateD Flip-flop (+ve EDGE)

Symbol

DQ

Q'

CLK

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D Flip-Flop

Timing Diagram:

CLKCLK CLKCLK

Q

Q

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JK Flip-Flop




4

5

6

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JK Flip-Flop

J-K flip-flop: Q and Q' are feedback to the pulse-

steering NAND gates.

No invalid state.

Include a toggle state.

J=HIGH (and K=LOW) a SET state

K=HIGH (and J=LOW) a RESET state

If both inputs LOW a NO change

If both inputs HIGH aToggle

J

C

K

Q

Q'

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JK Flip-Flop

Symbol:

JK Flip-flop (+ve EDGE)

Combination gateJK Flip-flop (+ve EDGE)

Symbol

JQ

Q'

CLK

K

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JK Flip-Flop

Truth Table:

J K CLK Q(t+1) Comments

0 0 Q(t) No change0 1 0 Reset1 0 1 Set1 1 Q(t)' Toggle

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JK Flip-FlopApplication: Frequency Division

J

C

K

Q

CLK

High

CLK

Q

Divide clock frequency by 2.

J

C

K

QA

CLK

High

J

C

K

QB

High

CLK

QA

QB

Divide clock frequency by 4.

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JK Flip-Flop

Timing Diagram:Similar to S-R flip-flop but toggles when J = K = 1

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T Flip-Flop




4

5

6

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T Flip-Flop

Truth Table:

T flip-flop: single-input version of theJ-K flip

flop, formed by tying both inputs together.

J

C

K

Q

Q'

CLK

T

TQ

Q'

CLK

T CLK Q(t+1) Comments

0 Q(t) No change1 Q(t)' Toggle

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