1993 High Speed Digital Design SYlllposium...1993 High Speed Digital Design SYlllposium Fli"Ja...

1993 High Speed DigitalDesign SYlllposium

Fli"Ja HEWL.ETT~~ PACKARD

Physical Layer Design Issues forSerial Communications:A SONET Case Study

Neil QuarmbyHoward RubinRick CurtisLou Levesque

Texas Instruments, Inc.Dallas, Texas

Tel: (214) 644-5580Fax: (214) 997-6390 -

1993High Speed DigitalSystems Design & TestSymposium

© Hewlett-Packard Company 1993

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Abstract

Today's evolving communication networks require highlyreliable physical layer transmission of digital bits. Withspeeds increasing to phenomenalrates, reliability is becomingincreasingly difficult to designinto the physical layer. This

Authors

Neil Quarmby B.Se

Current Activities:Neil Quannby is StrategicTechnical Marketing Manager forEuropean TelecommunicationsTransmission and SwitchingApplications. He is currentlymanaging the development offull-custom circuitry containinghigh-speed analog PLLs whichare targeted for use in theTGB2000 BiCMOS ASIC family.

paper discusses some of the mostsignificant physical layer issuesthat must be considered whendesigning a serial communications system, including jittermanagement, byte and cellsynchronization, clock recovery,and others.

Author Background:Neil joined Texas InstrumentsLtd. in 1978 after graduatingfrom Nottingham University.Neil managed a group of engineers working on Digital SignalProcessor and Graphics SystemProcessor support. He waselected to Member, GroupTechnical Staff(1987) and thescope of his role expanded toinclude all European Militarycustomers. His current assignment is to develop, coordinate andmarket silicon solutions in thebroadband communications arena.

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Authors (Cont'd)

Howard Rubin PE

Current Activities:Howard Rubin holds the titleof Member ofTechnical Staffin the Semiconductor Groupat Texas Instruments. Howardprovides application engineeringassistance in the design and testof LAN and WAN internetworking products using T1's advancednetworking components.

Author Background:Howard graduated with theBSEE degree from PennsylvaniaState University (1969) andearned an MBA at Rider College(1988). He has served as representative on LAN standardsand testing committees andteaches numerous workshopson Token Ring LAN and ATMW.AN architecture and design.

Rick Curtis

Current Activities:Rick Curtis holds the positionof Member of Group TechnicalStaff of the SemiconductorGroup at Texas Instruments.Rick is currently involvedin product definition anddevelopment for SONET/SDHIATM catalog products.

Author Background:Rick holds a BSEE degree fromthe University ofArkansas(1983) and a MSEE degree fromSouthern Methodist University(1992). Rick has been employedat Texas Instruments since 1983.

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Lou Levesque

Current Activities:Lou Levesque is a Memberof Group Technical Staff in theSemiconductor Group at TexasInstruments. Lou is currentlyinvolved in system level development for SONET/ATM applicationspecific integrated circuits.

Author Background:Lou holds a BSEE degree fromNortheastern University (1973).Lou worked with AT&T BellLaboratories, North Andover,MA for over thirty years as aMember ofTechnical Staff, andhas been with Texas Instrumentsfor over two years.

Physical Layer Design Issues for SerialCommunications: A SONET Case Study

Slide #1

Physical Layer Design Issuesfor Serial Communications:

A SONET Case Study

•Texas Instruments

Slide #2

Overview• SONET networks

Network spanGeneric model

• Physical layer issuesFrame structuresAlarms and indicationsNoise sources and specifications

• TOC BiCMOS componentsTDC1555 clock recovery chipTDC23028 line interface chip

• Conformance measurementsJitter tolerance/attenuation testRMS jitter testSONET framing, alarm and indications test

A review of the SONET network span is providedto depict the functional requirements of particularnetwork elements. A more focused development ofageneric serial transmission model is used to delineatethe lower layer procedures that may be implementedin VLSI. An examination ofbit, byte and framestructure expected in the SONET STS-3 and SDHSTM-1 data streams sets the stage for discussion offrame synchronization tasks. Signaling informationrelating to alarms and indications between networkelements is discussed. Noise sources impacting therecovery of a stable clock is graphically presented toenhance the appreciation of practical clock recoverysolutions. Levels ofjitter attenuation and tolerancein clock and data recovery systems is related totesting methodologies to ensure conformance toindustry standards and practice.

A brief overview ofTI's BiCMOS process technologywill familiarize the reviewer offeatures and benefitsof this advanced architecture making possible highspeed silicon building blocks for SONET, SDH andATM networking solutions. A functional blockdiagram of the TDC1555 highlights the performancetasks of this TI clock recovery chip. Anothercomponent, the TDC2302B, is introduced whichaccepts serial information from the clock recoverychip and converts the data to parallel format is alsodescribed. The relationship of these devices to theTDC3003 SONET overhead terminator is brieflypresented. A practical arrangement for measuringjitter, jitter tolerance and jitter attenuation usingHP instrumentation as implemented in TexasInstrument's Shennan, Texas facility is presented.

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Slide #3

The SONET/SDH Network Spans

:.-:1------ Path --------+=~U". -+. +:1---- Un. ----..:

Source: Dykes, M., 'SONET MeaslJr8mantS in the Real Wotld,'Hewlett: Packard, 1992Comm. TestSymp.

Category Interfaces

Category I equipment is used in the 1.5.. to 45.. Mb/s(DS-l and DS-3) interfaces to SONET NEs.

Category II equipment is used in the OC-N andSTS-N interfaces for synchronous SONET interfacesto regenerators for the purpose of connection to andbetween carriers.

Network Elements

Terminal Multiplexers are used to combine lowerrate data streams to higher data rate capacity lines.Digital cross connects provide switching capabilityto route tributary data streams among higher rateSTS-3c carriers. Regenerators are used to restorebit-level signal quality so as to equalize the effectsof channel distortion and accumulated phase jitter.Regenerator applications may involve only physicaland section layer design rules. The Add DropMultiplexer (AlDM) network element is used to addor drop, say DS-l signals from, say STS-l signals.

Since it connects to the telecommunicationsnetwork, it extracts and transfers the networkclock to subsequent stations. The requirementsfor the AlDM may be more rigorous than the localapplication, since exacting standards for transferredphase noise performance exist for equipmentgenerating a clock to the carrier network LocalApplications are those generally associated withend user applications, hence host burden, costand packaging issues are primary considerations.These may be Internetworking or workstationapplications that feed the main SONET datastream, but terminate the data to a local areanetwork gateway or user application.

Layers

A layered interface exists in the SONET/SDHbit framing structure and application-specificdevices can be designed to encode/decode specificbit patterns into bytes and words carrying data.At the physical layer, the electrical or opticalinterface is made to the STS or STM signals. Assuch, issues of power level, pulse shape, line codingand channel equalization are considered. Detailsinvolving the LED driver for the Fibre Optic Cablemay also be considered. The section layer involvesdesign rules for access to the medium such asframing, scrambling, section error monitoring andcommunication of section level overhead. The linelayer provides synchronization and multiplexingfunctions required by the path layer so as to providetransport services for STS SPE payloads. Suchfunctions as overhead for maintenance andprotection purposes are inserted in the line layersignaling. The transport of network servicesbetween SONET higher layer protocols or terminalmultiplexing equipment is provided by at the pathlayer. End-to-end tributary services such as DSl,DS3, etc are enabled by means of POH pathoverhead information.

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Slide #4

Signal Processing

Physical Media Interface

Access to payload information and the insertion andextraction of data frames is the major function oftheoverhead terminator. End user applications requirea data interface that optimizes attached system buslimitations. By stripping the Framing informationneeded to access the SONET network from theactual payload information, the data manipulationprocedures of the host protocol processor may bemore efficiently executed. In the process of buildingSONET frarn.es for transmission to the network, thesection, line and path overhead bytes need to beinserted with the payload frarn.es before convertingthem to/from the serial transmission physical layer.

methods are used for line encoding ofthe serialbit stream which yield significant gains in channelutilization and error detection and correction, suchas B8ZS, B3ZS, and 8B/10B. Bit level, modulo2 scrambling is used in the encoding/decodingprocess to eliminate the effect of extended zerosor ones that can cause clock synchronizationfailures due to insufficient data cell transitions.As mentioned previously, layer overhead andpayload data is embedded in the received SONETsuperframe. Signal processing procedures arerequired to identify the locations ofthese data bytesto generate byte and frarn.e synchronization signalsto flag the appearance of this information. Highspeed data is transmitted serially to avoid multipleparallel paths in the communication medium.However parallel processing of the these decodedbits is necessary in order to reach the channelcapacity using byte and multi-byte wide processors.Embedded in the frames passed between stationsare alarms and indications which communicate thestatus of the line interface and subsequently dataintegrity. Upon detection of an alarm condition, astatus flag is inserted in the frame to communicateto a far-end network element that terminates theservice the need to initiate automatic servicemanagement processes. Internal parity checkingand lockout are used to protect the process ofbit/byte conversion and data handling procedures.

Payload Access

InserVExtractPayload InformationInto/From SlandarclizedFrame or Format

AddID9Iete TJ3flSIT1issionOverhead

Frame/Byte Alignment

Serial to Parallel.Parallel to Serial Conversion

Alarm Detae:tion and lndlcal:ion

Parity Generation and Checking

Clock Recovery!Clock Generator

Signal Encoding!Decoding (B8ZS. B3ZS.881108, Scrambling, etc.)

Fibre OpticRecelverf[)rtver

UTP/STP Transceiver

coax TransceIVer

A Fiber Optic (Fa) interface is typically requiredin SONET networks and is required to convert theoptical transmitter and receiver energy to electricalpulses that can be interpreted by electrical clockand data recovery circuits. Many applications inlocal networks currently have metallic transmissionmedia installed, and these will be used for shortdistance transmission service. The transceiversfor interface with Unshielded Twisted Pair (UTP)media have the additional task ofequalizing forchannel distortion and intersymbol interference.Data transmission on coaxial cable rather thanbalanced twisted pair will feature more uniformchannel characteristics with less noise. However,the added cost of the transmission medium willhave to be realized.

Generic SerialTransmission Model

After the medium has been properly terminated,the next step is to recover the network clock andto regenerate it for data validation and subsequentframe synchronization. The inherent noise qualityof the clock recovery circuit as well as its responseto phase jitter are critical to the robustness ofthenetwork and effect its ultimate dimension. Various

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Slide #5 SONET/SDH Frame

2430 Bytes/Frame' 8 Bils/Byte • 8000 Frames/Sec = 155.52 Mb/s

SONET/SDH Serial Data Stream

However at 125 JlS and 155.52 Mb/s, each framecarries a total of2430 bytes organized in 9 rowsof 270 bytes per row. The first nine columnscontain overhead·and pointer information thatallows access to the SONET channel asdescribed above. The section overhead identifiesthe Framing, STS-l Identifiers, Section ErrorMonitoring, Orderwire, Section User Channel,and Section Data Communication Channelbytes. The location of these bytes is critical tomaintaining coordination with other sectionterminating functions, as well as transportingSTS-3 frames across the physical medium. Theline overhead contains Pointer Offset, PointAction, Line Error Monitoring, APS Channel,Line Data Communications Channel, Orderwireand bytes reserved for Growth. The location ofthese bytes is critical to maintainingcoordination with other line terminatingfunctions, as well as locating the start of thepayload envelope data. The payload pointersprovide a means for flexible and dynamicalignment of STS Synchronous PayloadEnvelope within the STS envelope capacity.These allow the SPE to float within the STSenvelope capacity to accoIIllIlodate phase andrate variations.

The payload envelope is the bearer capacityfor transmitted user information. Two typesof data organization follows: The STS-3 byteinterleave format allows for transmission ofmultiple tributaries, referred as virtual tributary(VT), within a single SPE. The informationis byte interleaved which ensures fairness inthe allocation of channel capacity amongmultiple subrate sources. If the SPE capacityis to used for the STS-3c or STM-l payloadformat, a concatenated SPE is possible. Theensures that the subrate services are kepttogether, whereby the SPE must be multiplexed,switched, and transported through the networkas a single entity.

SONET Payload Envelope

".

STS-3c orsnii·· ..

Concantel"lated Payload

Frame Slot Width = 125 /..IS

SONETPayload 9 Rows

Envelope

······ .. f!~~....... ........... 9Columns

'.

Payload Pointers

Una OverheadL.U:-......,.------:.,.l

Section Overhead

+--.261 BYt~ ---+ .>::ST$-3

Byte Interleaved Payload

Bit, Byte, and Frame Synchronization_~.~ID.ID••

~ a a ......

The STS-3 or STM-l rate is transmitted at arate of 155.52 Mb/s (nominal). The informationis transmitted bit-by-bit using a CMI, coded markinversion line code. After conversion to the electricalsignal, the data pulses are nominally "rectangular"(although at 155 Mb/s they are anything butrectangular) and must fit in a Transmitter pulsemask which is defined for a binary zero and binaryone symbol. These signals are very low in amplitude(0.5 V) and have a fast rise time of2 ns. Since thisdata stream must propagate through the establishedcarrier line equipment, a 125 JlS frame slot width isimposed on the data pattern. This essentiallydefines the framing rate of 8K frames per second andfurther defines the size ofthe SONET frame able tobe transported at this rate. Naturally as the linerate increases to 622 Mb/s and higher, larger dataframes may be constructed, but the 125 Jls frame slotwidth requirement remains fixed.

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Slide #6

SONET/SDH Alarmsand Indications

• Alarm Indications

• LOS Loss of Signal

• Tracking Mode Frame Monitoring• RFE Received Frame Error• OOF Out of Frame Error• LOF Loss of Frame Error

Slide #7

Noise and Distortion inSONET/SDH Clock Recovery

One of Two

AClock Generated Noise

RMSJitter

Amplitude

Noise Roor L..- _

Alarm Indications

1/1 ShotWander Noise

Thermal NoiseNon·Unearilies

Frequency

Jitter - General

Intermodulation

A Loss of Signal condition occurs when the receiverloses clock or data transitions (high or low) for aperiod of25 !ls, which corresponds to about 38-bitcells of signal loss.

Tracking Mode Frame Monitoring

A Receive Frame Error occurs coincident with loss offrame synchronization and is signaled by the localreceiver coinddent with the third A2 framing byte ofthe Section Overhead. If four consecutive frameshave framing errors, OOF becomes active high. Itwill remain active for at least two frames to verifYframing integrity. The LOF indicator becomesactive high if OOF is high for 3 ms, which relates to24 frames worth oferror. It remains high until eightl'lII1~"'l:lILivl'"1"'1 I[Jl-frl":r: fHlll1i]]~paUU[;lTIj) illlJ llJlJ[;inid.

Jitter is the uncertainty associated with a signal'sbit cell value that results in the loss of datarecognition at terminating network elements.Jitter is often measured on the extracted clockas the level ofRMS Jitter Amplitude within anarrow bandwidth of frequency. The noise may becharacterized by checking the Jitter Amplitude atdiscrete frequencies, then plotting on a continuum.Avariety of sources contribute to phase instabilitya~ mea~ured from one bit cell to the next. Jittercan result from system stimuli such as error bursts,phase hits, and outages. However data patterntransitions can also cause jitter. Accumulation ofjitter in a chain of regenerating stations can occur ifeach station must synchronize to and transfer datawith respect to the locally recovered clock. Channeliml1cUnnonto ouoh QO roiwu l~iJiJl D.a~ 191ilil 9&'9....h·.1kJ

and other probleD1s exacerbate the generation of

clock jitter. The use offiber optic transmissionOlia.th roduooo tho offoot ofOhQnml! impall'W~ntli.

RMS Jitter Amplitude

On the vertical axis, a measure ofjitter amplitudeis presented relative to the noise floor. The noisefloor is the lowest level of discernible noise ininstrumentation circuits. All noise from the clockextraction circuit must be measured against thisnoise floor. The clock recovery circuit performs aswould a filter to pass the desired signal (clock) from

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all other signals (noise). The selectivity ofthisfiltering process is a measure ofits ability toattenuate interfering noise that shows up asclock jitter.

Frequency of Jitter Noise

Along the frequency domain are possible causes ofjitter. Wander, Thermal Noise, and Nonlinearityresult in low frequency phase jitter. These effectsare easily tracked by succeeding clock recoverycircuits, and are transferred to down streamnetwork entities. Shot noise is more burst-like inoccurrence and typically falls within the bandwidthofthe clock recovery filter. Fortunately the levelof shot noise is nearer the noise floor and presentsless ofa problem to clock recovery circuits.Intermodulation noise results from channeldistortion and environmental interference and sois difficult to eliminate in practical installations.This noise occurs at increasingly higher frequenciesand may fall outside the bandwidth ofclockrecovery circuits. A tradeoff exists in the designof receiver circuits deploying narrow bandwidthclock recovery circuits to filter some ofthis noise,yet pass an allowable amount to the next station.

Slide #8

Noise and Distortion inSONET/SDH Clock Recovery

Two of TwoCLOCK EXTRACTION

METHODS ADVANTAGES DISADVANTAGES

Jitter Tracking, DutbandI/O Drive Umited. Excitation

SAW Filters Dependent. High Cost, LargeJitter, Attenuation

and Fragile

Frequency Stability, SuperiorPhase Drift. Vcc/GNO Noise.

Silicon PLLs I/O, Macro call. capability,Low Cost False/lnje<:tion, Locking

VCXO Osdllators High Frequency, Stability High Cost, Low Jitter Tolerance

Low Cost,High Transfer Jitter, Analog

RCIAclive FiltersTraditional Des$gn Adjustment, R&CluiresJtt1er,

Absorbing Circuits

Jitter-Noise and Filter Implementations

The design of a good clock recovery circuit impliesraising its ability to tolerate incoming jitter whilelimiting the jitter it transfers to the next lineinterface. Ifwe consider the clock recovery circuitas an active filter, and if the energy in the basebandsignal is substantial, then a low cost solution canbe realized from lumped parameter networks anda gain-controlled amplifier. Unfortunately, thisapproach suffers from higher transferred jitter,thus requiring dejitterizer circuits, and is a moredifficult design task from a producibility standpoint.Surface Acoustic Wave (SAW) filters are often usedin high speed data circuits because they exhibitexcellent out ofband noise rejection with widebandwidth passband characteristics for good dynamictracking ability. Since they are essentially highQ passive filters, they must be driven and bufferedby amplifiers. Inadequate drive capability anddependence on continuous excitation are theirmajor weaknesses. These devices are also moredifficult to produce in volume due to their highcost and fragile structure. Silicon PLL filtersanswer the call for practical, realizable clock receiversolutions. They exhibit inherently superior drivecapability and may often be integrated with higherdensity logic functions to create application-specificIes that are optimized for a particular line rate and

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function. With careful design, these devices canachieve good frequency stability and out-of-bandjitter rejection characteristics. Superior processtechnology and control is a must in manufacturingofthese devices to avoid sensitivities to powersupply noise, phase offset and false or injectionlocking difficulties.

Slide #9

Jitter Tolerance forSONET/SOH Line Interface

Jitter Tolerance Mask

The JTOL mask is a benchmark ofjitter toleranceperformance against which a solution's actualsensitivity to jitter can be compared. A valueabove the mask is satisfactory, that is more peakpeak jitter is required to induce bit errors in thedata validation process. Bit error rates less thanone in 1010 are generally considered satisfactoryin most applications. However NO occurrence oferrors may the target in the development stagesfor a new product.

Sinusoidal Jitter Input

Source: Bellcore TR-NWT-000253. Fig 5-15

The ordinate axis ofthe JTOL mask is calibratedin unit intervals of sinusoidal jitter. A phasemodulator is typically used to stress a data streamofpredictable pattern. The Unit Interval is arelative measure of phase jitter with respect tothe width of a bit cell at the subject line rate,which for 155.52 Mb/s is 6.43 ns. The sinusoidaljitter is measured at the frequency breakpoints andelsewhere as indicated on the JTOL mask. At eachfrequency of measurement, the level of sinusoidaljitter is increased until an intolerable BER occurs.

15Ulpop -slope =

~~B~~c:._+_~"I I I II I • .I I SIOpel=-20 dB'deoade

0.15UIp-p -l--.J.--r--r----""r-'-_I I

SinusoidalInput 1.5 UlpopJiller

Amplitude(P-p)

10Hz 30 Hz 300 Hz 6500 Hz

Frequency at which Phaae Jitter la Measured

Jitter Tolerance

The Jitter Tolerance (JTOL) specification forreceiver performance is a measure of how muchjitter in a data signal can be tolerated by the clockrecovery circuit before errors in data validationoccur. To assure minimum bit error rate in thepresence of noise, the JTOL must always be greaterthan the worst case transfer jitter.

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Physical Layer Design. Issues for SerialCommwricatio~:ASONETC~eS~dy

Slide '*1.0 Frequency of Jitter Output

Jitter Attenuation for SONET/SOHLine Interface

Jitter Attenuation Characteristics

0.1 dB

JitterGain Any measurements must

fall below the mask

The jitter attenuation is measured at the frequencybreakpoints and elsewhere as indicated on theJitter Attenuation mask. At each frequency ofmeasurement, the level of sinusoidal jitter outputis compared to the input.

Slide #11130,000 Hz

Frequency at which Phase Jitter Is Measured

Source: BeUcore TR-NWT-QOO253, Fig 5-14

Jitter Tolerance/Attenuation TestMethodology

The minimum level ofphase jitter that can beapplied to a data stream without exceeding theBER limit is mapped against frequency andcompared to the JTOL mask. The test requiresmany data points to properly map out the jittertolerated for comparison with the JTOL mask.These tests are frequently repeated in thedevelopment cycle as efforts to improve asolution's jitter tolerance may involve tuningchannel equalizer and loop filter valuAs, adjustingboard layouts and selectine: interface devices forlow loee. A \X1neietent meW1.il for data generation,collection and reporting is needed to expedite thisprocess. The pattern generator is used to generatethe pseudo random bit sequence that must bereceived with :miniIllal bit errors at the receiver.

Pattern + PhaseJitterUI(A)

RecoveredData

DUT

SER Detect10-n

eLK

JitterAttenuation

Jitter Input

Jitter Attenuation

Jitter attenuation is a relative measurementmade at discrete frequencies between the incomingdata stream and that which is clocked back outto the network. The inherent noise level of theclock recovery circuit itself adds statistically to thereceived jitter and becomes part of the transferredjitter ifthere is no elastic store for de-jitterizingthe transmitted pulses. The jitter attenuation ofa clock recovery circuit limits the amount ofjitterpassed to the next line interface when the local clockis used to synchronize the transmitting of serial datato the network

Jitter Attenuation Mask

The Jitter Attenuation mask sets benchmarkperformance in a manner similar to the JTOLmask, however this one sets the maximum levelofjitter allowable at any given SONET networkentity. All measurements must fall below the maskto be ~ceptable.

Sinu(;oidol JHtor Input

The measure ofquality in the Jitter Attenuationtest is gain in dB. For gain to be an attenuation, thevalue rrmst of course be less than unity, as indicatedon the mask.

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Recovered

rPattern ISignal with Minimal Jitter Clock

OUTGen I I1.. __ ----1----

PRBS1'sand D'sONETFrames

RMSJitter

Internal and f (ID)Environmental

in S

RMS Jitter Test Methodology

Slide #12

Device Under Test

A Pseudo Random Bit Sequence (PRBS) is used asthe data pattern to stress the receiver and providea rich source of baseband energy for clock recovery.The input signal is modulated at incrementedfrequencies and at a phase deviation in UIs untilbit errors are detected by the bit error rate tester.A sinusoid is used to simplify the generation andanalysis ofthe phase jitter. The sinusoid frequencyand amplitude are accurately controlled, often bydigital means for repeatability.

NOISe SOurces

The Device Under Test (DUT) is the target receiverwith clock recovery and data validation circuitsactive. It is not necessary to include the framingand alarm functions as they are dependent onthese clock/data processes, however they areimportant and will be tested elsewhere. The derivedclock signal is used by the BER tester (BERT) tosynchronize it to the recovered data outputted bythe DUT. The recovered data signal is analyzed bythe BERT to detect bit slipping resulting from thereceiver's inability to recover or track the desiredclock signal in the presence of sinusoidal jitter.

Bit Error Rate Test

The PRBS is known by the Bit Error RateDetector so it can track the recovered data anddetect bit errors in the data validation process.The level ofBER is often expressed as two or fewererror seconds over a 30 seconds measurementinterval. This related to BER levels ofperformanceslightly more than one error in approximately1010 transmitted bits.

RMS Jitter Measurement

As indicated in the diagram, this is a measurementofjitter transferred from the input to the outputof conformant SONET regenerator. A value ofjitter attenuation is computed for comparison withthe acceptable levels as previously described. TheRMS Jitter instrument is used to measure inputjitter vs output jitter as a function of frequency.The spectrum ofjitter generated by the DUT(and subsequently transferred to the network)provides useful information about noise sourcesand characteristics ofthe clock recovery circuit.These must be analyzed carefully to meet therequirements ofindustry standard organizations.

PRES or Other Pattern Input

The pattern generator is used to generate a cleanPRBS that is tracked with minimal bit errors at thereceiver, in a manner similar to the JTOL test above.

Device Under Test

A test of transferred jitter may requiremeasurement at the recovered data output ofthe receiver, also. This is particularly the casewhen measuring transferred jitter in the presenceofa PRBS data pattern. The RMS jitter spectrummay be measured at the recovered clock if it isaccessible in the receiver design under test.Analysis ofclock noise under stable input conditionsis useful for determining the quality of a receiverimplementation.

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Slide #13

BiCMOS Products forSONET/SDH

• BiCMOS EPIC-liB Process Technology

• ECL/Pseudo-ECl Compatibility

• Proven Architecture

Proven Architecture

TI is considered by most of the majortelecommunications design companies as theleader in high performance, application specificintegrated circuit (ASIC) design and fabrication.The TGBlOOO has been used successfully toimplement dozens ofASIC and complex gate arrayfunctions. TI has introduced a family of Gate Arrayproducts based on this process technology whichrange in complexity up to and beyond lOOK usablegates. In the case of Gate Arrays a triple levelmetalization scheme is used to interconnect this seaof gates. This allows TI to develop a wide variety ofdifferent structures for the logic functionality andperformance requirements of data handling, staticRAM and analog functions that are co-resident on asingle substrate.

EPIC IIB BiCMOS for TDC2302B SONETISDH

The EPIC lIB is a process technology able tointegrate the features of high speed logic, fastFIFO's multiport memory and VCO and chargepump circuitry. TI's BiCMOS approach resultsin low power dissipation/consumption designs, also.This process technology may be used for effectivesolutions for clock recovery, frame alignment,overhead termination and elastic store - astypically required in SONET/SDH applications.

BiCMOS EPIC·llB Process Technology

A TI patented process serves as the foundationfor TI's ABT and LinBiCMOS high speedand intelligent-function logic and linear products.The ABT family allows bipolar device structuresfor tighter, more uniform timing characteristicswhich results in higher speed circuit implementations. CMOS structures realize lower powerimplementations of complex logic functions whichresult in higher density, integratable macro cells.

ECIJPseudo ECL Compatibility

Bipolar Emitter Coupled Logic (ECL) structuresare used to implement non-saturating, high speedtransceivers and data buffers for high data rateinterface. Bridging the gap between ECL structuresand standard TTL I/O, Pseudo ECL (PECL)converters are available. These are referred toVcc instead of ground.

Cost Effective

Although additional processing levels add more costto the BiCMOS technology, systems requiring a highlevel of integration are more cost effective than pureCMOS or Bipolar configurations.

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Physical Layer Design Issues for SerialCommwrlcations: A SONET Case Study

Slide #14

TDC1555 STS-3/STM-1 ClockRecovery Chip

eLK

Data In -I!lIIIIL- -.:::Data=Out~=.:::..-_--{~}

TDC1555

The TDC1555 is a clock and data recovery devicefor use at the 155.52 Mb/s high speed data ratesassociated with SONET and SDH systems. Theclock recovery functions are implemented withanalog PLLs using TI's BiCMOS process technology.This device complements other TI BiCMOS devicesfor complete line interface solutions at the 155.52Mb/s rate. It serves also as the key building blockfor TI's continued development of high density VLSIsolutions for SONET/SDH and ATM applicationsthat meet the jitter attenuation and jitter accommodation requirements of Bellcore SpecificationTA-NWT-000253.

Phase-Locked Loop

The transition detector terminates the incomingdifferential serial data input, slices the level to abinary representation and buffers the signal fordriving the phase/frequency detector. The datainput may be EeL or Pseudo-ECL compatibleand is automatically adjusted. A phase/frequencydetector is used to sample the incoming serial data

and output an error signal to the charge pumpcircuit to maintain the Voltage ControlledOscillator NCO) in synchronism. A frequencyLoss-Of-Lock (LOL) indicator detects when theloop has brought the VCO close to the desiredembedded clock in the incoming serial bitstream. The charge pump and associated loopstabilization filter smooth the error pulses derivedfrom the freq/phase lock detector and outputthe dc voltage sensed by the VCO to modifyits frequency. An external capacitor input isprovided for additional stabilization ifnecessaryto reduce jitter enhancement (peaking) effects.The dc voltage is used to speed up or slowdown the VCO oscillator. This has the effect ofadjusting its clock position within the centralone-third ofbit cell for data validation.

Data Validation Latch

This recovered clock is fed back to the phasedetector and presented to the retiming circuitfor data validation. The recovered clock providesthe decision timing for comparison with theinstantaneous value of the received data. Hencethe timing signal must have very low inherentphase jitter and be well-centered in the middleof the receive window eye pattern for maximumjitter tolerance.

Auxiliary Functions

Although the major function of this device is clockrecovery, a differential PECL to ECL mode bufferis provided for the transmit channel. This isparticularly useful where the framing device doesnot have the capability of interfacing opticaltransmitter circuits requiring the ECL interface.

Packaging Options

The TDC1555 is available in the 24-pin wide-bodysurface mount or dual-in-line packages.

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Physical Layer Design Issues for SerialCommunications: A BONET Case Study

Slide #15

Instrumenting the TDC1555 RMSJitter Test

Bij Error Rate Tester

Digital Storage Scope

Serial TDC1555 SerialL-';:o:=",--+I Clock Recovery I-oa:::::ta:.:::o:...ut......

ala n Chip

OUT Platform

Clock Recovery RMS Jitter Test

RMS Jitter Test

Clock recovery RMS jitter test measuresperformance under different input conditions.This test measures the RMS jitter on the validateddata signal that is correlated with incoming datapattern, whether a PRES of successively increasingextent or of long strings ofzeros or ones. A DSO isused to analyze the waveform and determine theRMS level ofJitter occurring on the sampled signal.

Input Conditions

A serial data stream is generated by the Bit ErrorRate Tester (actually a data pattern generator).The use of the pseudo-random bit pattern providesa consistent means for generating random datapatterns and for exploration of worst case sequencesto stress the clock recovery circuit. The following bitstreams are used: 27-1, 210-1, 215-1, 223-1, 231-1.Strings of"l's" or "O's" are also used to determinewhether the phase detector/charge pump circuitryare able to tolerate jitter with consistent marginwhen stressed at group delay limits. The BERcapability of the pattern generator is also used toensure a sufficiently low error rate condition whenevaluating the RMS jitter level of the clock recoverysystem measured.

Analysis

The HP 71600 Series Error Performance Analyzerconsists of pattern generator, synthesized clocksource, and error detector modules configuredin the HP 75000 modular measurement system.It features standard pseudo-random test patternsup to 231-1 bits long. Complementary clockand data outputs simplify connection to theTDC1555 high-speed logic device, which reducesthe DDT platform design to one ofgood RF practiceand stripline techniques for wiring to/from thesilicon device.

The automatic features ofthe HP 54120B SeriesHigh-Bandwidth Digitizing Oscilloscope (DSO)help make the data collections and statisticalprocessing of data more accurate and repeatable.In this application, the DSO captures the serialoutput data and processes the sample to determineRMS jitter on a bit-cell by bit-cell basis at the linerate of 155 Mb/s, doing so for a variety of inputsignal patterns. The data pattern effects on theinstrumentation are ignored - only the impact ofdata pattern on the data recovery process results.

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Physical Layer Design Issues for Serial

Communications: A SONET Case Study

Slide #16 Analysis

TDC1555 Jitter Tolerance/Attenuation Test

Digital Transmission Analyzer

Serial

Data InTDCl555

Clock RecoveryChip

Serial

DataOul

The automatic features of the DTA help make the

tasks ofdata collection and statistical processing

more efficient for production test environment. The

DTAis capable ofpattem generation and coded

sequences, while also monitoring the data recovery

circuit for occurrences of error "hits." The DTA is

also capable of performing the CCITT 0.171recommended tests using internal filters for

selective jitter measurements.

~ OUT Plallonn

Clock Recovery Jitter TransferfTolerance Test

Jitter Tolerance/Jitter Attenuation Test

This test measures the peak-peak jitter tolerance

and the intrinsic jitter attenuation (transfer) by the

clock recovery system of the TDC1555. The clock

recovery jitter tolerance test measures the level of

input jitter 9.llowable before bit recognition errors

occur due to insufficient eye height or bit slipping inthe PLL. The clock recovery jitter attenuation test

measures the noise and distortion passed to the

reconstructed clock as a result of random and data

correlated jitter response ofthe PLL loop filter. In a

manner similar to the previous RMS Jitter Test, the

DTA generates the data pattern. However unlike

the RMS Jitter test, the DTA also analyzes the RMSjitter on the output data streaIIl and evaluates the

jitter tolerance and jitter attenuation characteristics

as a function of frequency.

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Physical Layer Design Issues for SerialConununications: A SONET Case Study

Slide #17

TDC23028STS-3/STM-1 Line Interface,

Framing and Alarm DetectionFDdIllyL.qoptoack....... --.....,-

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Cod< -- _Cod< """"""'155.5Mb/ll ....... """ _F....,... EctJCMOS Frami'lg

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UNENibble/ByleMode

TERMINAL

SiDERESET SIDe.

HS .....

T....... _

T.......,.."."'"

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1S5.5Mbis on- """""'" "-""'"""""' ""'"

-_.Tel'lTllnal~

TDC2302B

The TDC2302B STS-3/STM-l Line Interface

provides the nibblelbyte framing interface

between the data and clock serial bit stream

of the TDC1555 and the higher layer protocol

decode functions of the attached system. This

device is based on TranSwitch Corporation's

CMOS TXC03201, but utilize TI's high perfonnance0.8 j.l1I1 BiCMOS process technology. Framing

error indication, ifenabled, is also implemented

on this VLSI device.

Receive Channel

The device's main function on the receive channel

is to extract framing synchronization and to convert

the incoming serial information to clock and data

in byte/nibble parallel format. Two synchronization

modes are supported: tracking and non-tracking.

When tracking, the TDC2302B will find the initial

frame and verifY it on successive frames for frame

alignment errors. In the non-tracking mode, it

finds the frame, but no subsequent monitoring of

the signal is provided. Descrambling and Bl parity

detection functions are provided internally to the

TDC2302B ifenabled. The incoming serial data

is monitored at the PECL input to determine

transition density, and a Loss-Of-Signal (LOS)

indication is generated ifbelow the nominal 25 ~s.

When in the tracking mode, the TDC2302B outputs

a Receive Frame Error (RFE), Out-Of-Frame error

(OaF), or Loss-Of-Frame error (LOF) ifframe

alignment errors are found. ECUPECL converters

simplify the connection of external ECL interface

devices to internal CMOS gate structures. Facility

mode loopback is possible which routes line-side

received data to the terminal side and outgoing

transmit channel. This feature is useful for line

side diagnostics.

Transmit Channel

In the transmit mode, the device accepts byte/nibble

data and clock from the terminal side and embeds

a frame synch signal to establish proper timing for

the scrambling and B1 parity generation. These

scrambling and Bl parity generation functions are

provided internally to the TDC2302B ifenabled.

The transmit block nibblelbyte information is

converted to serial data using the receive clockinputted above. This ensures synchronism to the

line side network. Terminal mode loopback is

possible which routes terminal-side transmit data

to the line side and local receive channel. This

feature is useful for terminal side diagnostics.

PEClJECL converters simplifY the connection of

internal CMOS gate structures to external ECL

interface devices.

Packaging Configuration

The TDC2302B is packaged in an 84-pin plastic

leaded chip carrier (PLCC) using 50-mil-pin spacing.

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Slide #18

Instrumenting TDC2302B Interface,Framing and Alarm Test

EJectrk:alJnterfaceE1665ZHP5eries90 •.••

"""'"""",",,'"""'~.Enc:odlngl1-----___.~i8B110B.Ftamel9yteAlignmentSerialtoPatlllel

TnmmItted:

: __ __ .. __ _._~~.~;

Line Interface, Framing and Alarm Test

Here we test the ability of the line interfacedevice's clock, framing and alarm indicationcapability to meet requirements ofANSIT1.105-1991 Bellcore TR-NWT-000253 andCCITT G.708. The test verifies the solution'sability to insert the required parity bits andperform the scrambling! descrambling operationsneeded to build proper SONET/SDH frames.Such tests as frame alignment, payload mapping,pointer generation and analysis are desired.Block data moves are performed by the testinstrumentation to prove that data manipulationis possible at low bit error rate when operatinga terminal side loopback, but external to the linedevice. The Sensitivity ofthe Clock Recovery istested under stress conditions of a PRBS datastream of successively increasing extent, or oflong strings of zeros or ones and the resultingBER is determined. Values of the framing bytesare changed and errors are inserted which forceinternal alarms to indicate the occurrence. Lossof Signal, Loss ofFrame and Out ofFrame alarmsconditions are detected. Other indications such asbit Interleave parity codes and far end block errorare also checked.

Procedure

The HP Series 90 SONET/SDH analyzer isoutfitted by the Electrical Interface and Fibre OpticInterface modules for driving the HP Series 90Interface Board. This Interface Board is used asthe hardware environment for the optical interface,clock recovery and line interface devices. Anexternalloopback is made at the tenninal side ofthe TDC2302B. Procedures for ECL hardwaredesign should be observed in arranging circuitsand instrumentation at the SONET/SDH linerates. (}()od termination practice is required whenpreparing the Interface board testing environment.All terminations are 50-ohm and stripline practicefor 200+ MHz data transmission.

Analysis

The HP Series 90 with associated Fibre Opticor Electrical Interface plug-ins generate a datapattern and receive the reconstructed signal tocompute the Bit Error Rate. Selection is madebetween an optical interface or electrical interfaceto determine the impact of successive stages on thederived BER figure of merit. A PClWindows-baseduser interface loads the interface modules withconformance test suites.

The HP Series 90 Analyzer provides ATM andSONET/SDH measurement capability for testingB-ISDN networks. Use of this test packagesimplifies the generation and analysis of theseserial bit streams and embedded cells. Theflexibility of the Series 90 to support a wide varietyof optical and electrical interfaces and HP-IB remotecontrol makes generation of comprehensive testingsuites practical.

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Slide #19

STS-3c/STM-1 Appl icationUsing TI-TOe Products

ElectroOptic Interface

The TDC components require external translationof the optical serial data. The fiber interfaceconverts the optical input to either an ECL orPseudo ECL level for connection to the TDC1555clock recovery chip.

Clock Recovery

Use of the TDC1555 allows the extraction ofthe155.52 Mb/s clock and retiming validation of thedata for presentation to the TDC2302B LineInterface. The data is still in its serial format,however the extracted clock is needed to interfacethe transmitted information synchronous with theSONET/SDH network.

Synchronization and Framing

The TDC2302B accepts the serial bit stream,decodes the framing synch and handles thescrambling and parity bit detection as describedearlier in this presentation. The decoded bytesare presented to the TDC3003 SONET OverheadTerminator as a parallel interface.

Overhead Termination

The TDC3003 provides section, line and pathoverhead processing on the STS-3/STS-3c/STM-lsignal. It provides additional line AlS, loss ofpointer, path AlS, loss of multiframe, and yellow(path remote) indications. B2 and B3 paritycounting and pointer movements are detected also.Using the framing and clock reference pulses fromthe TDC2302B, this device can determine pointerjustification for the SPE of the STS-3/STM-1 frame.Up to 261 bytes corresponding to one STS-3c/STM-lpayload (plus VC-4 overhead) SPE or three 87 byteSTS-l SPEs are passed to the attached system viathe Local Bus I/O Interface. A similar, but reverseprocess exists in the transmit channel directiongoing back out to the line side.

Local Bus 110 Interface

A typical workstation applications will requireeither an 80 x 86 or 680 x 0 compatible microprocessor interface. The interface provided bythe TDC3003 allows for 10 bits ofaddress and8 bits of data in an interrupt-driven data transferprocess. Alternately, the information may bepassed to another application via a shared memoryarchitecture using an additional DMA controllerand memory interface solution.

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Slide #20

A SONET Case StudyConclusion

• Low cost solutions are required for desktop BISONservices that include interface with SONET payloadenvelopes which may contain ATM packetized data

• User demand for High Bandwidth Line Interface Solutionswill stimulate the introduction of VLSI devices that meetapplicable Bellcore, ANSI and CCITT standards

• Texas Instruments has developed an 0.8 (.l BiCMOSprocess technology that could handle data rates in excessof 1.2 GHz.

• Demonstrating conformance to Industry Standards ismade easier by use of HP Instrumentation. There isconsistency in measurement when data is collected usingthis approach, which allows comparative data analysis.

• There is a DEMO Table that shows the test set updiscussed in this paper.

SONET Networks

Low cost solutions are required for desktopB-ISDN services that include interface withSONET payload envelopes that may containATM packetized data.

Physical Layer Issues

User demand for high bandwidth line interfacesolutions will stimulate the introduction ofVLSIdevices that meet applicable Bellcore, ANSI andCCITT standards.

TDC Components

Texas Instruments has developed a BiCMOSprocess technology that could be used at data ratesup to the GHz range.

Instrumenting for Conformance andPerformance Measurements

Demonstrating conformance to industry standardsis made easier by use ofHP instrumentation.Data collected using this approach is consistent inmeasurement and allows comparative data analysis.

Slide #21

Recommended Resources• Test Equipment

- HP 71603B 3 GHz BERT

_ HP 54120-series High Bandwidth SCope

_ HP 3764A Digital Transmission Analyzer

_ HP 75000 Series 90 SONET/SOH Analyzer

• Integrated Circuit Products

_ TI TOC1555 STS-3/STM·1 Clock Recovery Chip

_ TI TOC2302B ST5-3/STM-1 Line Interface Chip

_ TI TOC3003 SONET/SOH Overhead Terminator Chip

• Evaluation Board

_ TranSwitch TXC-21061 SONET/SOH Eval. Board

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1993 High Speed Digital Design SYlllposium...1993 High Speed Digital Design SYlllposium Fli"Ja...

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