PAL Device Handbook Advanced Micro Devices Monolithic~ ~ nMemoriesuunJJ AWholly Owned Sub.idli"Y 01d ~ n c e d Micro Devke. 24-pin Combinatorial TTl/CMOS PALDevices PRODUCTPINSTECHNOLOGYtpo(ns}Icc(rnA} DESCRIPTIONPAGE AmPAL22XP1024TTL20,30,4090,180,210XOR gate5-271 PAL20S1024TTL35240Product termsteering5-103 AmPAL22P1024TTL15,25105,21024-pinsuperset5-291 Am/PAL20L 1024TTL15,20,25,30105,165,21010 outputs5-113,5-306 PAL20L824TTL,ECMOS15,25,35,450.1,105,210Standard5-122 PAL6L1624TTL2590Wide output5-141 PAL8L1424TTL2590Wide output5-141 PAL12L1024TTL40100Simple combinatorial5-147 PAL 14L824TTL40100Simple combinatorial5-147 PAL16L624TTL40100Simple combinatorial5-147 PAL18L424TTL40100Simple combinatorial5-147 PAL20L224TTL40100Simple combinatorial5-147 PAL20C124TTL40100Simple combinatorial5-147 24-pinRegistered TTL/CMOSPAL Devices PRODUCTPINSTECHNOLOGYfMAX (MHz) Icc (rnA) DESCRI PTIONPAGE AmPALC29MA 1624EE CMOS20,15120Advanced Async.Macro5-209 AmPALC29M1624EE CMOS20,15120AdvancedMacrocell5-231 PAL32VX1024TTL25,22180J-K,varied terms5-70 Am/PAL22V1024TTL,ECMOS40,33,28.5, 20,1890,180Versatile5-79,5-249 PAL22RX824TTL28.5210J-K flip-flops5-87 PAL20RA1024TTL20200Asynchronous5-95 AmPAL20XRP1024TTL30,22,14105,180,210XOR gate & polarity5-271 AmPAL20XRP824TTL30,22,14105,180,210XOR gate& polarity5-271 AmPAL20XRP624TTL30,22,14105,180,210XOR gate& polarity5-271 AmPAL20XRP424TTL30,22,14105,180,210XOR gate& polarity5-271 PAL20RS1024TTL20240Product termsteering5-103 PAL20RS824TTL20240Product termsteering5-103 PAL20RS424TTL20240Product termsteering5-103 PAL20X1024TTL22180XOR gate5-113 PAL20X824TTL22180XORgate5-113 PAL20X424TTL22180XORgate5-113 AmPAL20RP1024TTL37,25105,210Programmable polarity5-291 AmPAL20RP824TTL37,25105,210Programmable polarity5-291 AmPAL20RP624TTL37,25105,210Programmable polarity5-291 AmPAL20RP424TTL37,25105,210Programmable polarity5-291 PAL20R824TTL,E CMOS37,25,20,150.1,105,210Standard5-122 PAL20R624TTL,ECMOS37,25,20,150.1,105, 210Standard5-122 PAL20R424TTL,E CMOS37,25,20,150.1,105,210Standard5-122 PAL32R1640TTL16280MegaPALTMdevice5-158 (Continued onback cover) IPAL Device Handbook Introduction Applications PAILDevice Data Book Programming. andQuality PALASM 2 Software User Documentation Data Sheets Appendices 1988 AdvancedMicro Devices,Inc. AdvancedMicro Devices reserves theright tomake changes inits products without notice in order toimprove designor performance characteristics. The performance characteristics listed inthis document are guaranteed by specific tests, correlated testing,guard banding, design and other practices common to theindustry. For specific testing details contact your local AMDsales representative. The company assumes noresponsibility for the use of any circuits described herein. 901ThompsonPlace,P.O.Box 3453,Sunnyvale,California 94088 (408)732-2400 TWX:910-339-9280 TELEX: 34-6306 ii In late 1987, the two programmable logic market leaders, Monolithic Memories and Advanced Micro Devices, merged into one great company.We combined our strong traditions of customer service andinnovationtooffer youthebestlineofprogrammablelogic devices.The1988 DataBook presentsthetechnicalspecificationsontheentireproductline.Theseparate1988 Handbook presentsallofthenecessarysupportmaterial,whetheryouareaccustomedtousingMMIor AMDproducts. AMD/MMIhas the products, manufacturing capacity and technology to perpetuate theleadership in the programmable logic field which we pioneered.In the1988 Data Book you will notice that we notonlyhavethebroadestprogrammablelogicline,butwealsohavetheindustry'smost comprehensiveCMOSprogrammablelogic line.Wethink thatyouwillfindtheData Bookand Handbookinformativeanduseful.Ifyouhaveanycommentsor questionsonthe books or the product line, please contact us. Cyrus Tsui VicePresident Programmable Logic Division MonollthlcW Memories Description This1988 PAL DeviceHandbook/Data Book isyour completeguide toall programmablelogic devices (PLDs) fromMonolithic Memories and Advanced Micro Devices.The merger of the two companies provides a greater wealth of products and services for you.Note that all PLDs which werein productionbefore the merger are still being produced. The PAL Device Handbook/Data Book is organized into two volumes and six easy-to-use sections: PAL Device Handbook Section 1: Introduction Includes anoverview of thePLD product family. Section 2: Applications Includes detailed application examples.The first few chapters provide tutorials inPLD design. The applicationnotes are grouped by applicationarea. PAL Device Data Book Section 3:Programming and Quality Includes information on PLD software programs, programming information, PLD technology and quality discussions, and package information. Section 4: PALASM 2 Software User Documentation Includes complete documentation for PALASM 2 software. Section 5: Data Sheets Includes specifications for all PLDs from the combined company.PAL devices formerly from MMI areunder "PAL Devices," whilePAL devices formerly from AMD are under "AmPAL Devices." Section 6: Appendices Includes quick referenceinformation. If you have any questions or comments on PLDs or any other products, please contact your most convenient AMD/MMI sales office,listed at the end of eachbook. Monolithic mMemories iii Major Contributors Marc Baker RichChin Arthur Khu Cindy Lee RonFritz Scott Graham Alexandra Huff Chris Jay MitchKane David Lee WarrenMiller BryonMoyer Bernadette Olson Nick Schmitz David Selby KapilShankar MaltiSwamy Laurie Taylor John Turner EdValleau Phil Watt Trademarks PALIEl,HALIEl,PALASMIEl,andSKINNYDIP areregisteredtrade-marks of Monolithic Memories,Inc. ProPAL'N,MegaPAL'N, ZPAL'N,MegaHAL'N,ZHAL'N,PLE'N, PLEASM'N,DOC'N,Diagnostics-On-Chip'N,PROSE'N,MONOX'N, HiPAC'N,andAutoVec'Nare trademarksof Monolithic Memories,Inc. IMOxmand SSR'Naretrademarks of AdvancedMicroDevices. Xilinx,XACT""',XACTOR'N,LogicCell Array'N,andLogic Processor1M are trademarks of Xilinx Inc. P-SILOS'Nis a trademark of SimuCad. IBM is a registered trademark of InternationalBusinessMachines Corporation. MicroChannelThl, IBM-PC'N,PC-XT""',andPC-AT"'"are trademarks ofInternationalBusinessMachinesCorporation. Data1I01El is a registered trademark of Data 1/0 Corporation. ABELThI,PLDtest,UniSite'N,LogicPak,LogicFingerprintThf, and PROMlink1M aretrademarksof Data 1/0 Corporation. FutureNet is a registered trademark of FutureNet,a Data 1/0 Company. DASHThf,DASH-ABELThI,DASH-GATESThf,PLD-CADAT""',and DASH-CADAT-PLUSThfaretrademarks of FutureNet,a Data 1/0 Company. CUPLThIis a trademark of Personal CAD Systems. MultibusThf isa trademark of IntelCorporation. ISDATA isa registered trademark ofISDATA GmbH. LOG/iCThfis a trademark ofISDATA GmbH. Apollo isa registered trademark of ApolloComputer. Q-Bus,UNIBUS,VAX,and VMS areregisteredtrademarks of DigitalEquipment Corporation. Microsoft is a registered trademark of Microsoft Corporation. MS-DOSThfisa trademark of Microsoft Corporation. UNIXThfisa trademark of AT&T Technologies,Inc. DAISY andDNIX areregisteredtrademarks ofDaisySysiems. SOFTPACKThI,SOFTLlNKTM,andLOGILlNK'Naretrademarksof Digelec,Inc. ALLPROThlandLOGIPROTMaretrademarksof LogicalDevices,Inc. PROMACThfis a trademark of JapanMacnicsCorporation. WordStarisa trademark of MicroProInternationalCorporation. Mouse SystemThf is a trademark of Mouse SystemsCorporation TestPLAThfis a trademark of StructuredDesign,Inc. NuBusThl is a trademark of TexasInstruments iv Monolithic W Memories Table of Contents PAL Device Handbook Introduction I nt rod uct10 n .............................................................. " ............................ " ........................... ,........................... ................................. ....1-1 What isa PLD? ...............................................................................................................................................................................1-1 What Advantages do PLDs Have Over Other Implementations? .................................................................................1-4 Product Overview ............................................................................................................" .......................................................... " ...1-7 PAL Devices "".".. "".".. "".".. "".".".".. "".".".".".".".. ".""."."."................................................................ " ........................... ,.....1-7 Nomenclature .............................................................................................................................................................................,.....1-7 Programmable Seq uencers .................................................... "...............................................................................................1-19 LCA Devices ......................................................... ,.....................................................................................................................".1-20 Applications Beginner's Guide ."."." .. ""."."."."."."." .. "".".".".".".".".""".""."." .......................................................... " ........................... ,.....2-1 Constructing a Combinatorial Design .................................................................... " ...............................................................2-2 Constructinga RegisteredDesign...........................................................................................................................................2-9 Programming a Device..............................................................................................................................................................2-14 PLDDesi g n Methodology .........................................................................................................................................................2-21 Conceptualizing a Design ......................................................................................................................................................... 2-22. Device SelectionConsiderations ...........................................................................................................................................2-23 Implementing a Design ..............................................................................................................................................................2-26 Simulation .......................................................................................................................................................................................2-30 Device Programming and Testing ..........................................................................................................................................2-33 Combinatorial Logic Design ...................................................................................................................................................2-35 Encoders and Decoders ..............................................................................................,.............................................................2-35 Multiplexers ..................................................................................................................................................." ...............................2-43 Comparators ...............................................................................................................................................................................".2-45 Range Decoders .......................................................................................................................................................................... 2-52 Adders/Arithmetic Circuits ........................................................................................................................................................2-53 Latches ............................................................................................................................................................................................2-58 Registered Logic Design ..........................................................................................................................................................2-61 Binary Counters ............................................................................................................................................................................2-67 Modulo Counters ..........................................................................................................................................................................2-75 Gray-Code Counters ................................................................................................................................................................".2-87 Johnson Counters ........................................................................................................................................................................2-88 Shift Registers ...............................................................................................................................................................................2-90 Asynchronous RegisteredDesigns .......................................................................................................................................2-94 Monollthlo lAin Memories v Table of Contents State Machine Design ...............................................................................................................................................................2101 State Machine Theory ..............................................................................................................................................................2103 State Machine Types: Mealy & Moore ...............................................................................................................................2105 Device Selection Considerations .........................................................................................................................................2107 PAL Devices as Sequencers ..................................................................................................................................................2111 Programmable Logic Sequencers (PLS)..........................................................................................................................2117 PROSE Sequencer (PMS 14R21) ........................................................................................................................................2120 Fuse Programmable Controller (Am29PL141) ...............................................................................................................2121 State Machine Design Tutorial ..............................................................................................................................................2122 Microprocessor-Based Systems ......................................................................................................................................2131 Interfacing to the8086/80186/80286 .................................................................................................................................2134 8086 and Am7990 LANCE Interface .........................................................................................................................2135 8086 and Am9516 Universal DMA Controller Interface .....................................................................................2138 80286 to Am9568 Data Ciphering Processor Interface ......................................................................................2143 80286 to Am8530 Interface ...........................................................................................................................................2147 Interfacing to the68000/68020 .............................................................................................................................................2149 The 68000 and Am8530Interface withInterrupts ................................................................................................2150 68000 and Am7990 LANCE Interface .......................................................................................................................2153 68000 to AmZ8068 Data Ciphering Processor Interface ...................................................................................2155 68000 andDual Am9516 DMAControliers Interface ..........................................................................................2159 Am8530 to68020Interface ..........................................................................................................................................2162 Interfacing to the8088 .............................................................................................................................................................2165 8088 toAm9516 UDC Interface ..................................................................................................................................2166 80186 to Am9516 Universal DMA Controller Interface ...... ;.........................................................................................2170 68000Interrupt Controller ...................................................................................................................................................... 2172 Memory Control ............................................................................................................................................................................ 2179 Memory Handshake Logic .....................................................................................................................................................2184 Customize a DRAMController Using Advanced PAL Devices .................................................................................2187 8088 to Am2968Interface ......................................................................................................................................................2202 MC68000 to Am2968Interface .............................................................................................................................................2210 GeneralPurpose DualPort Arbiter .....................................................................................................................................2215 Dynamic Memory Control State Sequencer ....................................................................................................................2224 8Bit Error Detection andCorrection ..................................................................................................................................2229 Fuse Programmable Controller Simplifies Cache Design ..........................................................................................2239 PAL22RX8A Provides Controland Addressing for a 32LocationDeep RAMBasedLIFO ..........................2250 Graphics and Image Processing Systems .................................................................................................................2257 Small System Video Controller ............................................................................................................................................. : 2261 PAL32VX10 Uses BuriedRegister for Input Intensive State Machine Designs .................................................2275 Digital Signal Processing .......................................................................................................................................................2283 Waveform Generator ................................................................................................................................................................2286 PAL32VX10 Uses BuriedRegister for Inputlntensive State Machine Designs .................................................2292 Analog toDigital Conversion .................................................................................................................................................2297 PAL Devices,PROMs, FIFOs andMultipliers Teamup to Implement SingleBoard HighPerformance Audio Spectrum Analyzer ................................................................2307 Bus Interface ...................................................................................................................................................................................2325 Unibus Interrupt Controller .....................................................................................................................................................2328 A MULTIBUS Arbiter Design for 10 MHz Processors ...................................................................................................2333 MULTIBUS to Am9516 Interface ..........................................................................................................................................2338 ZBUS and 8088/8086Interface ..........................................................................................................................................2342 VMEBus Control Simplified withPLDs .............................................................................................................................2347 vi Monollthlo W MemorIes Table of Contents Communications .......................................................................................................................................................................... 2-357 B8ZS CodingUsing CMOS ZPAL Devices ......................................................................................................................2-362 HDB3 Line CodingUsingPAL Devices .............................................................................................................................2-384 ZPAL Devices Implement D4 Frame Synchronization .................................................................................................2-404 T1Extended Superframe Provides TransmissionError Detection.........................................................................2-431 TimeDivision Multiplexingwith the LCA Device ............................................................................................................2-435 LCA Device Implements an8-Bit Format Converter inaPBX Switching Module ............................................2-444 Serial Data Link Controller .....................................................................................................................................................2-453 OAMEncoder ina ZPAL Device ..........................................................................................................................................2-456 PAL Devices Implement the Full V.32ConvolutionEncoder .....................................................................................- 2-463 PLD DevicesImplement 4B3T Line Transcoder ............................................................................................................2-475 PALC22V10 Creates Manchester Encoder Circuit .......................................................................................................2-499 Peripheral Design ........................................................................................................................................................................ 2-507 Building anESDI Translator Using theM2064 Logic Cell Array ..............................................................................2-509 Writinga TapeDriveController inPROSE .......................................................................................................................2-519 GCR (4B-58) Encoder/Decoder ...........................................................................................................................................2-541 Industrial Control ......................................................................................................................................................................... 2-547 Stepper Motor Controllers ......................................................................................................................................................2-550 Shaft Encoders ........................................................................................................................................................................... 2-558 Military Applications ..................................................................................................................................................................2-579 Radiation Hardness ..................................................................................................................................................................2-581 Article Reprints Programmable Logic Device PreservesPins,Product Terms(PAL32VX1 0) ......................................................2-589 PLD ProgrammabilityExtends its Sway Over Complex 1/0(PALC29M/MA16) .................................................2-593 PROSE Devices Simplify StClteMachine Design(PMS14R21) ...............................................................................2-601 Designing a State Machine witha Programmable Sequencer (PMS14R21) ......................................................2-607 FPCs andPLDs Simplify VMEBusControl (Am29PL141) ........................................................................................2-619 Fuse-Programmable Chip Takes Commandof Distributed Systems (Am29PL141) ........................................2-633 PAL Device Buries Registers,Brings StateMachines to Life(AmPAL23S8) ......................................................2-639 ProgrammableEvent Generator Conquers TimingRestraints(Am2971) ............................................................2-644 Wait-State Remover Improves SystemPerformance(PAL22V1 0) .........................................................................2-648 PLDs Implement EncoderlDecoder for Disk Drives (PAL22V1 0)............................................................................2-651 MixingData Paths Expands Options in SystemDesign (PAL22V10) ....................................................................2-660 Programmable Logic Chip i v a l ~ Gate ArraysinFlexibility (PAL22V10) .............................................................2-670 XOR PLDs Simplify Design of Counters and Other Devices (PAL20X1 0) ...........................................................2-676 The PAL20RA 10 Story -The Customization ofa StandardProduct (PAL20RA 10) ........................................2-683 PLDs Abound:RAM-BasedLogic Joins In .......................................................................................................................2-699 Introduction to Programmable Array Logic .......................................................................................................................2-702 Logical Alternativesin Supermini Design ..........................................................................................................................2-711 Conference Proceedings New PAL Device Architecture Extends Design Flexibility (PAL32VX10)..............................................................2-719 PROSE Architecture andDesign Methodology (PMS14R21 ) ...................................................................................2-724 Blazing Fast PAL DevicesEnable New Application Areas(PAL 16R8-1 0,PAL 1OH20P/G8).........................2-730 Sales Offices ...................................................................................................................................................................................2-740 ~ Monolithic W Memories ~ vii Table of Contents PAL Device Data Book Programming and Quality Design Software for Programmable Logic .........................................................................................................3-1 PALASM 2 Logic DesignSoftwarePackage ........................................................................................................................3-5 PLPL:ProgrammableLogic ProgrammingLanguage ......................................................................................................3-7 Logic Cell Array andDevelopment Systems ......................................................................................................................3-21 ABEL-GATES ................................................................................................................................................................................3-35 CUPL ................................................................................................................................................................................................ 3-43 LOG/iC .............................................................................................................................................................................................3-66 Programming .....................................................................................................................................................................................3-76 Programmer Reference Guide ................................................................................................................................................3-81 ProPAL,HAL and ZHAL DevicesProgram ......................................................................................................................3-104 Testability ..........................................................................................................................................................................................3-108 Designing TestableCombinatorial Circuits......................................................................................................................3-109 Designing Testable Sequential Circuits.............................................................................................................................3-114 Designing Testable StateMachines ....................................................................................................................................3-118 Designing for Testability withthePROSE Device.........................................................................................................3-123 Using TestVectors .................................................................................................................................................................... 3-128 Technology andQuality MONOX 3 Oxide-IsolatedProcess .....................................................................................................................................3-130 Prod uct Ass u rance .................................................................................................................................................................... 3-132 Test andFinish Operations ....................................................................................................................................................3-138 IMOX Product Technology and Reliability ........................................................................................................................3-140 IMOX Product Reliability ................................................................................................................................................3-141 IMOX Product Testability............................................................................................................................................... 3-144 ECL Technology ......................................................................................................................................................................... 3-150 CMOSHiPAC Technology ......................................................................................................................................................3-155 CMOSEE Technology .............................................................................................................................................................3-159 Latchup inCMOS IntegratedCircuits ................................................................................................................................3-160 Metastability .................................................................................................................................................................................3-164 Packaging SurfaceMount Technology....................................................................................................................................................3-170 PAL DevicePackage Outlines ..............................................................................................................................................3-179 PAL DevicePackage Thermal Characteristics ...............................................................................................................3-208 AmPAL Device Package Outlines .......................................................................................................................................3-224 AmPAL DevicePackage Thermal Characteristics ........................................................................................................3-231 PALASM2Software User Documentation Introduction .......................................................................................................................................................................................... 4-1 Install PALASM 2 Software ......................................................................................................................................................4-15 Run the Software ............................................................................................................................................................................4-29 Build a BooleanEquation Design .......................................................................................................................................4-61 Build a State Machine Design ...............................................................................................................................................4-95 Build Simulation ...........................................................................................................................................................................4-137 Program the Device ....................................................................................................................................................................4-169 PALASM 2 Software Glossary ............................................................................................................................................4-183 PALASM 2 Software Index .....................................................................................................................................................4-189 vi i i Monolithic W Memories l1 Table of Contents Data Sheets PAL/PLD Device Menu ...............................................................5-3 TTL/CMOS PAL Devices ...........................................................5-9 PAL16RA8..................................................................................5-11 PAL 16RP8A Series .................................................................5-17 PAL16P8A PAL16RP8A PAL16RP6A PAL16RP4A PAL 16R8 Family ................................................................................5-26 PAL 16R8D Series ....................................................................5-29 PAL16L8D PAL16R8D PAL16R6D PAL16R4D PAL 16R88 Series ....................................................................5-31 PAL16L88 PAL16R88 PAL16R68 PAL16R48 PALC16R80-25 Series ..........................................................5-33 PAL 16L80-25 PAL 16R80-25 PAL 16R60-25 PAL 16R40-25 PAL 16R88-2 Series ................................................................5-35 PAL16L88-2 PAL16R88-2 PAL16R68-2 PAL16R48-2 PAL 16R8A Series ....................................................................5-37 PAL16L8A PAL16R8A PAL16R6A PAL16R4A PAL 16R88-4 Series ................................................................5-39 PAL16L88-4 PAL16R88-4 PAL16R68-4 PAL16R48-4 PAL 16R8A-2 Series ................................................................5-41 PAL16L8A-2 PAL16R8A-2 PAL16R6A-2 PAL16R4A-2 PAL 16R8A-4 Series ................................................................5-43 PAL16L8A-4 PAL16R8A-4 PAL16R6A-4 PAL16R4A-4 PALC16R8Z-25 Series ...........................................................5-50 PAL 16L8Z-25 PAL 16R8Z-25 PAL 16R6Z-25 PAL16R4Z-25 PAL 16X4 .....................................................................................5-51 PAL 1 OH8Series .......................................................................5-56 PAL10H8 PAL12H6 PAL14H4 PAL16H2 PAL16C1 PAL10L8 PAL12L6 PAL14L4 PAL16L2 PAL32VX10A .............................................................................5-70 PAL32VX10 ................................................................................5-70 PALC22V1 OH-25 ......................................................................5-79 PALC22V1 OH-35 ......................................................................5-79 PAL22RX8A ...............................................................................5-87 PAL20RA 10-20 .........................................................................5-95 PAL20RA10 ................................................................................5-97 PAL20RS10 Series ...............................................................5-103 PAL20S10 PAL20RS10 PAL20RS8 PAL20RS4 PAL20X10A Series ................................................................5-113 PAL20L10A PAL20X1OA PAL20X8A PAL20X4A Monolithic W Memories ix Table of Contents PAL20RS Family .............................................................................5-122 nUCMOS AmPAL Devices ..............................................5-167 x PAL20RS8 Series ..................................................................5-125 PAL20LS8 PAL20RS8 PAL20R68 PAL20R48 PAL20RS8-2Series ..............................................................5-126 PAL20LS8-2 PAL20RS8-2 PAL20R68-2 PAL20R48-2 PAL20RSA Series ..................................................................5-12S PAL20LSA PAL20RSA PAL20R6A PAL20R4A PAL20RSA-2 Series ..............................................................5-130 PAL20LSA-2 PAL20RSA-2 PAL20R6A-2 PAL20R4A-2 PALC20RSZ-35 Series ........................................................5-133 PALC20LSZ-35 PALC20RSZ-35 PALC20R6Z-35 PALC20R4Z-35 PALC20RSZ-45 Series ........................................................5-133 PALC20LSZ-45 PALC20RSZ-45 PALC20R6Z-45 PALC20R4Z-45 PAL6L16A ................................................................................5-141 PAL8L14A ................................................................................5-141 PAL12L10 Series ...................................................................5-147 PAL12L10 PAL14LS PAL16L6 PAL1SL4 PAL20L2 PAL20C1 PAL32R16 ................................................................................5-15S GeneralInformation ..............................................................5-164 AmPAL23SS-20 ......................................................................5-169 AmPAL23SS-25 ......................................................................5-169 AmPAL16RSFamily ......................................................................5-1S4 AmPAL 16RSD Series ...........................................................5-1S3 AmPAL16LSD AmPAL16RSD AmPAL16R6D AmPAL16R4D AmPAL 16RS8 Series ...........................................................5-197 AmPAL16LS8 AmPAL16RS8 AmPAL16R68 AmPAL16R48 AmPAL 16RSAL Series........................................................5-197 AmPAL 16LSAL AmPAL16RSAL AmPAL 16R6AL AmPAL 16R4AL AmPAL 16RSA Series ...........................................................5-197 AmPAL16LSA AmPAL16RSA AmPAL16R6A AmPAL16R4A AmPAL 16RSO Series..........................................................5-197 AmPAL16LSO AmPAL16RSO AmPAL16R60 AmPAL16R40 AmPAL 16RSL Series....................................................................5-197 AmPAL16LSL AmPAL16RSL AmPAL16R6L AmPAL16R4L AmPAL 16RS Series ..............................................................5-197 AmPAL16LS AmPAL16RS AmPAL16R6 AmPAL16R4 AmPAL 1SPS8 .........................................................................5-202 AmPAL1SPSAL .......................................................................5-202 AmPAL 1SPSA .........................................................................5-202 AmPAL 1SPSO .........................................................................5-202 AmPAL1SPSL ..........................................................................5-202 Monolithic W Memories Table of Contents AmPALC29MA16-35 ............................................................5-209AmPAL20RP10A Series .....................................................5-306 AmPALC29MA16-45 ............................................................5-209AmPAL22P10A AmPALC29M16-35 ...............................................................5-231AmPAL20RP10A AmPALC29M16-45 ...............................................................5-231AmPAL20RP8A AmPAL20RP6A AmPAL22V10-15 ...................................................................5-249 AmPAL20RP4A AmPAL22V1 OA .......................................................................5-260 AmPAL22V10 ..........................................................................5-260 AmPAL20L 108 ..............................................................5-306 AmPAL20L 10-20 ...........................................................5-306 AmPAL20XRP10Family ..............................................................5-271 AmPAL20L10AL ............................................................5-306 AmPAL20XRP10-20Series ...............................................5-286 AmPAL22XP10-20 PROSE/PlS Sequencers ....................................................5-313 AmPAL20XRP10-20 PMS14R21 A ............................................................................5-315 AmPAL20XRP8-20 PMS14R21 ...............................................................................5-315 AmPAL20XRP6-20 AmPAL20XRP4-20PLS167-33 ...............................................................................5-331 AmPAL20XRP10-30L Series............................................5-286PLS168-33 ...............................................................................5-331 AmPAL22XP 10-30LPLS105-37 ...............................................................................5-331 AmPAL20XRP10-30L AmPAL20XRP8-30L FPC/PEG Sequencers ...........................................................5-337 AmPAL20XRP6-30L Am29PL141FuseProgrammable Controller ..............5-339 AmPAL20XRP4-30L Am2971Programmable Event Generator ....................5-365 AmPAL20XRP10-30Series ...............................................5-286 AmPAL22XP10-30 ECl PAL Devices .....................................................................5-379 AmPAL20XRP10-30 PAL 10020EV IEG8 .................................................................5-381 AmPAL20XRP8-30 PAL 1OH20EV/EG8 ................................................................5-381 AmPAL20XRP6-30 PAL 1OH20G8 ..........................................................................5-382 AmPAL20XRP4-30 PAL 1OH20P8 ...........................................................................5-386 AmPAL20XRP1 0-40L Series............................................5-286 AmPAL22XP10-40L AmPAL20XRP10-40L AmPAL20XRP8-40L HAllZHAl Devices .................................................................5-391 ZHAL20A Series ....................................................................5-394 ZHAL24A Series ....................................................................5-401 AmPAL20XRP6-40L AmPAL20XRP4-40L Military PAL Devices ..............................................................5-415 Introduction ..............................................................................5-417 AmPAL20RP10Family .................................................................5-291 AmPAL20RP1 08 Series.....................................................5-306 AmPAL22P108 AmPAL20RP108 AmPAL20RP88 AmPAL20RP68 AmPAL20RP48 Military PAUPLDDevice Menu........................................5-418 Military 20-pinPAL Devices ...............................................5-421 Military 24-pinPAL Devices ...............................................5-439 DC/AC Parametric Testing .................................................5-469 JAN 38510 andStandardMilitaryDrawings ................5-470 Military Screening ..................................................................5-474 Quality Programs ...................................................................5-477 AmPAL20RP1 OALSeries ...................................................5-306 AmPAL22P1 CAL logic Cell Array ........................................................................5-481 M2064 ........................................................................................5-483 AmPAL20RP10AL M2018 ........................................................................................5-483 AmPAL20RP8AL AmPAL20RP6AL Military M2064/M2018 .........................................................5-518 AmPAL20RP4AL Electrical Definitions .............................................................5-531 Monolithic W Memories xi Table of Contents Appendices Logic Reference ........................................................................................................................................................................6-1 Basic Logic Elements ...........................................................................................................................................................6-1 Basic Storage Elements ......................................................................................................................................................6-8 Binary Numbers ...................................................................................................................................................................6-15 Sig nalPolarity .........................................................................................................................................................................6-19 Glossary .......................................................................................................................................................................................6-24 Competitive Cross-Reference ......................................................................................................................................6-30 Worldwide Application Support ..................................................................................................................................6-40 Sales Offices .............................................................................................................................................................................6-41 xii Monolithic mil] Memories Alphanumeric Product Index Am29PL1415-339AmPAL20XRP4-40L5-286PAL16L25-56PAl20R8A-25-130 Am29715-365AmPAL20XRP6-205-286PAL16L65-147PAl20R885-125 AmPAl16L85-197AmPAL20XRP6-30L5-286PAL16L8D5-29PAl20R88-25-126 AmPAL16L8A5-197AmPAL20XRP6-305-286PAL16L8A5-37PAl20RA105-97 AmPAL16L8AL5-197AmPAL20XRP6-40L5-286PAL16L8A-25-41PAl20RA10-205-95 AmPAL16L885-197AmPAL20XRP8-205-286PAL16L8A-45-43PAl20RS105-103 AmPAL16L8D5-183AmPAL20XRP8-30L5-286PAL16L885-31PAl20RS45-103 AmPAL16L8L5-197AmPAL20XRP8-305-286PAL16L88-25-35PAl20RS85-103 AmPAL16L805-197AmPAL20XRP8-40L5-286PAL16L88-45-39PAl20S105-103 AmPAl16R45-197AmPAL20XRP10-205-286PAL16P8A5-17PAl20X4A5-113 AmPAl16R4A5-197AmPAL20XRP1 0-30L 5-286PAL16R4D5-29PAl20X8A5-113 AmPAL16R4AL5-197AmPAL20XRP10-305-286PAL16R4A5-37PAl20X10A5-113 AmPAL16R485-197AmPAL20XRP1 0-40L 5-286PAL16R4A-25-41 AmPAL16R4D5-183PAL16R4A-45-43PAl22RX8A5-87 AmPAL16R4L5-197AmPAL22P10A5-306PAL16R485-31 AmPAl16R405-197AmPAL22P10AL5-306PAL16R48-25-35PAL32R165-158 AmPAL16R65-197AmPAL22P1085-306PAL16R48-45-39PAL32VX105-70 AmPAL16R6A5-197AmPAL22V105-260PAL16R6D5-29PAL32VX10A5-70 AmPAL 16R6AL5-197AmPAL22V10-155-249PAL16R6A5-37 AmPAl16R685-197AmPAL22V10A5-260PAL16R6A-25-41PAL10020EV/EG85-381 AmPAL16R6D5-183AmPAL22XP10-205-286PAL16R6A-45-43 AmPAL16R6L5-197AmPAL22XP10-30L5-286PAL16R685-31PALC 16LSO-255-33 AmPAL16R605-197AmPAL22XP10-305-2S6PAL16R68-25-35PALC16L8Z-255-50 AmPAl16R85-197AmPAL22XP10-40L5-2S6PAL16R68-45-39PALC16R40-255-33 AmPAl16R8A5-197PAL16R8D5-29PALC16R4Z-255-50 AmPAL 16RSAL5-197AmPAl23S8-205-169PAL16R8A5-37PALC16R60-255-33 AmPAl16RS85-197AmPAL23SS-255-169PAL16RSA-25-41PALC16R6Z-255-50 AmPAL16RSD5-183PAL16RSA-45-43PALC16RSO-255-33 AmPAL16RSL5-197AmPALC29M16-355-231PAL16RS85-31PALC16RSZ-255-50 AmPAL16R805-197AmPALC29M 16-455-231PAL16RS8-25-35PALC20L8Z-355-133 AmPALC29MA 16-355-210PAL16R88-45-39PALC20R4Z-355-133 AmPAL18P8A5-202AmPALC29MA 16-455-210PAL16RA85-11PALC20R6Z-355-133 AmPAL18P8AL5-202PAL16RP4A5-17PALC20R8Z-355-133 AmPAL18P885-202M20185-483PAL16RP6A5-17PALC20L8Z-455-133 AmPAl18P8L5-202M20645-483PAL16RP8A5-17PALC20R4Z-455-133 AmPAL18P805-202PAL16X45-51PALC20R6Z-455-133 PAL6L16A5-141PALC20R8Z-455-133 AmPAl20L 1OAL5-306PAL8L14A5-141PAL1SL45-147PALC22V10H-255-79 AmPAl20L1085-306PALC22V10H-355-79 AmPAl20L 10-205-306PAL10H85-56PAL20C15-147 AmPAl20RP4A5-306PAL10H20G85-382PAL20L25-147PLS105-375-331 AmPAl20RP4AL5-306PAL 1OH20EV/EG85-381PAL20L10A5-113PLS167-335-331 AmPAl20RP485-306PAL10H20P85-3S6PAL20L8A5-12SPLS168335-331 AmPAl20RP6A5-306PAL10LS5-56PAL20L8A-25-130 AmPAl20RP6AL5-306PAL20L885-125PMS14R215-315 AmPAl20RP685-306PAL12H65-56PAL20LS8-25-126PMS14R21A5-315 AmPAl20RPSA5-306PAL12L65-56PAL20R4A5-12S AmPAl20RPSAL5-306PAl12L105-147PAL20R4A-25-130 AmPAl20RPS85-306PAL20R485-125 AmPAl20RP10A5-306PAL14H45-56PAL20R48-25-126 AmPAl20RP10AL5-306PAL14L45-56PAL20R6A5-12S AmPAl20RP1085-306PAL14LS5-147PAL20R6A-25-130 AmPAl20XRP4-205-2S6PAL20R685-125 AmPAl20XRP4-30L5-2S6PAL16C15-56PAL20R68-25-126 AmPAl20XRP4-305-2S6PAL16H25-56PAL20R8A5-128 MonolithIc mMemorIes xiii Notes xiv Monolithic WMemorles PAL Device Handbook PAL Device Data Book Introduction Applications ... 1i Table of Contents Introduction ..........................................................................................................................................................................................1-1 Whatis aPLD? ...............................................................................................................................................................................1-1 What Advantages doPLDsHave Over Other Implementations? .................................................................................1-4 Product Overview .............................................................................................................................................................................1-7 PAL Devices .....................................................................................................................................................................................1-7 Nomenclature ...................................................................................................................................................................................1-7 Programmable Sequencers .....................................................................................................................................................1-19 LeA Devices ..................................................................................................................................................................................1-20 1ii Monolithic W Memories Introduction The Programmable ArrayLogic device, commonly known as the PALdevice, was invented at Monolithic Memories over 12 years ago.The concept forthis revolutionary type of device sprang forth asa simple solution to the shortcomings of discrete TTL logic. ThesuccessfullyprovenPROMtechnologywhichallowedthe enduser to"writeonsilicon"providedthetechnologicalbasis which made this kind of device not only possible, but very popular as well. The availability of design software made it much easierto design withprogrammablelogic.Asdesignerswerefreedfromthe drudgeryoflow-levelimplementationissues,new complexde-signs wereeasier toimplement,andcouldbecompletedmore quickly. This chapter outlines some basic information essential to those whoareunfamiliarwithProgrammableLogicdevices(PLDs). The information may also be useful to those who are current users ofprogrammablelogic.Thespecificissueswhichneedtobe addressedare: What is a PLD? What other implementations arepossible? What advantages doPLDshaveover other implementations? What is aPLD? In general, a programmable logic device is a circuit which can be configuredbytheuser toperformalogic function.Most "stan-dard"PLDsconsistofanANDarrayfollowedbyanOR array, either (or both) of which is programmable.Inputs are fed into the ANDarray,whichperformsthedesiredANDfunctionsand generates product terms.The product terms are then fed into the OR array.IntheOR array,theoutputsofthevariousproduct terms are combined toproduce the desired outputs.There are three fundamentaltypesof standardPLD: thePROM, thePAL device,andthePLS device. PROMs PROMsareusually thought of asmemory elements.However, thePROMhasa fixed ANDarray(whichdecodes thememory address) followed by a programmable OR array (Figure1).For eachof a givenset of input combinations(addresses),it gener-atesa valuewhichhas beenprogrammedinto the device. r-'\ L........I ,, . FIXEDAND ARRAY -$- INDICATESPROGRAMMABLE CONNECTION + INDICATES FIXED CONNECTION 40101 PROGRAMMABLEOR ARRAY A ,, Figure 1.PROMArray Structure Monolithic W Memories 11 Introduction PAL Devices ThePAL devicehasa programmable ANDarray followedbya fixedORarray(Figure2).ThefactthattheANDarrayis programmablemakes itpossiblefor thedevices tohavemany inputs. The fact that the OR array is fixed makes the devices small (whichmeans less expensive) andfast. PLSDevices ThePLS(ProgrammableLogic-basedsequencer)devicesare basedonthe standard PLA architecture(Figure 3),whereboth the ANDandtheORarraysareprogrammable.Thisarrange-ment allows for greater overall flexibility.The architecture is a bit morecostlyintermsofdiesizeandspeed,so for simplelogic functions, a PAL device is usually more cost effective.However, thisarchitectureisveryeffectiveforsequencers,wherethe flexibilityallowslargerstatemachinesthanmightfitinaPAL device. Other PLDs Inadditiontothebasicsum-of-productsPLDs,somemore complexPLDsdedicatedtosequencingareavailable,most notably thePROSETMdevice and the Am29PL 141.Their archi-tectures are described elsewhere in the handbook, but their fun-damental benefits are the sameas those of the more traditional PLDs. g ~ ~ gg PROGRAMMABLEANDARRAY INIATESPROGMN-$- D CRAMABLE CONECTION + INDICATES FIXEDCONNECTION Inpractice,thedistinctionsbetweenarchitecturesarenotas significant as the differences between the types of functions to be performed.Forthis reason, this handbook is organized primarily intodiscussionsaboutPAL devicesanddiscussionsaboutse-quencers,whetherthosesequencersbeimplementedinPAL devices,PLS devices, or one of the dedicated sequencers. What Other Implementations Are Possible? There areessentially four alternatives toprogrammable logic: Discrete Logic Gate Arrays Standard CellCircuits Full CustomCircuits Discrete Logic Discretelogic,or conventional TIL logic,has theadvantageof familiarity; hence its popularity.It is also quite inexpensive when only unit cost is considered.The drawback is that the implemen-tation of even a simple portion of a system may require many units of discrete logic.There are "hidden" costs associated witheach unit that goes into a system, which can render the overall system more expensive. ~FIXEDORARRAY . ~~~~~~L.I n ~~1=< L.I Figure 2.PALDevice Array Structure 40102 12~ Monolilhlc W Memories ~IntroductiOL'1 Designingwithdiscrete chipscanalsobeverytedious.Each design decision directly affects the layout of the board.Changes are difficultto make. The design is also more difficult to document, makingitharder to debugandmaintainlater.Theseitemsall contribute to along design cyclewhendiscrete chips areused extensively. Gate Arrays Gatearrays have beenincreasing in popularity.Theattractive-ness of this solution lies in the device's flexibility.By packing the functions into the device, a great majority of the available silicon isactuallyused.Sincesuchadeviceiscustomizedforan application,itwouldseemtobetheoptimumdeviceforthat application. However,onealsopayssubstantialdevelopment costs,espe-ciallyin the case of a design whichneeds changesafter silicon hasalreadybeenprocessed.Eventhoughtheunitcostsare generally quite low for gate arrays, the volumes required to make theiruseworthwhileexcludesthemasasolutionformany designers.This fact, added to the long design cycle and high risk involved, make this solution practical for only a limited number of designers. Standard Cell Circuits Standard cell circuits are quite similar to gate arrays, their main advantage being that they consist of a collection of different parts of circuits which have already been debugged.These circuits are ~ ~ ~ ~ ~ ~ ~ ~ . PROGRAMMABLEANDARRAY -$- INDICATES PROGRAMMABLE CONNECTION 40103 then assembled and collected to perform the desired functions. This canideally lead toreduced turnaround fromconception to implementation,and a much more efficient circuit. The drawback is that even though the individual components of the circuit have been laid out, a complete layout must still be per-formed to arrange the cells.Instead of just customizing the metal interconnections,asis done ina gate array, the circuit must be developed from the bottom up.Development costs can be even higherthan forgate arrays, and despite the standard cell concept, turnaround time often tends to be longer than planned. Again, the volumemustbesufficientlyhightowarrantthedevelopment costs. Full Custom Circuits Full custom deSigns require that a specific chip be designed from scratch to perform the needed functions.The intent is to provide a solution which gives the designer exactly what is needed forthe application in question; no more and no less.Ideally, not a square micron of silicon is wasted.This normally results in the smallest piece of silicon possible to fit the needs of the design, which in turn reduces the system cost.Understandably, though, development costs and risks for such adesign are extremely high, and volumes must be commensurately highinorder for sucha solution tobe of value. PROGRAMMABLE ~ORARRAY .. . . 1'\ ~F< ~F< F< ~F< ~F< y , Figure 3.PLA Array Architecture ~ PRonolithlc W Memories ~ 13 01 What Advantages do PLDs Have Over Other Implementations? Asuser-programmablesemicustomcircuits,PLDsprovidea valuablecompromisewhichcombinesmanyofthebenefitsof discretelogicwithmanyofthebenefitsofothersemicustom circuits.The overall advantages can be found inseveral areas: Ease of design Performance Reliability Cost savings Ease of Design The support tools available for use in designing with PLDs greatly simplify the design process by making the lower-level implemen-tation details transparent.In a matter of one or two hours, a first time PLDuser can learn to design with a PAL device, program it, and implement the design ina system. Thedesignsupporttoolsconsistofdesignsoftwareanda programmer.Thedesignsoftwareisusedingeneratingthe design;theprogrammerisusedto configurethedevice.The software provides the link between thehigher-level designand the low-level programming details. All of the available design software packages (of which Monolithic Memories' PALASM software is the most widely used) perform essentially the same tasks.The design is specified with relatively high-level constructs; the software takes the design and converts itinto a formwhich theprogrammer uses to configure the PLD. Most software packages providelogic simulation, whichallows one to debug the design before actually programminga device. Thehigh-level design filealsoservesasdocumentation of the design.This documentation canbe eveneasier tounderstand than traditional schematics. Depending on the capabilities desired, a device programmer can cost anywhere from under $1,000.00 to around $15,OOO.00for a high-volumeproductionprogrammer.ManyPLDusersdonot find it necessary to purchase a programmer; it is often quite cost effectiveand convenient tohaveeither themanufacturer or an outside distributor do the programming forthem.Fordesign and prototyping, though, it is very helpful to have a programmer; this allows one to implement designs immediately. Theconvenienceofprogrammablelogicliesintheabilityto customize a standard, off-the-shelf product.PLDs canbe found instock tosuit a wide range ofspeed and power requirements. The variety of architectures available also allows a choice of the properfunctionality forthe application at hand.Thus adesign can beimplementedusingastandarddevice,withtheendresult essentially being a custom device.If a design change is needed, it isa simple matter to edit the original design and then a new device, or,in the case of reprogrammable CMOS devices, erase andreprogram the old device. Boardlayoutisvastly simplifiedwiththeuseof programmable logic.PLDsoffergreatflexibilityinthelocationofinputsand outputs on the device.Sincelarger functionsareimplemented insidethePLD,boardlayoutcanbeginoncetheinputsand outputs are known.The details of what will actually be inside the PLDcanbeworkedout independentlyof thelayout.Inmany cases, any needed design changes can be taken care of entirely within the PLD,andwillnot affect the PC board. Performance Speed is one of the main reasons that designers use PAL devices. The TTL PAL devices presently on the market can provide equal or better performancethanthe fastestdiscretelogic available. ECL PAL devices extend the benefits of programmablelogic to the evenhigher-speed realmof ECL logic.Today's fastest PAL devices are being developed on the newest technologies to gain every extra nanosecond of performance. Performancecannotcomestrictlyattheexpenseofpower consumption.SincePLDscanbeusedtoreplaceseveral d'iscretecircuits, thepower consumptionofa PLDmay wellbe less than that of the combined discrete devices.AsmorePLDs aredevelopedinCMOS technology,theoptionforevenlower power becomes available, including zero standby power devices for systems which can tolerateonly minute standby power con-sumption. Reliability Reliability is an area of increasing concern.As systems get larger and more complex, the increase in the amount of circuitry tends to reduce the reliability of the system; there are "more things to go wrong".Thus a solution which inherently reduces the number of chips in the system will contribute to higher reliability.Aprogram-mabie logic approach canprovide device quality levels up to 50 partspermillion(ppm),whilealsoprovidingamorereliable solutiondue to the smaller number of devices required. Withthe reductionin units andboard space,PC boards canbe laid out less densely, which greatly improves the reliability of the boarditself.Thisalsoreducescrosstalkandotherpotential sources of noise, making the operation of the system cleaner and more reliable. Cost For any design approach to be practical, it must be cost effective. Cost isalmost always a factor in consideringa new design or a design change.But thecalculation of total systemcost canbe misleadingif not allaspects are considered.Many of thecosts can be elusive or difficult to measure.For example, it is difficult toquantifythecostofmarketsharelostduetolateproduct introduction. The greatest savings over a discrete design are derived from the fact that a single PLD canreplace several discrete chips.Board spacerequirementscandrop by 25% or more whenPLDs, are used.Figure4illustratessomeofthecostsofthevarious solutions discussed so far, withmany of the factors that may not alwaysbeconsideredincludedfor comparison.Theseinvolve such items as inventory costs, inspection costs, test costs, board materials costs, and of course the very costly time spent design-inganddebuggingsuchsystems,andisolatingandreplacing units which fail.With each design change, the cost of a custom 14 Monolithic W Memories ~f eo =: e: a ~~~~~tf .... in PLDs: BLANK PLDs: FACTORY PROGRAMMED DISCRETE LOGIC GATE ARRAYS STANDARD CELLS FULL CUSTOM Unit Cost Range Low-Med Low-Med Low-Med Low Low Very Low --NREslPurchaseDesignGate Count Development CostsVolumeFlexibilityper Device For Best Economics None5K-200KMed20()-2K Low10K-200KMed20()-2K None1K-10KLow10-30 Med-High10K-200KMed-High1K-10K High100K-300KMed-High1K-10K High200K andUpHigh1K-60K ----Figure 4.Cost and Design-time Comparisons Engineering Design Time 1/2 Week 3-10 Weeks 1 Week 12-40 Weeks 26-52 Weeks 1-2 Yrs. ~ r.J Design Turnaround Time Short (1-10 Days) Moderate (8-10 Wks.) Short (1-10 Days) Long (3-9 Mos.) Long (6-12 Mos.) Long (6-12 Mos.) Cost of Each Design Change Very Low Med Med High High High -:J .. ""l o D-C () .. O :J Introduction solutionrisesdramatically,whilethatofauser-customizable approachisminimal.Therelationshipbetweenthevarious alternatives issummarizedinFigure 5. Another economic benefitof the use of PLDs is that when one PAL device isused inseveral different designs, as is often the case, the user has not com mitted that device to anyone of the particular designs until the device has been programmed.This means that inventory can be stocked for several different designs in the form ofonedevice.Asrequirementschange,thepartscanbe programmed to fit the need.And in the case of reprogram mabie CMOSdevices,one isnot committedeven after programming. Thereisalsoacost-effectivePLDsolutionforhigh-volume production.Just as a ROM is a PROM which has been hard-wired formassproduction,HAL (HardArrayLogic)devicescanbe producedinhighvolumesforextra costsavings.Thismask-programmedversioncanbeproducedinhighvolume~ i t unparalleledquality.Inaddition,intheeventthatproduction quantitiesforyoursystemshowanunexpectedincrease,the equivalentPALorProPALTMdevices(in-factoryprogrammed PAL devices) canbe quickly obtainedandprogrammedinyour factory,by Monolithic Memories, or through distribution to cover thetemporaryshortage.MoredetailsonHALandProPAL devices are provided onpage 3-104 of the DataBook. One finalsubtle cost issue is derived from the ease with which a competitorcan copy a design.PLDs have a unique feature called a security fuse, whose purpose is to protect a design from being copied.By using secured PLDs extensively in a system, one can COST safely avoid having one's system easily deciphered.The added designsecurityprovidedbythisfeaturecanbuyextramarket time,forcingcompetitorstodotheirownoriginaldesignwork rather than copying the designs of others. Summary Programmable logic provides the means of creating semi-custom designs withreadily available standard components.There is a widevarietyofPLDs;PALdevicesaremostwidelyused,and performwellforbasiclogicandsomesequencingfunctions. Otherdedicatedsequencersprovidethecircuitryrequiredto implement more complex designs. By assuming some of the attributes of gate arrays, programmable logic provides the cost savings of any other semicustom device, withouttheextraengineeringcosts,risks,anddesigndelays. Reliabilityisalsoenhancedasqualityincreasesandboard complexity decreases. Thedesign tasksaregreatlysimplifieddue tothedesigntools whicharenow available.Designsoftware and device program-mers allow top-down high-level designs, with a minimum of time spent on actual implementation issues.Simulation allows some design debugbefore a device is programmed. For all of thesereasons,programmable logic has become,and willcontinuetobe,thedesignmethodologyofchoiceamong digital systems designers. ~~DEVELOPMENTTIME Figure 5.Development Cost vs Time for Alternative Logic Implementations 16 ~ Monolithic W Memories~Product Overview Introduction Monolithic Memories and Advanced Micro Devices offer a wide variety of PLDs, implemented in a variety of technologies.In this section, we will briefly discuss the device families, and look at the variousarchitecture,speed,andpower options.Morespecific device information canbe foundin theindividual data sheets in Section 5.Discussions on some of the special architectural fea-tures of many of the devices can also be found in their respective datasheets. TherearethreebasicPLDareasaddressedbyMonolithic Memories' devices: PAL devices-general purpose Programmable sequencers-state machines LCATMdevices-high density The largest application area is that coveredby the PAL devices. ThereisawidevarietyofPALdevices,rangingfromsimple devicesthataddressgenerallogicdesignproblemstomore sophisticateddevices that deal withmore complex problems. There is also a series of sequencers which are not PAL devices, featuringarchitecturesparticularlywellsuitedtosequencing operations.While there arePAL devices that work well as state machines in addition to their other applications, these dedicated sequencershavegivenupsomeoftheirgeneralitytoprovide optimal state machine solutions. The final area covered is that of high-density design, addressed bytheLCA devices.TheLCA device takestheapproachofa programmablegatearraytoprovideaPLDwithmanyusable gates. Design software radically simplifies the design of any circuit ina PLD.PALASM software is used for all of the PLDs except the LCA devices. The LCAdevices make useof XACTTMsoftware for logic configuration.ThePALASMsoftwaredocumentationisin Section4;XACTsoftwareisdiscussedmorefullyon page 3-17 of theData Book. PAL Devices PAL devices are available inthree different technologies: TIL CMOS ECL The CMOS devices often provide the same functions as the TTL devices,and can beusedinthesamesockets,withtheadded benefit of lower power.Thus the TIL and CMOS devices will be discussedtogether,followedbyasummary ofspecificCMOS issues.ECLdevices require completely different design consid-erations, and cannot be interchanged with TIL or CMOS devices. They will therefore be discussed separately. PAL devices generally have a mnemonic naming scheme, which provides some basic information about the devices' capabilities. BecauseMonolithicMemoriesandAdvancedMicroDevices recently merged, there are presently two slightly different naming conventionsinuse.SomedeviceswereoriginallyMonolithic Memories' devices; some were AdvancedMicro Devices'; some devices were produced by both companies before the merger.In order to minimize the confusionafter the merger, the old device names are being maintained. The two naming conventions will be discussedseparately.Throughoutthishandbook,"Am PAL" designates products originally from AdvancedMicroDevices. Note that allproducts thatMonolithicMemoriesand Advanced.. MicroDeviceswereproducingbeforethemergerarestillin production. Monolithic Memories Nomenclature Monolithic Memories originally set the PAL device naming stan-dard.Anexample of an older device name is shown inFigure 1. Asdeviceshavebecomefaster,andasCMOShasbecome available,ithasbecomenecessarytochangethewaywe describe the performance of newer devices.While the conven-tion is slightly different, it does make it easier to see exactly what the speed grade and power level of a device are.Anexample of sucha new device is shown inFigure 2. AdvancedMicro Devices Nomenclature TheAdvancedMicroDevicesnomenclature followstheMono-lithic Memories nomenclature with a few modifications.A typical older devicename isshown inFigure 3. AdvancedMicroDevicesalsofoundtheneedtomodifythe nomenclaturewiththeadventoffasterdevicesandCMOS devices.Anexample of a newer device is showninFigure 4. Therelationshipbetweenadeviceanditsnamewillbecome apparent in the Tablesfollowing. The package designators also differ.A cross reference for com-mercial packages isshown in Table1. MONOLITHICADVANCED PACKAGEMEMORIESMICRO DEVICES Plastic DIPNP Plastic SKINNYDIPNSP Ceramic DIPJD Ceramic SKINNYDIPJSD PLCC-20-pinNLJ PLCC from 24-pin DIP,FNJ JEDEC PLCC from 24-pinDIPNL-PLCC from28-pinDIPFNJ LCCLL Table 1.Package Designators Monolithic W Memories l117 Product Overview PAL _If NUMBER OF INPUTS~ARCHITECTURE Notes: Eel devices alsohaveeither'10H' or'100'following'PAl'to indicate theECl family compatibility. The number ofinputs includes feedback,if feedback exists. Thearchitecture codevaries.Itisusuallymnemonic,andthe meaningsofeachcodewillbelistedineachofthefollowing sections. POWER LEVEL SPEED GRADE NUMBER OF OUTPUTS (OR FLlPFLOPS) 40201 The speed grade indicates the propagation delay.In general, the speeds are as follows: blank:35ns(Note that -2 and -4 devices areslower) A:25ns B:15ns D:10ns The power level canbe one of three designators: blank:'full power',180-240 rnA -2:'half power',90-105 rnA -4:'quarter power', 45-55 rnA Figure 1.MonolithIc Memories Nomenclature for Older Products Notes: PAL ~ TC 16 TECHNOLOGY~NUMBEROFINPUTS ARCHITECTURE The technology designator canbe one of four codes: blank=TTL C=CMOS 10H=10KH ECl 100=100K ECl The number ofinputs includes feedback,if feedback exists. f t SPEEDGRADE L POWERLEVEL NUMBEROFOUTPUTS (ORFLlPFLOPS) 40202 Thearchitecture codevaries.Itisusuallymnemonic,andthe meaningsofeachcodewillbelistedineachofthefollowing sections. The power level can be one of four designators: blank:'fullpower',180-240 rnA H:'half power', 90-105 rnA Q:'quarter power', 45-55 rnA Z:'zero power',-t>pO

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PR Figure 12.Basic FlipFlops DT DC TT TC JKT JKC SRT SRC Building the D-Type Flip-Flop Equations A Ootype flip-flop merely presents the input data at the output after being clocked.Its basic transfer function can be expressed as DT:=D wherewehaveusedpinsOT("0True")andDasshownin Figure12. Note theuseof':=' hereinsteadof'='.Thisindicates thatthe output is registered for this equation.The difference is illustrated inFigure 13. DDT b. 0 -D0aDT CLK "---40307 aFigure 13.Registered vs.Combinatorial Equations We canalso generate the complement signal(named with the statement DC:=/D As per Figure 12,we want to add synchronous preset and clear functions to the flip-flops.This can be done with two input pins, calledPR andCLR.Toadd these functions to the true flip-flop signal, we add /CLR to every product termandadd one product termconsistingonlyofPRoLikewise,forthecomplement functions, we add /PR to every product term, and add one product term consistingonly of CLR.This is showninFigure 14. DT:- D*/CLR +PR DC:=/D*/PR +CLR Figure 14.OTypeFlip.Flops with Clear and Preset Monolithic mMemories 2-9 Ell Beginner's Guide Inthis way, when clearing the flip-flops, the active-HIGH flip-flops havenoproduct terms true,andgo lOW; the active-lOW flip-flops have the last product term true, and will therefore go HIGH. Thereverse will occur for the preset function. DT:- D*/CLR +PR*/CLR DC:- /D*/PR +CLR There Is still one holein this design:what happens if wepreset and clear at the same time?As it Is right now, both outputs will go HIGH.This makes no sense since one signal Is supposed to be theInverseoftheother.Torectifythis,wecangivetheclear functionpriorityoverthepresetfunction.Wecandothisby placing lelR oneveryproduct termfor the true flip-flop signal. The results areshown InFigure15. Figure 15.D-Type Flip-Flops with Clear Priority Building the Remaining Equations The same basic procedure can be applied to all of the other flip-flops.Theequations are shown InFigure16. 210 EQUATIONS ;emulatingallflip-flopswithD-typeflip-flops DT:- D*/CLR +PR*/CLR DC:- /D*/PR +CLR TT:- T*/TT*/CLR +/T*TT*/CLR +PR*/CLR TC: - T* /TC* /PR +/T*TC*/PR +CLR JKT:=J*/JKT*/CLR +/K*JKT*/CLR +PR*/CLR JKC:- /J*/JKC*/PR +K* / JKC* /PR +CLR SRT:- S*/CLR +/R*SRT*/CLR +PR*/CLR SRC: ..R*/PR +/S*SRC*/PR +CLR ;outputisDif notclear ;or1if presetandnotclearatthesametime ;outputis/Dif notpreset ;or1if clear ;goHIif toggleandnotclear ;stayHIif nottoggleandnotclear ;goHIif presetandnotclearatthesametime ;goHIif toggleandnotpreset ;stayHIif nottoggleandnotpreset ;goHIif clearing ;goHIif Jandnotclear ;stayHIif notKandnotclear ;goHIif presetandnotclearatthesametime ;goHIif notJandnotpreset ;stayHIif Kandnotpreset ;goHIif clear ;goHIifsetandnotclear ;stayHIif notresetandnotclear ;goHIif presetandnotclearatthesametime ;goHIifresetandnotpreset ;stayHIif notsetandnotpreset ;goHIif clear Figure 16_Flip-Flop Equations Section MonollthlcWMemorles Beginner's Guide 40308 ClK ClR T PR I!!I := T" 0Il"tClR + /T" [!!] "tClR + PR*tClR >---1--10QH>---TT Figure 17"Feedback In the Equation for IT Notice that in some of the equations above, the output signal itself shows up in the equations.This is the way in which feedback from the flip-flop can be used to determine the next state of the flip-flop. AnequivalentlogicdrawingoftheTTequationisshownin Figure17. Completing the Design File Wearenowinapositiontoselectadeviceandcompletethe device file.The device used will be a PAL 16R8, which is actually an active-LOW device.The logic diagram for this device can be foundon page 5-47.The implications ofanactive-lOW device are discussed more fully on page 6-19.For now, suffice it to say thatonewayofimplementingactive-lOWlogicistodeclare outputsinthepinlistwithaslash('f)infrontofthem.This essentially defines themas'negative' or 'inverted' pins. Thedeclarationsectionisbuiltup just likethelastone,andis shown in Figure 18. TITLEBasicflip-flops PATTERNPODOl REVISIONA AUTHORStateyourNamehere COMPANYNameofyourCo.,Inc. DATE7/22/87 CHIPFlip-flopsPAL16R8 iPINS12345678910 CLKJKTPRCLRDSRGND iPINS1112131415 OEISRCISRTIDCIDT iPINS1617181920 ITCITTI JKCI JKTVCC Figure 18.Basic Flip-Flops Declaration Section Notice that this device has aclockand an output enable pin, called elK and OE, respectively.The input and output pins are named :isshowninFigure12.Theoutputpinsarealldefinedwith ;Iashes, toindicate that theyare inverted pins. The design cannow be processed by hitting and then hitting 6 This will tell you whether there are any basic problems with your design.You can correct any mistakes by editing the file and then reprocessing. Simulating the FlipFlops After processing the design and correcting any mistakes, we can write the simulation.We have all of the simulation instructions we need, except for onenew instruction which simplifies manipula-tion of the clock signal.It is possible to use SETF instructions with theclock pin,buttheneachclock transitionwouldrequire two instructions:onetosettheclockHIGH,andonetobringit back lOW. Instead, we can use the CLOCKF instruction.This pulses a clock pininoneinstruction.Ofcourse,registeredoutputswillnot change state until after the rising edge of the clock signal.Since we have named the clock pin ClK, we can clock this device with theinstruction CLOCKFCLK Wecansimulate the trueD-type flip-flop as follows: SETFD CLOCKFCLK CHECKDT SETFID CLOCKFCLK CHECKIDT isettheDinputHI ;clockthedevice ;verifythattheoutputwentHI ;settheDinputLO ;clockthedevice ;verifythattheoutputwent10 Before weactually simulate anyregistered designlike this, two items must be initialized: the clock and the output enable pin (OE). Since the ClOCKF statement executes a HIGH-LOW pulse on the clock pin,we must firstmake sure that the clock is set LOW l1 Monolithic IFJJ) Memories l1211 EJI Beginner's Guide to begin with.We must also enable tho outputs, which is done by setting the OE pin LOW.These tasks can be accomplished with thestatement: SETFCLRIPR CLOCKFCLK ;settheclearpin ;clearthecircuit SETFICLK10E ;makesuretheclearfunctionworked CHECKlOTDCITTTCIJKTJKCISRTSRC SETFICLR;removetheclearsignal Wealso need toinitialize the flip-flops.At the same time we can verify that theCLR functionisworkingcorrectly:We are now in a position to simulate the entire circuit.A thorough simulationisshowninFigure19. 212 SIMULATION TRACE_ONCLRPRDDTDCTTTTCJKJKTJKCSRSRTSRC ;initializethecircuit SETFCLRIPR CLOCKFCLK ;3ettheclearpin ;clear thecircuit ;makesuretheclearfunctionworked CHECKIDTDCITTTCIJKTJKCISRTSRC SETFICLR;removetheclearsignal ;checkoutthepresetfunction SETFPR; setthepresetpin CLOCKFCLK; presetthecircuit CHECKDTIDCTTITCJKTIJKCSRTISRT SETFIPR; removethepresetsignal ;verifythatclearhaspriority SETFPRCLR;setbothclearandpreset CLOCKFCLK CHECKIDTDCITTTCIJKTJKCISRTSRC SETFIPRICLR;removebothpreset,clear ;disableallflip-flopinputsfornow SETFIDITIJIKISIR ;checkoutD-typeflip-flops SETFD; settheDinputHIfromLO CLOCKFCLK; clockthedevice CHECKDTIDC;verifythatthetrueoutputwentHI ;andthecomplementwentLO SETFD CLOCKFCLK CHECKDTIDC SETFID CLOCKFCLK CHECKIDTDC SETFID CLOCKFCLK CHECKIDTDC ;holdaHI ;verifythatstatemaintained ;settheDinput10fromHI ;clockthedevice ;verifythatthetrueoutputwentLO ;andcomplementwentHI ;holdaLO ;verifythatstate~ i n t i n e d;checkoutT-typeflip-flops SETFIT; holdaLO CLOCKFCLK CHECKITTTC;trueoutputshouldstillbe10 ;complementoutputHI SETFT CLOCKFCLK CHECKTTITC ;togglefromaLO ;bothoutputsshouldhavechangedstate Flguro 19.Flip-Flop Simulation Section ~ Monollthlo W Memories ~Beginner's Guide SETFIT CLOCKFCLK CHECKTTITC SETFT CLOCKFCLK CHECKITTTC ;checkoutJ-Kflip-flops SETFIJIK CLOCKFCLK CHECKI JKTJKC SETFJIK CLOCKFCLK CHECKJKTI JKC SETFIJIK CLOCKFCLK CHECKJKTI JKC SETFIJK CLOCKFCLK CHECKI JKTJKC CLOCKFCLK CHECKI JKTJKC SETFJK CLOCKFCLK CHECKJKT/ JKC SETFJIK CLOCKFCLK CHECKJKTI JKC SETFJK CLOCKFCLK CHECKI JKTJKC ;checkoutS-Rflip-flops SETFIs/R CLOCKFCLK CHECKI SRTSRC SETFSIR CLOCKFCLK CHECKSRTI SRC SETFISIR CLOCKFCLK CHECKSRTI SRC SETFSIR CLOCKFCLK CHECKSRTI SRC SETFISR CLOCKFCLK CHECKISRTSRC CLOCKFCLK CHECKISRTSRC ;holdaHI ;bothoutputsshouldhaveheldtheirstate ;togglefromaHI ;bothoutputsshouldhavechangedstate ;holdaLO ;bothoutputsshouldhaveheldtheirstate ;setaHI ;outputsshouldhavechanged ;holdaHI ;bothoutputsshouldhaveheldtheirstate ;resetaLO ;outputsshouldhavechanged ;resetanoutputthatisalreadyLO ;makesurethattheoutputsdidn'tchange ;togglefromaLO ;verifythatoutputschanged ;setanoutputthatisalreadyHI ;makesuretheoutputsdidn'tchange ;togglefromaHI ;verifythatoutputschanged ;holdaLO ;bothoutputsshouldhaveheldtheirstate ;setaHI ;outputsshouldhavechanged ;holdaHI ;bothoutputsshouldhaveheldtheirstate ;setanoutputthatisalreadyHI ;makesuretheoutputsdidn'tchange ;resetaLO ;outputsshouldhavechanged ;resetanoutputthatisalreadyLO ;makesurethattheoutputsdidn'tchange Figure 19.Flip-Flop Simulation Section(Cont'd.) Monolithic: W Memories EJI 213 Beginner's Guide The file cannow besimulated in the same manner as the basic gatesdesign.Thesimulationresultscanbeviewedeither by examining the history or trace file,or by generating waveforms. The complete design file is shown inFigure 22 at the end of this section. Programming aDevice After simulating the design, and verifying that it works, it is time to program a device.There are several steps to programming, but the exact operation of the programmer naturally depends on the type of programmer being used.We will be as explicit as we can here, but you will need to refer to your programmer manual forthe specifics. The first thing that must be done after turning the programmer on is to select the device type.This tells the programmer what kind ofprogrammingdatatoexpect.Thedevicetypeisusually selected either froma menu or by entering a device code.Your programmer manual will have the details. Next a JEOEC file must be downloaded.To transfer the JEOEC filefromthecomputertoyourprogrammer,youwillneedto providea connection,as showninFigure20.Thisisnormally donewithanRS-232cableconnectedbetweenthe programmer'sportandaserialportonthecomputer(usually COM1). 40309 Figure 20.A Connector Must BeProvided Between the Computer and the Programmer If your programmer can perform functional tests, and you wish for those tests to be performed, you should download the '.JOC file; otherwise youshould download the'.JEO' file. To download data, the programmer must first be set up to receive data.The programmer manual will tell you how to do this.The data can thenbe sent fromthe computer by hitting Thissetsupcommunicationbetweenthecomputerandthe programmer.Whichever communication program is installed will beinvoked.ThisisusedtotransmittheJEOECfiletothe programmer. The details below assume you are using PC2; if not, follow the instructions for your program to accomplish the same steps. Before actually sending the data, you must verify the correct com-munication protocol.Check to make sure you know what protocol theprogrammerisexpecting;thenhitthekeyonthe computer.This allows you to set upthe baud rate, data bits, stop bits,and parity. Once the protocol has been set up, hit the key.You will be asked for the file name; enter the name of the JEOEC file you wish touse.The computer will then announce thatitissending the data, and tell you when it is finished.Note that just because it says ithasfinishedsendingdata does notmeanthat the data was received.Your programmer will indicate whether or not data was received correctly. Once thedata has beenreceived,the programmer isready to program a device.Place a device in the appropriate socket, and followtheinstructionsforyourprogrammertoprogramthe device.This procedure programs and verifies the connections in the device, and, if a '.JOC' file was used, will perform a functional test. Theprogrammer willannouncewhentheprogrammingproce-dure has been completed.You may then take the device and plug it into your application. If youhaveactuallyprogrammedone of theexamples thatwe createdabove, younaturally don't have a boardinto whichyou can plug the device.If you do have a lab setup, you may wish to play with the devices to verify for yourself that the devices perform just as youexpected them to. Youwillfindmuchmoredetailonmanyissues thatwerenot discussed in this section in the remaining sections of this hand-book.Thissectionshouldhaveprovidedyouwiththebasic knowledgeyouneedtounderstandtheremainingdesignex-amples in this book,and to start your own designs. 214 lfIIonollthlc W lfIIemorles Basicgates POOOO A Beginner's Guide TITLE PATTERN REVISION AUTHOR COMPANY DATE StateyourNamehere NameofyourCo.,Inc. 7/22/87 CHIPGATESPAL12H6 ;PINS2345678910 ACDFGIJKMGND ;PINS11121314151617181920 NPBEHR0LQVCC EQUATIONS B- /A E=C*D H=F +G L- /I +/J +/K o- /M*/N R=P*/Q +/P*Q SIMULATION ; inverter ;ANDgate ;ORgate ;NANDgateafterapplyingDeMorgan'stheorem ;NORgateafterapplyingDeMorgan'stheorem ;XORgate,expanded TRACE_ONABCD EFGHIJKLM N0PQR ;lookattheinverter SETFA CHECK/B SETF/A CHECKB ;lookatANDgate SETF/C/D CHECK/E SETFD CHECK/E SETFC/D CHECK/E SETFD CHECKE ;lookatORgate SETF/F/G CHECK/H SETFG CHECKH SETFF CHECKH SETF/G CHECKH ;setAHI ;verifythatBisLO ;setALO ;verifythatBisHI ;endofinvertertrace ;setC,DLO ;verifyELO ;CstaysLO,D goesHI ;EshouldstayLO isetCHI,DLO iEshouldstayLO ;CstaysHI,D goesHI ;EshouldnowbeHI iendofANDgatetrace isetF,GLO ;verifyHLO iFstaysLO,GgoesHI ;HshouldgoHI iGstaysHI,FgoesHI iHshouldstayHI iFstaysHI,G goesLO ;HshouldstayHI iendofORgatetrace Figure 21.CompleteBasic GatesDeSignFile Monollthlo [FJJJ Memories 215 216 Beginner's Guide jlookatNANDgate SETFIIIJIK CHECKL SETFK CHECKL SETFJIK CHECKL SETFK CHECKL SETFIIJIK CHECKL SETFK CHECKL SETFJIK CHECKL SETFK CHECKIL jlookatNORgate SETF1MIN CHECK0 SETFN CHECK10 SETFM CHECK10 SETFIN CHECK10 jlookatXORgate SETFIPIQ CHECKIR SETFQ CHECKR SETFPIQ CHECKR SETFQ CHECKIR jIJK..000 jverifyLHI jIJK..001 jLshouldstill beHI jIJK..010 jLshouldstill beHI jIJK..011 jLshouldstill beHI jIJKco100 jLshouldstill beHI jIJK..101 jLshouldstill beHI jIJK..110 jLshouldstill beHI jIJK..111 jLshouldgoLO ;endofNANDgatetrace jsetM,NLO ;verify0HI jMstaysLO,NgoesHI ;0shouldgoLO ;M,NnowbethHI ;0shouldstayLO ;MstaysHI,NgoesLO ;0shouldstayLO ;endofNORgatetrace ;setP,QLO ;verifyRLO ;PstaysLO,QgoesHI ;RshouldgoHI ;nowPHI,QLO ;RshouldstayHI ;bethinputsHI ;RshouldgoLO ;endoftrace Figure21.Complete Basic Gates Design File(Cont'd.) MonolithIc W MemorIes Beginner's Guide TITLE PATTERN REVISION AUTHOR COMPANY DATE Basicflip-flops P0001 A StateyourNamehere NameofyourCo.,Inc. 7/22/87 CHIPFlip-floPAL16R8 ;PINS1235678910 CLKJKTPRCLRDSRGND ;PINS1112131415 OE/SRC/SRT/DC/DT ;PINS1617181920 /TC/TT/JKC/JKTVCC EQUATIONS ;ernulatingallflip-flopswithD-typeflip-flops DT:=D*/CLR +PR*/CLR DC:=/D*/PR +CLR TT:=T*/TT*/CLR +/T*TT*/CLR +PR*/CLR TC:=T*/TC*/PR +/T*TC*/PR +CLR JKT: =J* / JKT* /CLR +/K*JKT*/CLR +PR*/CLR JKC:=/J*/JKC*/PR +K*JKC*/PR +CLR SRT:=S*/CLR +/R*SRT*/CLR +PR*/CLR SRC:=R*/PR +/S*SRC*/PR +CLR ;outputisDif notclear ;or1if presetandnotclearatthesametime ;outputis/Dif notpreset ;or1ifclear ;goHIif toggleandnotclear ;stayHIif nottoggleandnotclear ;goHIif presetandnotclearatthesametime ;goHIif toggleandnotpreset ;stayHIif nottoggleandnotpreset ;goHIif clearing ;goHIif Jandnotclear ;stayHIif notKandnotclear ;goHIif presetandnotclearatthesametime ;goHIif notJandnotpreset ;stayHIif Kandnotpreset ;goHIif clear ;goHIif setandnotclear ;stayHIif notresetandnotclear ;goHIif presetandnotclearatthesametime ;goHIif resetandnotpreset ;stayH