COOPERATIVE RESEARCH

1987 Annual Report

The Annual Report of the Semiconductor Research Corporation is published each June tosummarize the directions and results of the SRC Research Program, present the formalfinancial report, and provide information on activities and events of the SRC industry/government/university community for the previous calendar year. The highlight materialcontained in the research section and most of the illustrations used in this publication areprovided by the faculty and or graduate students conducting SRC-sponsored research. The

The Semiconductor Rese

remaining text is written by the technical staff of the SRC. Production is guided by the SRC’sEditorial Coordinator, Marian Regan.

This report is available to any interested personby requesting SRC Publication Number S88008.

Typesetting and graphics by Artworks, Inc., Research Triangle Park, NC.Printed in Greensboro, North Carolina, U.S.A., by Greensboro Printing.

arch CorporationThe Semiconductor Research Corporation (SRC) is

a cooperative effort of U.S. companies, with govern-ment participation, to strengthen and maintain thevitality and competitive ability of the U.S. semicon-ductor industry. Semiconductors are the key materialin integrated circuits, sometimes referred to as micro-electronic devices. These are the basic building blocksof the computation, communication, information proc-essing, and automation capabilities that are pervasivein the modern world and upon which the nation’sdefense and economy are becoming increasinglydependent.

The SRC plans and implements an integrated pro-gram of basic research conducted by faculty andgraduate students in the university laboratories. Themore-than-$80 million the SRC has committed toresearch programs over the last five years has fundeda so/id majority of the silicon-related generic researchconducted at U.S. universities. In 1987, SRC researchinvestigations supported efforts of 276 faculty and 383graduate students on 36 campuses.

SRC research is related to a set of long-rangeindustry goals. Research projects are funded throughformal contracts that are closely monitored by seniormembers of the 32-person corporate staff based atSRC headquarters in Research Triangle Park, NorthCarolina. Two special advisory groups complementthe SRC Board of Directors in furnishing policy andprogram guidance: the Technical Advisory Board(TAB) and the University Advisory Committee (UAC).

In 1987, the SRC provided support to the SEMATECHcooperative effort in manufacturing technology and willcontinue to participate by managing the SEMATECHsupporting research program.

The Semiconductor Research Corporation is amodel of cooperation for the efficient use of domesticresources. Its success has set the stage within theindustry, and between the industry and the government,for SEMATECH and other cooperative initiatives tostrengthen the U.S. technology base and, as a result,our nation’s ability to compete in microelectronics.

Die photograph of a pipelined, self-calibrating A/D converter implementedin CMOS technology at MIT (seeresearch highlight on page 34).

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MessageMessage from theChairman of the Boardand President

The SRC has been in operation for five years and is,by now, solidly established. Within our industry, theSRC is widely recognized for its accomplishmentstowards an integratedprogram of basic semiconductorresearch in university laboratories, and for encouragingthe supply of suitably qualified scientists and engineers.On a wider front, people are excited by the symbolismof U.S. companies’ cooperating on establishing asound foundation for our work. It has been delightful towatch the steady decrease of suspicions, and theincreasing ease of converse.

The most significant event of the last year has beenthe creation of SEMATECH. It represents a quantumleap in the cooperative activities of our industry. TheSRC has been a major participant in the many activitiesthat resulted in the creation of SEMATECH. That is veryappropriate, since SEMATECH’s mission is manufac-turing technology, while a major part (a third) of theSRC’s program is in the closely related area ofmanufacturing sciences. For that matter, there is also aclose relation of manufacturing technology with micro-structure sciences and design sciences, throughdesign for manufacturability. The SRC will participatein SEMATECH by assuming responsibility for its sup-porting research program. The administration of thisprogram will be similar in most respects to the existingSRC research efforts, and the results are expected tobe available to all SRC members.

It has been a busy year. As has been thoroughlypublicized in the press, the creation of SEMATECH wasfraught with major difficulties, which added greatly tothe load of the staff. A second issue was the need forthe SRC to transition from growth to stable funding.This came about because of the ’85-’86 downturn inindustry revenues, the resultant effect on SRC income,and now the need to rebuild our reserves. The neces-sary adjustments to the research agenda have beenmade, and the research program remains one of highquality and productivity. Throughout these difficultieswe have enjoyed constructive dialogue and goodrelations with our university partners.

Since the inception of the SRC research program atthe end of 1982, each of five groups has received totalfunding in excess of five million dollars: the University

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of California at Berkeley, Carnegie-Mellon University,Cornell University, the Microelectronics Center ofNorth Carolina, and Stanford University. The SRCsupport has had a major impact on each of theseresearch institutions, strengthening their contributionsto the new knowledge upon which our industry relies.We are currently reviewing the products of these majorefforts in order to obtain better understanding of theresearch management process. A brief summary ofthe first of these reviews, on Cornell, is given in thisreport.

The SRC has assumed an important role in thesemiconductor research activities in this country. Iexpect that over time the industry will find that moreactivities should be carried out together, rather thanseparately, and that the SRC will be asked to assume abroader responsibility for these cooperative activities.Its future successes will be determined by the quality ofmember participation, of its leadership, and of theresearch community with which we work.

My successor as Chairman of the Board of Directorsis Robert J. McMillin of Genera/ Motors. I am confidentthat he will find his tenure as rewarding as I have foundmine and that the SRC will benefit from his leadership.

Klaus D. BowersChairman, Board of Directors

Dr. Bowers has noted that this past year has seensignificant additional activity related to SEMATECH ontop of the increasingly busy schedule of the SRC. TheSRC’s ability to respond to this challenge is due to itshighly capable staff. Essential to this staff are theresidents assigned for varying lengths of time bymember organizations. These individuals make signifi-cant contributions to semiconductor technology whileat the SRC and, in the process, obtain invaluableexperience. At present, industry resident managerscomprise half of the ten-person research programstaff.

As SEMATECH becomes a reality, we expect thatdirect technology transfer from SRC research tomembers will be augmented by transfer to SEMATECH.SEMATECH will become one of our biggest customers.The foundation for a close relationship between theSRC and SEMATECH has been established by therequirement that all SEMATECH members must alsobe members of the SRC.

The partnership between the U.S. government andthe industry in semiconductor technology has grownmuch stronger. One effort in which the SRC has takeninitiative is support of the concept of a NationalAdvisory Committee on Semiconductors. The NACSwould provide a means for acquisition of information onthe technology and for the application of this informa-tion to increase the efficiency of the diverse, andsometimes redundant, semiconductor R&D efforts inthe United States.

The SRC’s primary research mission is the genera-tion of new knowledge that enables members toadvance their abilities to make competitive, high-performance products. An efficient means for com-municating this knowledge is in the form of models forsystems, circuits, devices, materials, processes, equip-ments, and fabrication sequences. Technology com-plexity makes these models difficult to construct andapply. During this past year, the SRC has seenimportant progress in modeling and the associatedsoftware environment. The need to link the technologymodels in a structure that extends from behavioral chipdescriptions to final production is becoming accepted.Efforts to provide a full spectrum of the needed toolsand software are paying off. Equipment modelingefforts are getting results, process and device modelsare being extended for submicron design rules, andlinkages between CASM (computer-automated semi-conductor manufacturing) and CAD tools are beingestablished. The knowledge on which future semi-conductor manufacturing will be based is emergingfrom SRC research.

Larry W. SumneyPresident

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Participants

CompaniesAT&TAdvanced Micro Devices, IncorporatedApplied Materials, lncorporatedControl Data CorporationDigital Equipment CorporationE.I. du Pont de Nemours & CompanyE-Systems, IncorporatedEastman Kodak CompanyEaton CorporationGTE Laboratories, IncorporatedGeneral Electric CompanyGeneral Motors CorporationHarris CorporationHewlett-Packard CompanyHoneywell IncorporatedIBM CorporationIntel CorporationLoral Systems GroupMonolithic Memories, Incorporated *Monsanto CompanyMotorola, IncorporatedNational Semiconductor CorporationThe Perkin-Elmer CorporationRockwell lnternational CorporationSEMI, Chapter **Silicon Systems, IncorporatedTexas Instruments IncorporatedUnion Carbide CorporationVarian Associates, IncorporatedWestinghouse Electric CorporationXerox Corporation

*The commitment for individual participation in the SRCby Monolithic Memories in 1987 preceded corporatemerger with Advanced Micro Devices.

GovernmentDepartment of DefenseNational Bureau of StandardsNational Science FoundationNational Security Agency

**The following companies are included inthe Semiconductor Equipment and MaterialsInstitute, Inc., CHAPTER:

AG AssociatesAmerican Technical CeramicsApplied Electron CorporationASYST Technologies, Inc.Coors Ceramics CompanyDynapert/AmedyneEagle-Picher Industries, Inc.Emergent Technologies CorporationFEP AnalyticFSI CorporationGenus, Inc.Gryphon ProductsHercules Specialty Chemicals Companylon Beam Technologies, Inc.Ion Implant ServicesLehighton Electronics, Inc.Logical Solutions Technology, inc.MacDermid, Inc.Machine Technology, Inc.MG IndustrieslScientific GasesMicrion CorporationThe Micromanipulator Comany, Inc.Oneac CorporationOptical Specialties, Inc.PT Analytic, Inc.Pacific Western Systems, Inc.Peak Systems, Inc.Sage Enterprises, Inc.The SEMI Group, Inc.Silsco, Inc.SlLVACO Data SystemsSOHIO Engineered Materials CompanySolid State Equipment CorporationTechnology Modeling Associates, Inc.Thermco Systems, Inc.UTI Instruments CompanyVLSI Standards, Inc.XMR, Inc.

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InstitutionsArizona, University ofAuburn UniversityBrown UniversityCalifornia at Berkeley, University ofCalifornia at Los Angeles, University ofCalifornia at Santa Barbara, University ofCalifornia Institute of TechnologyCarnegie-Mellon UniversityCase Western Reserve UniversityClemson UniversityColumbia UniversityCornell UniversityDuke UniversityFlorida, University ofFlorida State UniversityGeorgia Institute of TechnologyIllinois at Urbana/Champaign, University ofThe Johns Hopkins UniversityLehigh UniversityMassachusetts at Amherst, University ofMassachusetts Institute of TechnologyMichigan, University ofMicroelectronics Center of North CarolinaMinnesota, University ofNebraska at Lincoln, University ofNorth Carolina at Chapel Hill, University ofNorth Carolina State UniversityOregon Graduate CenterPurdue UniversityRensselaer Polytechnic InstituteResearch Triangle InstituteRochester, University ofRochester Institute of TechnologySouth Florida, University ofSouthern California, University ofStanford UniversityTexas at Austin, University ofVermont, University ofYale University

Malcolm L. White, Research Scientist at LehighUniversity, uses a vacuum evaporator to depositaluminum on glass substrates for semiconductorcorrosion studies. (This photograph and the o n eon page 26 appeared in the ”Lehigh ResearchPerspective 1987” and are used with permissionof journalist/photographer Kenneth A. Friedman,3061 Powder Mill Circle, Bethlehem, PA 18017.)

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Cooperative ResearchConcept

Cooperation

High quality research follows from awell-planned program that uses thebest information, concepts, andresources.

Characteristics of the SRC Research Program:

DEFINITION. From the outset, the SRC ResearchProgram has responded to a set of goals defined byrepresentatives from the SRC member companies.These goals provide a framework for selection ofuniversity-based research projects that are relevantto the needs of the industry and will result in a 20%acceleration in the pace of basic semiconductortechnology by the year 1994.

FOCUS and DIRECTION. Roadmaps have beendeveloped by industry representatives to refine andinterpret the overall SRC research goals for theselection of specific research thrust areas andprojects. These roadmaps are living documents thatallow for continuous fine-tuning to adjust to changesin strategy, funding, and the technology.

CONTROL. SRC research funding is distributedthrough formal contracts calling for deliverables onan agreed-to schedule.

ACCOUNTABILITY. Research funding is providedthrough a cost-reimbursement system that is keyedto recipients’ meeting contract obligations.

CREATIVITY. Topics under study in universitylaboratories are sufficiently flexible to accommodateinnovation.

BROADENING THE UNIVERSITY BASE. SRCresearch funding allows universities to hire addi-tional faculty, and to update research equipmentand facilities. SRC support also helps universitiesattract additional funding from other sources. TheSRC, in 1987, initiated a program for development ofinterdisciplinary curricula for the education of micro-electronics manufacturing engineers.

ATTRACTING GRADUATE STUDENTS TOINDUSTRY-RELATED FIELDS. By enabling univer-sities to conduct research that is relevant to thepractical needs of the industry, the SRC has attractedmore than 500 highly qualified graduate students towork on SRC projects that prepare them for theindustry’s manpower needs.

DEPTH. The communication and interaction that areencouraged among academic/industry/governmentresearchers of the SRC community not only serve tostrengthen the SRC research program and to keepmembers informed of its progress, but also help toreduce research redundancy among industry/government/university participants.6

“The SRC played a keyrole in creating our currentsemiconductor programat Michigan. [The SRC’s]direct investment is closeto $2.3 million and that,plus [ the SRC’s] influence,has enabled us to attractState and Federal supportin the amount of over $16million in facilities andabout $8 million in annualresearch.”

— Professor K.D. Wise

UPDATE TO UNIVERSITY FACILITIES. Among the advantages universities gain from SRCresearch funding is the opportunity to update equipment and expand facilities for state-of-the-artresearch. Shown above is a Solid-State Fabrication Facility built, in part, with SRC funding to theUniversity of Michigan Program in Automated Semiconductor Manufacturing. This project usesreactive ion etching as a process vehicle for examining key issues associated with automatedsensing, control, and process integration (see research highlight on page 21).

QUALITY. SRC research is continuously monitoredby the SRC technical staff and regularly reviewedand assessed by industry experts for qualityassurance.

RESULTS: TECHNOLOGY

... a supermarket of research results has beenmade available by university researchers fortransfer to industry members,

“ . . . we found the VLSI design automationresearch extremely relevant to our industrialapplications. The fact that it is followed in manycases by actual programs of high quality, makesit even more attractive . . . ”

— National Semiconductor

. . . inventions and new or improved processeshave been transferred to industry,

“If not for the availability of this valuable sourceof information, it would have taken us weeks orpossibly months to get the technique working;”

— Emergent Technologies.

. . . a variety of software packages has beenreleased to the mainstream.

“These programs have proven very useful andhave had a major impact on our ability to designand analyze packages” — Honeywell.

RESULTS: MANPOWER.

. . . The SRC research program has tripled thepopulation of graduate students who will makethe seminal inventions of the next decade andwill comprise the manpower base of the futureindustry.

. . . Over the last five years, more than 150 studentswho conducted research under SRC contractshave completed requirements for the Master’sor Ph.D. degrees and have joined the U.S. workforce. Most of these persons are now employedby SRC member companies or have joined thefaculty of U.S. universities.

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CooperationTechnology Transferin Action

Activities, events, andcommunication mechanisms areoffered by the SRC to expedite thetransfer of technology and to fostercooperative interaction among theindustry engineers and scientists,university researchers, andgovernment technologists whoparticipate in the SRC Community.

Events

The following major SRC technology transfer eventsin 1987 provided opportunities for exchange of infor-mation among industry, government, and academicparticipants in the SRC community. A total of over 750persons participated.

January 19: The workshop on Technology Transfer reviewedtechnology transfer practices currently in use at member com-panies and identified key technology transfer issues for industry.Three working sessions addressed (1) barriers and solutions. (2)measurement and reporting, and (3) information dissemination. AnSRC technology transfer roadmap was developed.

February 23 and 24: A two-day Technology Transfer Course onFABRICS provided discussions and laboratory hands-on use ofFABRICS, PROMETHEUS, PED, and PI/C. an Integrated suite ofcomputer tools that provides synthesis support for the design ofmanufacturing processes that minimize the effects of randomfluctuations and thus maximize yield.

March 17 and 18: The Topical Research Conference on Reliabilityof VLSl Circuits discussed future directions of reliability as relatedto oxides, electrostatic discharge, electromigration, packaging,equipment, and design.

April 21 and 22: The Topical Research Conference on AdvancedMOS Process and Device Modeling assessed state-of-the-artprocess and device modeling research, postulated needed futureresearch directions, and provided insight on the need for super-computing in microelectronics technology CAD.

May 74: A workshop on Semiconductor Fabrication Equipment:Vendor-User Synergisms discussed the nature of vendor-userrelationships and identified means for increasing benefits fromthese interactions in the U.S. semiconductor fabrication equipmentindustry.

May 28 and 29: At the Bipolar Device Technology conference,university and industry researchers who work at various levels ofmodeling/simulation discussed the full range of activities currentlybeing pursued in bipolar devices and circuits.

June 3 and 4: At the DARPA/SRC Workshop on Computer-Integrated Manufacturing (CIM) researchers explored theadvantages of CIM, flow languages, data models, scheduling,system architecture, equipment models, management tools, andinformation dissemination via networks.

June 16: The DEC/SRC Workshop on Technology Transfer inJapan covered corporate technology transfer processes in Japanand the U.S. Discussion areas included public policy, corporatephilosophy, management strategy and industrial/interrelationships,societal factors, educational system, technology transfer mecha-nisms, internal technology acquisition, and measurements ofsuccess.

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Photos: UPPER — Professor Michael Borrus,Deputy Director of the Berkeley Roundtableon International Economics, addressingforum audience; LOWER — Joseph L. Bowerof the Harvard Business School, leader of

forum panel.

June 29 to July 3: The joint SRC/Institute for Theoretical PhysicsWorkshop on Quantum Domain Devices discussed the inter-action of quantum mechanical and (quasi-)classical phenomeno-logical models, localization and interference effects, fluctuations,and the novel physics associated with small systems with a focuson “What can submicron technology do for informationtechnology?”

July 8 and 9: A technology Transfer Course on Technology CADfor BiCMOS Design provided lecture sessions and hands-on labexperience using a one-dimensionaland a two-dimensional TCADtool set for BiCMOS design. Future plans for tool developmentunder SRC sponsorship were discussed.

September 15 and 16: The Topical Research Conference onDesign Verification assessed the current state of the art anddefined areas requiring further research. It was decided that designverification would still be a relevant system design process for the1990s.

November 5 and 6: The Topical Research Conference onPackaging Reliability Without Hermeticity covered operatingenvironments, mechanisms of failure, physical chemistry of mois-ture films, contamination thresholds, and ionic activity.

November 13: Participants in the Workshop on Data Managementfor IC CAD were introduced to the Berkeley OCT / VEM / RPCdesign environment through presentations and on-line demonstra-tions and provided with an industry view of data managementrequirements for IC design systems of the 1990s.

November 20: At thesecond DEC/SRC Workshop on TechnologyTransfer in Japan, findings from interviews and literature searchesfor a project to explore technology transfer mechanisms beingpracticed in Japan and the United States were presented.

December 10 and 11: A Topical Research Conference onSubmicron BiCMOS Technology for the 1990s included dis-cussions of significant advances in process integration, unitprocesses, and circuit design. Critical issues were identified inorder to define future research directions and to provide recom-mendations on how to cost-effectively marry CMOS and bipolartechnologies to achieve a submicron BiCMOS technology.

Competitiveness ForumThe SRC arranged a forum on “U.S. Competitive-

ness — Analysis and Remedies,” by a panel of fourdistinguished scholars from the Harvard BusinessSchool and the Berkeley Roundtable on InternationalEconomics for a joint meeting of the SIA/SEMATECH/SRC boards in September. The panelists analyzed therelationship of national culture, manufacturing systems,and marketing approaches to a country’s economicsuccess in the international marketplace. lmprove-ments were suggested for U.S. business, industry, andeducation that would strengthen this nation’s competi-tive capability. Representatives from the U.S. semi-conductor industry comprised the audience of morethan 100 persons.

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CooperationTechnology Transfer inAction (continued)

SRC fellowship recipients Michael Neacsu (left), graduatestudent at the University of North Carolina at Chapel Hill, andThomas Cobourn, graduate student at Carnegie-MellonUniversity.

Fellowship Banquet

The SRC honored the 29 students who have beensupported by SRC Fellowships with a banquet onOctober 19 at the Governors Inn at Research TrianglePark, NC. Sharing dinner were members of the SRCtechnical staff and the newly appointed FellowshipProgram Industry Advisors. On October 20, the stu-dents conducted a ‘poster session” to familiarize theindustry Advisors with research being done in respec-tive graduate programs. The advisors are staff fromSRC member companies who have volunteered toestablish a one-on-one relationship with a Fellowshiprecipient throughout his or her doctoral studies. Thismeeting generated enthusiastic interactions not onlybetween advisors and students, but also among stu-dents who discovered areas of similar researchinterest.

Government Participation

Recognizing that the stakes are high and the risksreal for the U.S. economy and national security if thiscountry does not have a world-class and competitivesemiconductor industry, three agencies of the federalgovernment agreed in September, 1986, to participatein the SRC. In 1987, a fourth agency became aparticipant — the National Bureau of Standards.

Agency scientists and engineers contribute tech-nical expertise to the research program and share in allphases of SRC activity with members of the universityand industry community. The Government Coordi-nating Committee (GCC) of the SRC has the respon-sibility to provide the technical link between the variousparticipating government agencies and the SRCResearch Program. Mr. K. Speierman of the NationalSecurity Agency has served as the GCC Chairmansince its inception. Other members of the committeeinclude.. Mr. E.D. “Sonny” Maynard (Department ofDefense), Dr. Alan Stubberud (National ScienceFoundation), Mr. C.E. Holland, Jr. (SRC Resident Pro-gram Manager assigned by DoD), and Mr. Frank F.Oettinger (National Bureau of Standards). The GCCactively developed plans in the latter part of this year tosignificantly increase government agency and per-sonnel participation.

Evaluation

The first in a series of evaluations of SRC research atuniversities with major cumulative investments wasconducted in 1987. An evaluation team examined SRCresearch at Cornell University, which has receivedover $7 million in funding since 1982 for investigationsdirected to long-range objectives in process anddevice technology, and, more recently, in packaging.

The evaluation team concluded that Cornell’s multi-disciplinary research effort, involving 28 facultymembers and 47 graduate students in 1987, waseffectively addressing SRC goals and objectives.

Recommendations were made to the SRC tostrengthen Cornell’s sensitivity to patents and to guardagainst excessive focus at the expense of creativity.Cornell’s role in the SRC research agenda is to providea scientifically strong effort directed toward submicronprocess and device technology with a focus on one-quarter micron CMOS; and, in packaging, to concepts,materials, and base technologies.

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Resident Managers

Resident Managers are employees of member com-panies or government agencies who are assigned toSRC headquarters as technical staff for periods of oneor more years. As members of the staff, the residentscontribute the benefit of their experience to the SRCresearch program and share in monitoring the researchcontracts. Having an employee on site for continuousaccess to the research is an excellent mechanism formaximizing technology transfer. Listed in the fablebelow are the Resident Managers who have reinforcedthe corporate staff since the SRC’s inception.

The response of member companies and govern-ment agencies in providing a growing number ofResidents as staff assignees significantly enhancesthe efficient and effective management of SRCresearch.

The SRC Newsletter

The monthly SRC Newsletter provides informationfor and about the SRC community. The newsletter isavailable free of charge to the staff of member com-panies, participating government agencies, and U.S.universities. Circulation increased by 20% during 1987,reaching 5,000 copies by year’s end. Seventy-fivepercent of the subscribers are member companypersonnel.

Publications

In 1987, the SRC distributed over 12,500 copies ofpublications generated from university research andby the SRC staff. The SRC library catalogued 954 newresearch documents from January through December,and, by the end of the year, its inventory containedmore than 2,800 SRC publications.

Information Central

Use of information Central, the SRC’s on-line tele-phone database and mail facility, continues to provide24-hour-a-day benefits for the staff of industry/government members and university contractors. Off-site users logged over 840 hours of connect time in1987 to obtain information about SRC research andrelated activities. In addition to dialup usage of infor-mation Central, electronic communications amongmember companies, universities, and the SRC viaCSNET-Internet increased substantially.

Resident Managers *

Name Assigned From Period of Residence Area of Responsibility

Benjamin J. Agusta IBM 1983-1984 Microstructure SciencesRichard A. Lucic HP 1983-1984 Manufacturing SciencesJames R. Key CDC 1983-1985 Technology TransferJohn J. Cox DuPont 1984-1985 PackagingPatrick W. Wallace DuPont 1984 PackagingJeffrey A. Coriale Harris 1984-1987 CMOS-BiCMOSShakir A. Abbas IBM 1985-1987 Bipolar Technology/ReliabilityPhillip A. Lutz GM-Delco 1986- PackagingNorman F. Foster ATT 1987- Manufacturing Science/ReliabilityC. Edward Holland, Jr. DoD 1987- Government InterfaceKenneth L. Pocek Intel 1988- Design SciencesJeffrey L. Hilbert Motorola 1988- Design SciencesVincent Lyons IBM 1988- TECHCON 88

*Additional staff from member companies have served as Ad Hoc Assignees to assist in implementing TopicalResearch Conferences and Workshops or for short-term management of other activities.

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Cooperation

The SRC and Cooperative Initiatives

The success of the SRC in demonstrating theeffectiveness of cooperation has led to its being calledupon to participate in other efforts aimed at respondingto competitiveness issues for the U.S. semiconductorindustry. Primary among the SRC’s contributions toother efforts is a unique understanding of the statusand future directions of semiconductor technology thathas been gained while defining and implementing itsown generic research program with the industry.

SEMATECH

SEMATECH is the most prominent and highestimpact initiative that involved the efforts of the SRCstaff during 1987. This is an industry/governmentcooperative endeavor that reached an advanced plan-ning phase by the beginning of 1988 and that will belocated in Austin, Texas. The aim of SEMATECH is toensure a domestic, world-class semiconductor manu-facturing capability by 1993 through focused develop-ment and application of modern manufacturingtechnology.

The SRC has participated from the outset in definingthe need for, the thrust of, and gaining support forSEMATECH. The SRC's president, Larry W. Sumney,has had a key role as Managing Director for SEMATECHin its startup phase, and the SRC’s research staff havecontributed to the planning process. SEMATECH hasidentified the SRC as its agent for implementing andadministering a supportive research program. Theoperational concept for SEMATECH is shown in thediagram.

The university-based program already establishedby the SRC provides a strong foundation on which tobuild a research agenda for SEMATECH. Priorityresearch needs of SEMATECH have been identified insuch areas as optical lithography, metrology, manu-facturing systems, etching, multilevel interconnectionsystems, and packaging.

The SRC will carry out a research program in supportof SEMATECH in much the same mode as it hasplanned and implemented its existing research pro-gram since 1982, although funding for the two pro-grams will be distinct. Most of the results of bothprograms will be available to all SRC participants, andSRC research results will be fully accessible bySEMATECH.

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Charles E. Sporck (left), Chairman of the SEMATECH Board ofDirectors, with Larry W. Sumney, President of the SRC.

SEMATECH Concept

Formulation of a research plan for SEMATECH wasbegun in the latter part of 1987, and the first step insetting up the program was taken at the beginning of1988 when a Centers-of-Excellence program wasinitiated. These centers will not only conduct research,but will also provide knowledge resources forSEMATECH’s use during its aggressive developmentefforts.

Additional SEMATECH research initiatives mayextend beyond academic laboratories to other institu-tional participants in semiconductor research. How-ever, plans for these activities were still in the earlystages by the end of this calendar year.

National Advisory Committee onSemiconductors (NACS)

Legislation was introduced in 1987 in the UnitedStates Congress for the establishment of a prestigiousadvisory body on domestic semiconductor R&D activi-ties. The motivation for a National Advisory Committeeon Semiconductors is to improve the competitivestrength of the U.S. industry by increasing the efficiencyof its diverse R&D efforts. One approach that could betaken by an NACS would be to provide an overview ofthe programmatic and technical components of thenation’s semiconductor research activities, and toconduct a coherent analysis of its competitive statusand needs.

The SRC has participated in defining the NACSconcept and has consulted with the Congress andothers in bringing this proposal to its present stage. It isanticipated that if this proposal is enacted, the SRC willcontinue to cooperate in making it a success.

0ther Cooperative Activities

Other activities of the government and industryrelated to cooperatively addressing semiconductorissues in which SRC staff have been engaged includeparticipation on advisory committees of the NationalScience Foundation, the Department of Defense, andthe National Academy of Sciences. The SRC is alsorepresented in ongoing Semiconductor Industry Associ-ation (SIA) activities that focus on industry concerns.At the SIA/SRC Joint Conference in September, aforum was organized and conducted by noted acade-micians to analyze broad issues regarding U.S.competitiveness.

The above photograph taken at the Sandia National Labora-tories includes the following workshop participants (left toright): Dr. W. Dale Compton, Senior Fellow, National Academyof Engineering; Dr. William C. Holton, SRC Director forMicrostructure Sciences; Dr. Louis C. lanniello, DOE DeputyAssociate Director for Basic Energy Sciences and leader of theDOE National Laboratory Task Force Group; and Dr. VenkyNarayanamurti, Vice President of Research, Sandia NationalLaboratories.

The Semiconductor Industryand the National Laboratories

The SRC has been active in representing the U.S. semi-conductor industry at meetings to plan government/industry initiatives toward developing a national strategyfor the efficient use of domestic resources. One of theseinitiatives, under the auspices of the National Academy ofSciences, is aimed at implementing a cooperative effortbetween the research resources of the US. semi-conductor industry and the facilities and expertiseavailable at the U.S. Department of Energy’s NationalLaboratories, A Workshop held at the Sandia NationalLaboratories on May 26 to 28, 1987, was the first in aseries of technical-level planning meetings for this effort.

In November, a follow-on meeting to the SandiaWorkshop was held at Oak Ridge National Laboratory.This series of meetings will continue at other NationalLaboratory sites to articulate specific areas of theindustry’s generic research needs that conform to thecapabilities of the National Labs and to allow the NationalLaboratories to determine how they could mobilize theirresources to address those research needs.

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Research

The SRC’s ResearchProgram is based upon avision of the futurederived by working withthe industry on goals.

This vision allows one to forecasttrends in semiconductors over thenext several years with considerableconfidence and to create a researchagenda that accelerates U.S.technology development whileretaining flexibility for response tonew ideas and findings.

SRC Research Goals

The SRC Research Program addresses indus-try needs for improved performance and higherdensity integrated circuits. In brief, the overallgoals are to make possible in 1994 the prototypeproduction of chips with:● complexity 250 times greater than those of

1984 (equivalent to a 256 Mbit DRAM),

● functional throughput rates of 5 x 101 5 gate-hertz per square centimeter,

● reliability such that less than 10 failures occurin 1 billion operating hours,

● cost per functional element reduced by 500times from 1984 costs.In 1988, the SRC is planning to update and

extend these goals to the year 2001.

Research Directions

Although limited to topics associated with main-stream silicon semiconductor technology, the SRC’sresearch agenda covers a broad spectrum. Majoridentifiable thrusts encompass a majority of the pro-gram. The following subjects represent most of themajor thrusts, some results from which are presentedas research highlights on the next twenty-four pages:

● 0.25 micron CMOS/&CMOS● process and device modeling● computer-automated semiconductor manufac-

turing (CASM)● VLSI architectures● high performance bipolar technology● high performance packaging● design synthesis● single wafer processing● reliability and yield enhancement● analog ICs● advanced process technology● design for test● curricula development for microelectronic manu-

facturing engineering education.In addition, efforts are underway in other areas, such asquantum domain devices, metrology and robotics.

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Each of the thrusts identifies a research area that is apart of the SRC agenda and serves as a focus fordefining future directions. This analytical process iden-tifies high-impact microelectronic technologies for thenineties and beyond.

At present, little evidence appears to justify goingbeyond the 1/3-1/4 micron design rule capability inintegrated circuits. Greater impact will be obtainedthrough investment in design systems, development ofimproved system architectures, integrated manufac-turing systems, and the hierarchical software andsimulation environments that connect these.

Simulation of submicron semiconductor device pro-duction requires process and equipment models. Thelatter, in particular, do not exist and are proving difficultto obtain. Limits on equipment models may delayachievement of the sought-after ability to bridge simu-lations of system performance and design to those forproduction in order to achieve the economies neces-sary to compete successfully. In-situ and single waferprocessing technologies are replacing batch proc-esses of the past.

Metrology capabilities for submicron IC fabricationare very limited. In-process controls, pattern transfer,failure analysis, and structural control are pushing thelimits of measurement and monitoring capabilities. Thewinner in the race to produce the next generation maybe the possessor of the best measurement capabilities.

The increasing focus on system-level design, coupledwith the complexity of submicron ICs, will presentenormous challenges to design systems and methods.Future designs will require hierarchical methods, formalverification tools, and integrated design environmentssupporting system-level partitioning, extensive use ofsynthesis, and early evaluation of design tradeoffs —including performance, testability, reliability, yield, andcost.

Design systems will be extended to cover the designprocess from architectural-level system designthrough modeling of physical phenomena; device,materials, process, and equipment design; andmechanical and thermal considerations. Concurrentuse of multiple technologies, large data volumes, andsupercomputer systems and distributed hetero-geneous networks will require integrated design dataand process management.

CAD will extend to detailed thermal, electrical, andmechanical features of multichip subsystem packages.

Research Program Commitments($ in Millions)

Trends in funding levels for SRC research are shown above.The growth of total funding through 1986 ended as the pool ofpotential new members decreased and fees from the presentmembership were affected by the industry recession. A rever-sal of this trend is occurring for 1988. Not shown, because keydecisions are still being made, is the large impact thatSEMATECH funding will have on SRC research activity. TheSRC has been evaluating proposals for the SEMATECHCenters-of-Excellence initiative that will be managed throughthe SRC. This may result in a 25 percent increase in funding forresearch during the next calendar year.

The distribution of funding among the research areas is beingbrought into approximate balance according to plan. Theapparent decrease in program expenditures for ManufacturingSciences from 1986 to 1987 is, in part, an artifact resulting fromthe timing of year-end contract awards. It must be noted thatthe three major program areas are thoroughly integrated andsuch boundaries as may exist between them are not distinct.

15

ResearchCMOS andBiCMOSTechnology

As integrated circuit technologyapproaches thephysical limits of classi-caldevice technology at approximately0.1 micron minimum feature size, singlechip designs will serve for many systemapplications; and, advanced packaging,employing “silicon backplanes,” willprovide for enhanced-capability multi-chip interconnected systems.

SRC CMOS circuit technology per-formance goals for 1994 are a0.25 micron minimum feature size thatwill lead to device densities of 40 x 106

transistors/cm2 for logic designs and200 x 106 transistors/cm2 for DRAMmemory. Performance goals are a50 picosecond pair switching delaywith a 5 femtojoule/gate (power xdelay) product. Circuits will require aminimum of four levels of interconnect.

As minimum feature size is reducedand manufacturing yields improve(thereby reducing the cost adder ofadditional process complexity) BiCMOSis emerging as the leading edge tech-nology for high-performance mixedlinear/digital applications, digitalsignalprocessing, data acquisition systems,and, ultimately, high-speed digital logicand memory. SRC research is orientedto support this strategy, and technologyroadmaps for both CMOS and BiCMOSare being prepared to provide guidancefor the research.

Complementary BiCMOS technologythrusts in support of the SRC strategyhave been initiated at MIT, Stanford,and the University of California atBerkeley. A key aspect of the tech-nology involves the development of adesign and a fabrication process thatwill permit decoupling of the perform-ance parameters of the bipolar andCMOS components — allowing optimaltuning of the bipolar device to maximumspeed or higher voltage as required bythe circuit application, without com-promising the performance of theCMOS elements.

16

SEM view of 0.25 µm n-channel MOS devices. Zoom window shows active region ofMOSFET with effective channel length of 130 nm and effective gate width of 2.5 µm.Source-drain regions are silicided from the sidewall spacer outwards. CornellUniversity.

Device/ Process Integration for 0.25 Micron CMOS

Drain current-voltage characteristic ofn-channel MOSFET with effective chan-nel length of 90 nm and gate width of2.5 µm at a temperature of 77 K.

Researchers at the SRCICornell Centerfor Microscience and Technology are invest-igating device structures, related unit proc-esses, and process integration of 0.25 pmCMOS devices via design, fabrication, char-acterization, and analysis. Compatible E-mode 0.25 µm n-channel devices havebeen investigated in an E/D mode NMOSenvironment. The 0.25 µm NMOS processhas been employed during 1987 for processand device experiments in order to com-plete the characterization of n-channeldevices down to channel lengths of 100 nm.

Professor J. Peter KrusiusCornell University

MIT BiCMOS Technology

The MIT BiCMOS process is oriented toward mixed analog/digital applications and isserving as the development vehicle for a 16-bit analog to digital converter. Theprocess uses epi wafers and offers fully optimized NMOS, PMOS, and semi-oxideisolated vertical n-p-n bipolartransistors. In addition, MOS capacitors with n+ bottomplates, and non-optimized vertical p-n-p bipolar transistors are available.

The cross section of devices available is shown in the large figure above that wasprepared by Kenneth O, an SRC-supported graduate student. The device character-istics for the MOS and n-p-n bipolar devices are shown in the three smaller figuresbelow.

Professors L. Rafael Reif and Hae-Seung LeeMassachusetts lnstitute of Technology

NMOS Device: gate width 20 µm, gatelength 2 µm, Threshold Vt = +0.75 V,VSB = 0, = 1 volt steps.

PMOS Device: gate width 20 µm, gatelength 2 µm, Threshold Vt = -0.85 V,VSB = 0, = -1 volt steps.

Accurate Simulation of Shallow Boron ImplantationShallow boron profiles are required in

submicron CMOS circuits and are producedby low energy implants of B+ or ions.Because Boron can channel so easily intosilicon, the simulation of as-implanted boronprofiles has been quite difficult. LSS theoryfails to predict these profiles because if isstrictly valid for implantation info amorphousmaterials for which there is no channeling.The use of a Pearson distribution offers onlylimited improvement. A new simulationapproach has been successfuly applied forboth and implants. This physically

based approach uses the sum of two Pear-son functions that accounts for the chan-neling and nonchanneling events, respec-tively. The ratio of the two functions variessmoothly with the logarithm of the dose. Asimulated profile based on this newapproach is illustrated for B+ implants. Thenew approach provides accurate simulationof the entire profile for all energies anddoses.

Professor A.F. TaschUniversity of Texas at Austin

Vertical n-p-n Bipolar Device:Emitter length 6.0 µm,Emitter width 6.0 µm.

17

Research

Process and Device ModelingAccurate models are required for the Several efforts are underway to

design of processes and devices in the devise improved circuit-level devicesubmicron regime. In turn, successful models. At the California Institute ofintegrated circuit design depends on Technology, an accurate, physically-the availability of good circuit-level based charge model has been devel-models for the circuit components. oped that expresses intrinsic charge inSeveral projects in the SRC research a MOS device as a single continuousportfolio address the development of analytic expression that is equally appli-improved models and simulators for cable in the saturation and ohmicprocesses and devices. Work has con- regions of operation. Accurate andtinued on the extension and refinement efficient table look-up models are beingof the leading-edge SUPREM 4 and developed at the Georgia institute ofPISCES 2 process and device modeling Technology for analog applications.programs (see research highlight on The BSlM modeling and characteriza-following page). A class of difficult tion system for MOS devices fromprocess modeling problems involves Berkeley is being extended to providethe representation of creep-flow phe- accurate models for 0.25 micron chan-nomena that arise in IC processing. nellength devices, Work is focusing onSRC research at Berkeley has resulted representation of temperature effects,in a prototype simulator, CREEP, for hot electron ef fects, and non-this class of problems (highlight below). quasistatic charge effects.

SIMPL is a tool for simulating andviewing the cross-sectional structureof VLSI wafers, given mask and processdata. An interactive workstation inter-face has been developed for SIMPL,and a capability for identifying potentialtopography problems has been added.SIMPL is now being linked to moredetailed process simulators such asCREEP and SAMPLE via the PIF dataformat.

CODECS is a mixed-level circuit anddevice simulator that supports the inclu-sion of one and two-dimensionalnumerical models along with circuitmodels. This mixed-level simulationcapability allows the user to explore theeffect of process-related parameters,such as doping profiles, on circuitperformance.

CREEPCREEP is a two-dimensional process

simulator designed to solve certain creep-flow problems encountered in IC fabricationtechnology. Its most important capability isthe prediction of general 20 silicon oxida-tion. It also performs glass-reflow or film-shrinkage simulation as subset problems ofsilicon oxidation. CREEP incorporatesstress-dependent silicon oxidation modelswhich have been shown to accurately pre-dict the retardation of oxidation on cylindri-cal silicon surfaces. CREEP is equippedwith a flexible and robust data structure forhandling geometrical information. All geo-metrical structures are represented usingnodes and segments. Hence, fairly generalgeometrical structures can be handled. Anautomatic finite element mesh generatorhas also been built into the CREEP program.The figures show simulations of a silicongate and a LOCOS structure to illustrate thecapability of the mesh generator. In bothcases, the user specifies only a mesh-

18

Gate Oxidation

density parameter (about 10 µm in theexamples shown). The mesh is then gen-erated automatically by CREEP at everytime-step of the computation.

Professor William G. OldhamUniversity of California at Berkeley

LOCOS

Integrated Technology Computer-Aided Design (TCAD)SUPREM 4 contains advanced kinetic

models for processes such as nonplanar(trench) oxides and source/drain diffusionsengineered to reduce hoi carrier effects.The figures show typical structures withSUPREM 4 coupled directly to PISCES 2 toextract pertinent electrical parameters. Theupper figure compares the critical electricfield strength for a corner after a single900°C dry oxidation and a smoother cornerwhich has been oxidized, stripped, andreoxidized. The contour lines and peakelectric field values indicate the importanceof having accurate models for stress-dependent local oxidation. These resultscan help improve fabrication of more reli-able oxides for DRAMS and isolation. Thesecond figure shows the process anddevice simulation of a novel MOS devicewith local ion implantation used to reducehot carrier effects at the drain. Based onaccurate 2D profiles from SUPREM, theelectrical characteristics obtained withPlSCES 2 are shown. Previous ID profilesused for quasi-2D analysis were inadequateto match experiment. The PISCES codenow includes new mobility data and anaccurate avalanche generation model.Excellent substrate current predictions cannow be obtained for 0.5 µm channel lengthdevices — both conventional and LDDconfigurations.

Professors Robert W. Dutton andJames D. Plummer

Stanford University

SUPREM 4 simulations of local oxidation with contours of electric field computedusing PISCES 2.(Left) single-step oxidation showing 1450 V/µm peak electric field.(Right) two-step oxidation showing 450 V/µm.

Process and device simulations of the JMOS device designed to reduce hot carriereffects at the drain by creating a local buried JFET.(Left) SUPREM 4 cross section showing p+ island to drive the current subsurface intothe JFET.(Right) Comparison of experimental results and PISCES 2 output using SUPREM 4impurity profiles.

19

CASMComputer-Automated Semicon-

ductor Manufacturing (CASM) is asignificant new research thrust thatincludes programs aimed at developingthe tools needed to automate the ICmanufacturing process.

Substantial automation of both waferprocessing and factory managementwill be needed to obtain the degree ofmanufacturingprocess control requiredto meet the goals of the industry for the1990s. The differing approaches takenby university investigators for SRCCASM research have resulted in amatrix of complementary programs todevelop some of the building blocks forestablishing such automation. Theprocess/circuit modeling activities thathave long been the strengths of theprograms at Stanford and UC/ Berkeleyare now being extendedinto the criticalprocess/equipment modeling requiredfor real-time, closed-loop control andintegration of fabrication. A completelyintegrated and automated semicon-ductor fabrication facility is beingmodeled, based on a fundamentalunderstanding of the unit processesand the development of an associatedfactory simulation (virtual factory) thatwill allow the testing of the manufac-turability of a design before committingit to silicon.

At the University of Michigan, re-search is more sharply focused onequipment/process modeling and, inparticular, on the development of sen-sors for in-situ monitoring of the param-eters needed for real-time processcontrol.

The contribution to CASM byCarnegie-Mellon addresses the tech-niques needed to analyze masses ofdata generated by the many testing/characterization facets of the waferfabrication process. The focus is onsophisticated statistical tools for estab-lishing correlations between sets ofparameters, such as wafer test resultsand process conditions.

20

Research

MODES Representation of a Portion of a Fabrication Line.

Programmable and Virtual FactoryThe objective of this program is the

development of tools and methodologiesthat will enable reproducible, high-yield,low-cost, flexible manufacturing of VLSIcircuits. The approach being used is tosimulate and, then, to control a computer-integrated manufacturing (ClM) line. Thebenefit of this research will be the predictionand control of process, device, and circuitparameter distribution resulting from normalmanufacturing variations. Two representa-tions of a VLSI fabrication facility will becreated: the programmable factory and thevirtual factory. The programmable factory isan integrated system of manufacturingequipment, sensors, and computer hard-ware and software in an actual fabricationenvironment. The virtual factory represents

a factory that can be run in simulation on acomputer workstation. A wafer fabricationfactory simulator, MODES (Modeling Dis-crete Events Simulations), has been devel-oped. MODES is a CAD tool for wafer fabdesign, optimization, and operation that willalso double as a prototyping vehicle for theCIM interface to the Programmable WaferFabrication Line. It is being developed as ademonstration platform for exploring repre-sentations and techniques for semicon-ductor manufacturing modeling and simula-tion. This software uses a mixture of graphi-cal and procedural specification to repre-sent the manufacturing line and its behavior.

Professor Krishna C. SaraswatStanford University

Sensors for Process AutomationAchievement of the real-time process

control needed to meet the stringent require-ments of automated submicron manufac-turing will require in-situ measurement ofmany process parameters. The Automationin Semiconductor Manufacturing Programat the University of Michigan is developingsilicon-based integrated sensors to meetthis need, with emphasis on the reactive ionetching (RIE) process. First prototypes ofmonolithic integrated sensors for gas pres-sure, flow, and composition have beencompleted for use in reduced-pressureetch systems. A standardized sensor inter-face has also been defined for these devicesand is being integrated. The bidirectionalinterface transforms the sensor chip into asmart peripheral, which features self-testing, flexibility in features, rapid response,and high precision, using PROM-baseddigital compensation. Expert-system soft-ware has been developed to allow controldecisions based on data from sensors, fromin-situ wafer monitoring, and from down-stream cells employing machine vision.

Professor Ken D. WiseUniversity of Michigan

An Integrated Pressure-Based Microflow Sensor for Semiconductor Process Gases.

Block Diagram of an Integrated VLSI Sensor for Use in Automated Manufacturing.

21

ResearchVLSI Architectures

Research in VLSI architectures isintended to explore high risk/highpayoff opportunities where novel struc-tures can exploit the inherent com-plexity of VLSI systems to achieve newfunctionality and/or enhanced perform-ance. As an example, connectionistarchitectures may offer new computa-tional paradigms, but they also providea challenge to VLSI design because oftheir high connectivity requirements(see research highlight from ProfessorHammerstrom). VLSI architectures arealso driven by data input/output con-straints In many image processingproblems, data are naturally availablein scan-line order; and, thus, the archi-tecture must be matched to this con-straint in order to obtain optimum per-formance (see research highlight fromProfessor Liu). Special computationalprocedures are often so widely usedthat consideration of special architec-tures to expedite execution is war-ranted. An example is the general areaof finite element computation thatrequires a significant commitment ofcomputing resources for many applica-tions. A new architecture that appearsto be nearly optimum for the operationsrequired in the solution of finite elementproblems has been devised and isdescribed in the highlight from Pro-fessor Preparata.

It often turns out that the synthesis ofan effective VLSI design requires theconduct of interactive architecturaltradeoffs from the system level down tothe bit level. In the design of a chip to beused in an adaptive sidelobe cancelersystem having many applications incommunications, it was found at theUniversity of Southern California that anovel arithmetic scheme, which allowsonly two nonzero bits in the binaryword, provides a very efficient andeffective VLSI realization.

An Architectureto Solve PartialDifferential Equations

The numerical solution of partial differen-tial equations is the essence of many of theproblems in applied engineering and phy-sics. The pervasive application for finiteelement analysis as a numerical method foran important class of such problems moti-vates the identification of a computingstructure naturally suited to the task. SRCresearchers have proposed an architectureappropriate for a dedicated, highly parallelfinite element machine that is efficient fordiverse tasks. The architecture is a 3Dmesh of trees augmented with an additionalplane of processors (organized as a 2Dmesh of trees), some additional connec-tions, and a few matrix registers. This archi-tecture (with nodal processors and ele-mental processors located at the roots ofthe trees in the additional plane) can beused to compute the elemental stiffnessmatrices and load vectors, and to assemblethe global stiffness matrix and load vectorfrom their elemental constituents. The samearchitecture can be used to solve theresulting linear system of equations byNewton’s method and can also be hybrid-ized with a systolic array to achieve aprocessor/time (or area/time) tradeoff.

Professor Franco P. PreparataUniversity of lllinois

VLSI Design for rasterized 2D FET

Architecture proposed by researchers at Illinois forSolving Partial Differential Equations.

22

VLSI Architectures for Multidimensional ProblemsComputational architectures for multi-

dimensional problems are often driven bythe need to handle scan-line input data, andthese architectures must often performoperations on global data. Example applica-tions include problems in image processing,computer vision, linear algebra, and signalprocessing. This research is providing abasis for translating multidimensional com-putational problems, constrained to utilizescan-tine data in real time into equivalentone-dimensional computational problems.Multidimensional Shuffle Exchange net-works (and dual Butterfly networks) can beshown to provide asymptotically optimumperformance for many problems, and thesenetworks are serving as a basis for thisresearch. Necessary and sufficient condi-tions for rasterization for problems involvinggeneral data permutations on multidimen-sional Shuffle Exchange Networks havebeen developed, and a sufficient conditionfor rasterization of general computation isavailable. One of the benefits of the theoryis that matrix transposition associated withthe two-dimensional FFT is no longerrequired.

A VLSI design for rasterized 2D FFTcomputation has been completed and is in

fabrication (see microphotograph at left).The chip contains approximately 152K tran-sistors and is being fabricated in 1.25 µmCMOS technology at the MicroelectronicsCenter of North Carolina. It is projected thatan interconnected set of these chips canperform two 256 x 256 FFT transformationsin real time (30 frames per second).

A second VLSI design based on thegeneral theory will provide a novel bit-levelrasterization for some of the geometricfeature extraction calculations required incomputer vision. The new architectureutilizes a binary tree rather than the con-ventional quad tree and takes advantage ofinformation expansion associated with fea-ture extraction. Other benefits include theachievement of bit-level concurrency, re-moval of the requirement for a frame buffer,and a pipeline structure suitable for VLSIimplementation. It appears that a singlechip implemented in 1.25 micron CMOS willperform feature extraction for a 512 x 512image in real time.

Professor Wentai LiuNorth Carolina State University

rom North Carolina State University

Interconnection Structures for VLSI-BasedConnectionist/Neural Networks

lmportant practical problems are oftenincompletely specified and characterizedby many weak constraints, requiring largesolution spaces. Visual processing andspeech recognition are problems of thiskind. Processing such large data spacessignificantly overwhelms traditional sequen-tial, or low-level parallel computation.Recently a new style of massively parallelcomputation has been receiving attentionas a candidate for processing these largedimensional spaces. Massively parallelnetworks — often called connectionist orneural network models — are characterizedby a number of highly connected, simpleprocessors and are loosely based on bio-logical information processing systems.Fundamental computational limitations arebeing reached in the size of networks that

can be emulated. This computational wall isdue to the extreme connectivity of thesenetworks (generally every node, in even amoderate-sized network, has hundreds ofinput and output connections). SRC re-searchers are examining radically newsilicon-based computing structures. A setof interconnection architectures and hybridanalog/digital computation techniqueshave been developed that are optimized forconnectionist/neural network emulation inVLSI. An Intel iPSC Hypercube-based simu-lation environment has been created thatallows simulation of these architectures,both for correct function and for perform-ance in the presence of typical silicondefects.Professor Dan HammerstromOregon Graduate Center

Chip showing “APN” Silicon ConnectionProcessing Nodes from research at theOregon Graduate Center. (see insideBack Cover)

23

BipolarTechnology

Bipolar integrated circuits haverecently benefited from the continuingshrink in minimum feature size andoxide isolation technology, togetherwith fundamental advances made incooling technology for high-level pack-aging; therefore, bipolar integrated cir-cuits will continue to provide the highestspeed performance of existing siliconIC technologies. The thrust of advancedbipolar technology is the use of dielec-tric isolation to reduce parasitic resis-tance and heterostructures to improveemitter performance. The use of theseadvanced structures has created theneed for new bipolar transistor modelswith more sophistication than existingones. The SRC has reinitiated researchefforts to produce models capable ofadequately predicting the large signalbehavior of the new submicron bipolardevices.

The 1994 performance goals lead toa density of with a 25 picosecond pair delay, a1 power dissipation with apower-delay product of 10 femtojoulesper gate. This will require the use of the0.25 micron minimum-feature-sizedevices.

Research

Mixed-Mode Bipolar Device/Circuit SimulationIt is now apparent that reliable technology

CAD for VLSI must include mixed-modedevice/circuit simulation to predict IC reli-ability and yield as well as performance.The University of Florida Program, whichhas stressed physics-based transistor(BJT) modeling for bipolar circuit simulation,has begun the development of a novelseminumerical mixed-mode simulator,MMSP ICE, for advanced bipolar technolo-gies and, ultimately, for BiCMOS. A prelimi-nary version of MMSPICE, in which a phys-ical charge-based BJT model is writtendirectly into SPICE2G, will be available in1988. The model is implicitly defined by asystem of analytic equations derived fromregional carrier transport analyses. Thesystem of model equations is solved simul-taneously with the circuit nodal equationsby MMSPICE to effect the mixed-modesimulation. The simulator is orders of mag-nitude more computationally efficient thanthe more conventional device simulators inwhich the carrier transport equations aresolved totally numerically, yet is largelypredictive — subject to the uncertainties inthe actual IC structure. The accuracy of theanalytic BJT model is commensurate with

these uncertainties. In the above figure,measured and predicted (with only minimalparameter extraction associated with theuncertainties) current gains are plotted for arepresentative advanced-technology BJT.The accuracy of the simulation is excellentand demonstrates the potential ofMMSPICE. MMSPlCE will be evolved torender it useful for BiCMOS TCAD. Accurateanalytical modeling of integrated infer-connect signal transmission has been donebased on 2D numerical simulations, andseminumerical interconnect models arebeing readied for implementation inMMSPICE. Accounting for interconnectdelay in fast VLSl circuits is now essentialfor predictive simulation. In the future, otherparasitic effects (e.g., latch-up) and reli-ability physics (e.g., hot-carrier effects) willbe modeled and implemented in MMSPICE.MOS and bipolar transistors will be modeledphysically but seminumerically, allowingthe simulator to be used for predictions forIC yield as well as for performance andreliability.

Professor J.G. FossumUniversity of Florida

24

Quantum Effects inSubmicron Structures

As the down-scaling of devices con-tinues, quantum mechanical effects arebeginning to emerge. One consequence isthat devices maybe influenced by statisticaleffects such as the precise number ofdopant atoms that happen to reside withinthe device, e.g., the base region of a bipolartransistor. Device performance may evendepend on the exact placement of dopantatoms.

For example, one random configurationis shown above of dopants in an ultrasmall,0.2 x 2.0 µm resistor. The low-temperatureresistance, computed by a quantum devicemodel developed at Purdue, is about 5which is about 10% lower than the classicalvalue.

Position of Middle Impurity

Even more striking is the ± 20% variationin resistance (see illustration) that occursas a single dopant atom is moved. Asdevice dimensions continue to shrink, thesequantum effects will begin to limit deviceperformance, but they offer opportunities todevise a new class of devices that exploitthe wave nature of electrons.

Professors M.S. Lundstromand S. Datta

Purdue University

A Minimum Parasitic ELO Bipolar TransistorState-of-the-art bipolar junction transistor

(BJT) switching speed and unity gain fre-quency are limited by the transit times ofcarriers through the device and by theparasitic capacitances and resistancesassociated with the fabrication technology.The Epitaxial Lateral Overgrowth BJT(ELO/BJT) structure reduces parasiticcapacitances by dielectrically isolating thelow-resistance collector region from the

substrate and the base region. This obviatesthe need for a traditional buried layer, withifs attendant parasitic collector substratecapacitance, yet the device is fully self-isolated with no trenches or diffusionsrequired. Parasitic resistances are reducedby keeping currentpaths short, andplacingthe highly-doped extrinsic collector andextrinsic base regions in close proximity tothe active device regions. The oxide layercovering the lateral portions of the over-growth provides the dielectric isolation, andthe field oxide provides interdevice isolation.The stacked nature of the two overgrowthsallow collector, base, and emitter contactsto be spaced as closely as lithographyallows, facilitating a small geometry device.Working BJTs were obtained at Purdue withnear bulk-quality characteristic in doubleELO silicon. In addition, the double ELOtechnique is adaptable to a wide variety ofapplications in SOI, sensor construction,buried interconnects, BiCMOS, and dielec-tric isolation.

Professor G. W. NeudeckPurdue University

25

ResearchPackaging

Integrated circuits require packagesthat interface chips to the outside world.As chips become more complex andperformance demands increase, paral-lel developments are required in pack-aging technology. In recognition of thisneed, packaging is the second largestthrust in Manufacturing Sciences. Itincludes six university groups atAuburn, Stanford, Lehigh, Cornell,Purdue, and Arizona, with researchprograms ranging from materials char-acterization to the development of CADtools for package design.

Research at Stanford has focusedon using silicon substrates for highperformance interconnections. Auburnis developing a methodology for eval-uating package reliability. Lehigh andCornell are covering both materialsand performance aspects of denselypacked designs. The Arizona researchis bringing package design capabilitymore in line with techniques that havebeen developed for the integrated cir-cuit chip. At Purdue, emphasis is onbuilding an accurate database of impor-tant materials used in packaging.

(Photo courtesy of Kenneth A. Friedman — See photo on page 5.)

Professor Kyra Stephanoff With Test Apparatus

Cooling With Pulsatile FlowThe heat generated by colonies of inte-

grated circuit chips can adversely affect theperformance and lifespan of semiconductordevices. Methods currently being used todissipate such heat have disadvantagesand limitations. For example, use of a steadyflow of air across multilayer boards totransfer heat away from the circuitry bynatural convection will create local hoispots due to attached recirculatory flows atthe leading and trailing edges of the chipcarriers. At Lehigh, attempts are beingmade to improve cooling techniques forlow-cost, moderate performance applica-tions; and one method under investigationis a heat transfer process that uses pul-sating, rather than steady, air flow. Thisproject is based on the concept that thechanges in pressure which occur with peri-

odic air flow reversals can cause the eddiesof hot air that collect around chip carriers tobe ejected into the mainstream and, hence,swept away from the board. Such air flowreversals prevent stable thermallayers fromforming adjacent to the chip carrier surfacesand, consequently, increase the local heattransfer away from the chip. Toward thegoal of developing a viable technique forcooling with pulsatile flow, backgroundinformation was gathered during 1987 fromvisualization experiments, linear analysis ofphenomena, and long-wavelength analysis.A test apparatus was constructed and out-fitted with instruments to perform heattransfer experiments.

Professors Kyra D. Stephanoffand Phillip A. Blythe

Lehigh University

26

Active Substrate Interconnection InvestigationsThe Active Substrate approach to system

integration employs a silicon wafer as astand-alone, active, interconnect systemwhere chips are bonded directly to thewafer. For attainment of SRC goals that arepointed toward an interconnect conceptallowing 1,000 pin-outs around a 10 mm x10 mm chip, the Stanford research team ofPease, Hong, and Bravman have beenusing an Active Substrate configuration touncover the problems of high-density, multi-chip packaging. This team has originated aconcept whereby chips are held down bymicrocapillary attachment to the activesubstrate, which can be cooled by themicrochannel heat exchangers previouslydeveloped in this research project. Chip-to-substrate electrical connections arehandled by microscopic cantilever beamsdistributed around the chip edges; powerconnections might be made through themicrocapillary attachment. Some advan-tages of the Active Substrate approach are:system interconnects are transferred to amicroelectronic environment, chip tech-nology can be optimized for performanceand functionality, chip and substrate tech-nologies can be mixed to optimize systemperformance, and yield problems of fullwafer-scale integration are avoided.

Professors John C. Bravmanand R. Fabian W. Pease

Stanford University

Photomicrograph of micromachined cantilevers for chip-to-substrate contacts inan experimental high-density packaging structure. These cantilevers are fabri-cated by using orientation-dependent etching and controlled-stress metallizationand may be able to provide a reversible, compliant contact array that would allow1,000 pin-outs around a 10 mm x 10 mm chip.

27

Research

Design SynthesisSynthesis tools and systems for use

in the design process are fundamentalto reducing time-to-market and designcosts, promoting re-use of design dataand knowledge, and supporting efficientevaluation of design alternatives. SRC-sponsored research in design synthesisincludes system-level synthesis tools,logic-level synthesis, layout synthesis,array compilation, and synthesis fordigital signal processing applications.

COSMOSCOSMOS (COmpiled Simulator for MOS),

being developed by SRC-sponsored re-search at Carnegie-Mellon, is a unit delayswitch-level simulator that represents aMOS transistor circuit as a network ofdiscrete switches. COSMOS achieves highperformance by preprocessing a MOS tran-sistor network into a Boolean description.From this description, a set of procedures isgenerated to compute the behavior of eachchannel-connected subnetwork. COSMOScompiles these subnetwork procedures,together with kernel and user interfacecode, to generate an executable simulationprogram. The resulting simulator operatesan order of magnitude faster than its prede-cessor MOSSIM II, thus achieving perform-ance that rivals a logic-level simulator whilepreserving the generality and power of aswitch-level simulator.

During 1987, four major improvementswere made to COSMOS: (1) addition of faultsimulation that combines both concurrentand parallel simulation techniques;(2) imple-mentation of an inferface to allow user-written simulator drivers; (3) addition of asymbolic verification capability; and (4) addi-tion of a test pattern generator that is basedon symbolic fault simulation. Fifty copies ofthe simulator were distributed to universityand member company sites for evaluation.

Professor Randal E. BryantCarnegie-Mellon University

Digital System SynthesisThe System Architect’s Workbench

(SAW) is the result of an ongoing projectthat is developing a synthesis methodologyand a set of supporting CAD tools to bringautomation to the system levels of IC design.The methodology begins with a program-like behavioral description of the digitalsystem to be designed and produces adatapath that is specified in terms of regi-sters, arithmetic logic units and busing, anda control sequence. As shown in the figure,the workbench currently provides threemain steps for the synthesis process. First,the behavior is transformed by the user.This may involve, for instance, splitting thebehavior into several smaller concurrentstate machines in response to physicalarea constraints. Next, the control sequenceis automatically designed by scheduling the

behavioral operations into control states inresponse to timing and resource con-straints. finally, the datapath (including theregisters, arithmetic logic units and busingstructures) is automatically designed. TheCoral and SEE-SAW programs allow theuser to interrogate the automatically pro-duced design through graphical depictionof correspondences between differentviews of the design. SAW will be used todrive a second component (LASSIE) of theCMU design system that synthesizes alayout from a structural description of adatapath. The SAW software is currently inuse and under evaluation in the researchlabs of several SRC member companies.

Professor Donald E. ThomasCarnegie-Mellon University

System Architect’s Workbench

28

Berkeley Synthesis SystemThe Berkeley Synthesis System (BSS) is

an integrated design system centered on aframework composed of an object-orienteddata manager (OCT), a view editor thatprovides a unified view interface to tools(VEM), and a remote procedure call capa-bility for distributed computing environ-ments (RPC). As shown in the figure, syn-thesis starts with a specification in a hard-ware description language and continuesclockwise around the periphery. Individualtools successively refine the descriptionuntil mask images for a completely synthe-sized system are obtained. Refinement canbe performed interactively, allowing theuser to change design constraints and toolsequencing. Tools read and write the samedatabase, creating new OCT views of adesign or annotating old ones. The OCT/VEM/RPC framework allows tools to effici-ently access and exchange information.

During 1987, MOSAICO, the macrocellplacement and routing system was inte-grated info the OCT/VEM/RPC environ-ment, and a parallelimplementation for thesimulated annealing floorplanner, PUPPY,was developed. This implementation yieldsa speedup that is almost linear in thenumber of processors. Development of theORCA placement and routing system forsea-of-gates architectures continued, anddemonstration of a prototype system isanticipated in 1988. Research in verificationresulted in an accurate switch-level timingverifier for synchronous circuits (E-TV) thatutilizes a dynamic path evaluation tech-nique. Development of a new building blocklayout system, BEAR, is underway. BEARutilizes L-shaped routing channels to guar-antee routing completion, and includes 2-and 3-layer gridless channel routers anddirect consideration of timing constraints tooptimize performance. Additional synthesisresearch resulted in the development of adeterministic algorithm for synthesizingoptimum asynchronous circuits for digitalsignal processing.

Center of Excellence for IC CADUniversity of California at Berkeley

The Berkeley Synthesis System

29

Research

Single WaferProcessing

The strategic direction of integratedcircuit fabrication is toward continuousflow single wafer processing with mul-tiple process steps accomplished with-in the same process tool, i.e., in-situ. Toobtain the benefits of this manufac-turing method, each process tool willbe equipped with sensors and micro-processor control linked to the factorycomputer to effect real-time control ofthe process. In the latter stages offabrication, low thermal budget proc-esses will become increasingly neces-sary to retain the precise doping con-centrations and profiles, and to obtainthe performance and reliability of thinlayers of dielectric and metal filmsemployed, e.g., for gate oxide, barriermetallization and interconnect.

The benefit of this IC fabricationmethod is a reduction in the theoreticalmanufacturing cycle time, further reduc-tion of particulate defects, and activecontrol of production parameters. Inaddition, the manufacturing line isamenable to technology tuning toaccommodate multiple process flowsfor a limited variety of products. Thesebenefits translate to lower manufac-turing cost, dramatically higher through-put, i.e., reduction in actual manufac-turing cycle time, and the ability tofabricate a variety of product within thesame manufacturing space.

Multiple ProcessTechnology

Side view of RTE CVD reactor, showing’lamp arrays.

Loading door and canti lever waferholder.

In-Situ Processing, i.e., the accomplish-ment of multiple process steps within thesame process tool without movement of thewafer, is under investigation at NC Statewhere a rapid thermal processing reactor isbeing employed for clean, epitaxial siliconor germanium growth, oxidation and nitri-dation in the same chamber without removalof the wafer between process steps. TheRTP reactor is microprocessor controlled,and is currently being instrumented withsensors and actuators for real-time controlof the programmed process. Both inner andouter chambers have been designed tooperate at vacuum levels for low pressureCVD and clean. Heating is by fifteen one-half kilowatt lamps placed above and belowthe wafer; the system is designed to handlesix-inch wafers,

Professor J.J. WortmanNorth Carolina State University

Laser ProcessingAs ICs grow in functional complexity and

die size, it becomes more important todevelop processing techniques that affectonly a limited region of the die and/or wafer;i.e., limited area processing (LAP). LAP isimportant for operations requiring extremedegrees of processing, such as through-wafer vias, or alteration of a nearly finishedproduct where a low thermal budget isrequired (such as custom isolation, cuttingsilicon lines, and custom metallization).Laser direct writing — a rapid, maskless,gas-phase process with micron scale pat-terning capability — is being investigated atColumbia as a suitable tool for LAP. Onesuccessful process is the direct depositionof custom aluminum interconnect from thepyrolytic surface reaction, employing di-methyl aluminum hydride. A second proc-ess under investigation is custom trenchisolation for active devices. This has beenexamined by etching trenches in a diffusedp-n junction to from an isolated region.

The I-V characteristic of a typical trench-isolated diode indicates good isolation.Electrical characterization of MOS capaci-tors and Schottky barrier diodes fabricatedon top of laser-etched silicon shows thatlittle damage occurs when the power ismoderate, indicating that laser-etchedmaterial is usable for IC fabrication.

Professor R.M. OsgoodColumbia University in the

City of New York

30

In-Situ GrowthParameters

Mobility of antimony versus concentra-tion, and the use of pulse doping toillustrate dopant stability.

Fabrication of submicron microelectronicdevices requires precise control of dopantconcentration and depth distributions, em-ploying low thermal budget processing.However, most of the common dopantsused in IC fabrication present serious prob-lems during film growth due to low incor-poration probability and/or pronouncedsurface segregation, giving rise to uncon-trolled profile broadening. The Thin FilmPhysics Group at lllinois has been investi-gating the use of low-energy (50-500 eV)accelerated-ion doping during MBE silicongrowth to overcome these effects. Theexperiments are carried out using a newultrahigh-vacuum-compatible, low-energyion source developed as a part of theresearch. Accelerated-ion antimony maybe made to incorporate with unity probabilityinto substitutional, electrically active, sitesat concentrations up to 3 x The filmsare essentially dislocation free with noindication of residual ion-induced damage.

Professor J.E. GreeneUniversity of lllinois

Five station Integrated Processing Facility for development of single waferintegrated processing technologies at Research Triangle Institute.

Low Temperature Silicon Oxynitride TechnologySingle wafer low temperature processing

with multiple process steps performed inthe same tool will be the hallmark of futureintegrated circuit fabrication. The next gener-ation ICs will require the use of smallerfeatures and thin films with improved reli-ability. Research conducted jointly at RTIand NC State is directed toward develop-ment of high-reliability, low-temperaturesilicon oxynitride films in a tool that ulti-mately is capable of performing additionalprocess steps. By the use of remote plasma-enhanced CVD, high quality gate dielectricshave been formed on silicon at tempera-tures as low as 300°C. The process can beused lo clean and deposit films (oxide,

nitride, and controlled-composition stoichio-metric oxynitride) in a clean ultrahighvacuum compatible environment, and thentransport the wafer in vacuum to an analysisstation. The deposition station accommo-dates in-situ, plasma-enhanced surfacecleaning together with in-situ surface char-acterization via reflecting high-energy elec-tron diffraction (RHEED). These featureswill ultimately make direct, immediate feed-backpossible for real-time process control.

Dr. James A HutchbyResearch Triangle Institute

Professor Gerald LucovskyNorth Carolina State University

31

Reliability andYield Enhancement

The Clemson contract was one ofthe first Manufacturing Sciences pro-grams responding to the high priorityplaced on IC reliability research. It hasfocused on three reliability issues:aluminum electromigration, charge injec-tion into dielectrics, and electrostaticdischarge. Most recently the emphasishas extended to reliability models foruse in the design process to predictdevice reliability before wafer fabrica-tion. Work has been started on devel-oping such a model for the electro-migration mechanism at Clemson andat Cornell.

Yield enhancement research atResearch Triangle institute and theMicroelectronics Center of North Caro-lina has been largely concerned withthe study of particulate contamination,both in the clean room environmentand as a more fundamental study of thebehavior of submicron particles inliquids and gases.

Yield Enhancement research at theUniversity of Illinois has concentratedon optimization of reconfiguration de-sign methods.

Research

Simulated ElectromigrationDiffusion along grain boundaries is an

important mass transport process in manyintegrated circuit phenomena. In particular,the migration of impurity and metal atoms inmetallization levels is a precursor to electro-migration failure. This is a common failuremechanism for interconnects that arestressed at high current densities forextended periods of time. A simulation,using the techniques of molecular dynamicsto study the diffusive properties of grainboundaries at an atomic level, is being usedat Cornell to investigate parameters thataffect the diffusion rates and activationenergies in different kinds of grain bound-aries. A metal grain boundary is simulatedon the computer (CNSF IBM 3090-600E) byplacing several hundred atoms on the latticesites of a chosen geometry and then re-laxing them to minimum energy positions.This gives the static structure of the bound-ary (see accompanying figure). Randomvelocities are then assigned to the atoms,and the trajectory of each atom can befollowed in time as it is repulsed andattracted by its neighbors. At temperaturesgreater than one-half Tmelt, atoms in thegrain boundary region become quite mobile,forming Frenkel pairs as vacancies arecreated and hopping from lattice site to sitewithin the boundary. By calculating the

distances that different atoms migrate atdifferent temperatures, a diffusion coeffici-ent and activation energy for the systemcan be determined.

Professor Edward D. WolfCornell University

A high angle tilt boundary in a body-centered cubic (bcc) lattice. Eachsphere represents an atom sitting on itslattice site. The kite-like structures inthe middle mark the boundary regionwhere the two crystals come together.The atoms in the central portion arefree to move in the dynamic part of thesimulation; the walls of atoms on theleft and right are held fixed and serveto contain the motion.

Reliability AnalysisA CAD tool called RELlANT has been

developed to analyze a layout for suscepti-bility to electromigration failure and to pre-dict the interconnect failure rate. Takinginput from a manufacturer’s CAD system,life test data unique to the process (obtainedfrom test vehicles or drop-ins) are combinedwith layout data unique to the design toprovide reliability assessment with lessneed for conventional stress testing. Theapplicability of simulated reliability testingwas demonstrated by using RELIANT on anactual design in production at an SRC

Model data extracted fromdesign data base

Features of RELIANT Analysis

Measured data used in analysis

Is an open architecture CADpackage

member company. RELIANT is the first ofseveral planned reliability simulation

Circuit analyzed under real

packages that will include the effect ofoperating conditions

defects, which result in infant mortality

failures, and wearout mechanisms such aselectromigration.

Professor K.F. PooleClemson University

CMOS Inverter Failure Rate vs. Time

32

Analysis of SpareAllocation andReconfiguration toIncrease Yield

If VLSI chip sizes are to increase sub-stantially, approaches to design and manu-facturing are needed that tolerate or avoiddefects, and, thereby, provide for yieldsgreater than those which are now possiblewith very large chips and wafer-scale inte-gration. One approach to a solution of thisproblem is through design for yield enhance-ment by means of restructurable inter-connect, logic, and architectural compon-ents. A project at Illinois has focused on thedevelopment of a computer-aided analysistool for evaluation of alternative reconfigur-able architecturaldesigns. Graph-theoreticmodels of hierarchical reconfigurationschemes have been developed and ana-lyzed. Based on these models, algorithmsfor reconfiguration have been developedand implemented. One example applicationof these algorithms, as illustrated below,

Bipartite description

has been the development of highly efficientheuristics for reconfiguration of largememory arrays in the presence of multiplememory cell defects, using spare rows andcolumns of cells. Work is currently under-way to incorporate the reconfigurabilityanalysis into an architectural-level per-formance, yield, and reliability evaluationenvironment.

Professor W. Kent FuchsUniversity of Illinois

Particle Removal fromSilicon Wafers

Quantitative evaluation of the effective-ness of various cleaning solvents for re-moving particulate contaminants from Siwafers has revealed that polar liquids aremuch more effective than the Freons. Ultra-sonic and hydrodynamic (shear stress)cleaning systems were developedat RTI formeasuring cleaning efficiency and force ofadhesion of micron- and submicron-sizedparticles on Si wafers. Results show that inaddition to van der Waal’s and electrostaticforces between particles and a wafer,hydrophobic/hydrophilic interactions alsoplay a major role in the cleaning process.For example, the passage of a wafer con-taminated with 1 µm polystyrene latexmicrospheres through the air-water inter-face resulted in particle agglomeration onthe wafer surface. The following photo-micrographs show a silicon wafer beforeand after immersion in a Di-water bath.

Single particles were found to migrate alongthe wafer surface to form islands with largeclusters of particles. Significant differencesin the cleaning efficiency and the mecha-nism ofparticle detachment were observedwhen inorganic particles were com-pared with organic (polystyrene latex)particles of the same size. Both ultrasonicand hydrodynamic cleaning techniqueswere found to be capable of achieving highcleaning efficiencies for µm-size particlesfrom Si wafers.

Studies at Microelectronics Center of NC andResearch Triangle Institute

Aerosol ParticleDeposition onHeated Wafers

Objects warmer than the ambient air aresurrounded by a particle-free space be-cause of thermophoresis and thermal con-vection. This interaction can be used toprotect wafers from particulate contamina-tion in both storage and processing. Thefollowing graph plots the reduction in parti-cle deposition velocity (particle surface fluxand ambient particle concentration) broughtabout by heating wafers exposed to poly-styrene latex spheres suspended in a parti-cle deposition chamber built as part ofSRC-sponsored research at the Microelec-

Wafer Temperature (°C)

tronics Center of North Carolina. Simplyraising the wafer temperature by 30°Creduces the particle deposition velocity byan order of magnitude. This thermalshielding effect can be useful in planningprocess procedures. For example, wafersloaded into a vacuum chamber, then fast-pumped and fast-vented, collect an order ofmagnitude more surface particles thanthose that are heated to 30°C above ambi-ent for this same procedure in the sameapparatus. This particle shielding propertyis most effective for aerosol particles in the0.1 to 1.0 µm size range.

Dr. Robert DonovanResearch Triangle Institute

33

Analog ICsThe complex task of designing

analog and mixed analog/digital inte-grated circuits has been, in general,inadequately supported by computer-aided design tools and systems. SRCresearch is addressing factors thatameliorate the continuing complexityof the task as the demand for higherperformance and more accurate cir-cuits for digital signal processing appli-cations and high precision analogincreases.

At Stanford, research directed byProfessor Bruce Wooley focuses onthe design of oversampled A/D con-verters. An efficient simulator forsampled-data systems has been devel-oped that is capable of analyzing boththe spectral nature of quantization noiseand the influence of practical circuitimpairments on system performance.Application of the simulator has re-sulted in the successful design andimplementation of a second-order,sigma-delta modulator in a 3 µm CMOStechnology. Modulator performance issummarized in the following table.

TechnologyOversampling RatioSampling RateDynamic RangePeak SNRSupply VoltagePower DissipationArea

3 µm CMOS2564 MHz89 dB79 dB5 V12mW0.77

Research in continuous-time analogdesign for MOS VLSI led by ProfessorMohammed Ismail at Nebraska hasresulted in the fabrication and evalua-tion of several circuits that demonstratesuperior performance to digital switchcapacitor circuits for high frequencyapplications. Future research will focuson exclusively MOS-domain designmethods for continuous-time analogcircuits and development of on-chiptuning systems.

Research

At MIT, a pipelined, self-calibrating A/D converter has been imple-mented in CMOS technology as shown in the die photograph above.Both loop gain and loop offset errors are calibrated by an on-chipcapacitor array and D/A converters. With the incorporation of thisself-calibration, it is possible to operate the converter so that only twosettling times of the operational amplifiers are required for each bitdecision. Projected performance of a 2-stage pipeline is 16 bitresolution at a sampling rate of 200 kHz. Plans include use of thisarchitecture as a test vehicle for a new high performance BiCMOStechnology.

Professor Hae-Seung LeeMassachusetts Institute of Technology

34

Analog Circuit SynthesisSystem-level applications increasingly

incorporate analog subsystems; hence,CAD tools that support synthesis of mixedanalog/digital circuits are critically needed.A major effort is underway at CMU toautomate the syntheses of full-customanalog cells. Work to date has focused onthe development of a knowledge-basedframework for behavior-to-structure syn-thesis with the goal of generating sized,topologically correct circuit schematicsfrom a set of process and performanceconstraints. This synthesis model has beenimplemented in the prototype system,OASYS, which currently supports the syn-thesis of CMOS operational amplifiers.Fabricated test chips confirm that OASYScan design real circuits. A set of untunedtest circuits, laid out directly from OASYS-synthesized schematics, meets specifica-tions closely (see accompanying table anddie photograph). Because synthesis inOASYS is fast, extensive exploration oftradeoffs is feasible. The example designsurface, generated in about three minuteson a workstation, illustrates tradeoffs amongseveral parameters and shows where neces-sary circuit design changes were madeautomatically. The design knowledge in

OASYS iS being broadened to support thesynthesis of more complex and nonlinearanalog cells to develop styles and algo-rithms that will generate layouts fromschematics, and to develop a knowledgeacquisition tool that will permit circuitdesigners to directly extend and modifyembedded synthesis knowledge.

Professors R.A. Rutenbar andL.R Carley

Carnegie-Mellon University

35

Advanced ProcessTechnology

The next generation IC manufac-turing technology will require the use ofadvanced processes specificallydesigned for low thermal budgetprocessing with finer geometries andsharper gradients to the dopant distri-butions. To retain long channel per-formance for submicron MOSFETs, arecessed gate device design can beemployed. To effect a CMOS circuitdesign with optimum signal to noise,both p- and n- polysilicon will beemployed to obtain surface channeldevices. Source/drain cladding will beused to reduce surface resistance, andbarrier metals will be employed. Theunderstanding of thin film stability andmetallurgy with films under high stresswill be important. A high density multi-level interconnect technology with lowdielectric constant insulation must bedeveloped to support the minimalswitching delay achieved with recessedgate submicron channel length FETs.Finally, this must be accomplished witha reliable, low-cost manufacturingapproach. SRC research is addressingsome of the key issues that must beresolved to achieve the next generation.

Research

Low Cost Silicon EpitaxyThe use of epitaxial silicon layers in ULSl

is increasingly attractive, but applicationsare limited at present by high cost andcomplexity. Research at UC/Berkeley IS

exploring the use of a high-capacity, hot-wall, chemical-vapor-deposition systembecause of the potentially low manufac-turing cost for selective silicon epitaxy. Aprototype hot-wall system in which thewafers are loaded perpendicular to the gasflow in a “coin-stack” fashion has beenconstructed by modifying a tube in a com-mercial LPCVD furnace system. The 9-inch-long flat-zone in the current configura-

tion can potentially accommodate up to 50wafers with a 100 mm diameter. An epitaxialsilicon growth rate of 10 nm/min is achievedwith a uniformity across each wafer of ±2%.Spreading resistance profiles show that fora 1.1 µm thick layer grown undoped on an

substrate that a “two-order transition-width” of about 0.2 µm with a backgroundconcentration of 5 x is produced.The deposition is perfectly selective, andthe growth rate is uniform independent ofpattern geometry.Professor William G. OldhamUniversity of California at Berkeley

Vias of 2 µm deep and 1 µm widecovered with 2.5 µm PIB Al film.

36

PIB Metal DepositionAn advanced metal deposition process

has been developed at RPI which achievescomplete wall-to-wall filling of trenches andvias without developing voids due to over-hanging deposition at the uppermost edgeof the via. Partial planarization of the metal-lization is possible in the as-deposited film.Additional processing, e.g., with excimerlaser pulsing or continued partially ionizedmetal beam (PlB) at 300°C substrate tem-perature, can result in complete planari-zation of the metal layer. The depositionprocess employs a PIB with 1-5% self-ionsand a bias potential of 1-5 kV applied to thesubstrate during deposit/on.

Professor Toh-Ming LuRensselaer Polytechnic lnstitute

Novel TungstenInterconnect Technology

A manufacturable, high-performanceinterconnect technology is key to ULSlintegrated circuits. Three of the majoraspects required of such a technology are:(1) multilevel — as many as four to tenlevels for “system”ICs, (2) vertical level-to-level interconnect without requiring nestedvias, and (3) planarization at each level,metal and dielectric. An inherently planartechnology has been developed at Cornellthat effectively addresses these threeissues. Each level of interconnect IS formedby selective deposition of tungsten intooxide channels produced by a highly direc-tional dry etch process. Prior to the tungstendeposition, a high dose silicon implant isemployed to modify the oxide surface prop-erties of the floor of the channel so that thedeposition of tungsten is initiated only withinthe channels. A similar process is employedfor the filling of vias between metal inter-connect planes.

Professor S. Simon WongCornell University

Photomicrograph of a cross section oftwo levels of planar tungsten inter-connect with a contact plug.

QUADRUPOLE MASSSPECTROMETER

Advanced Plasma EtchingA single wafer etcher has been devel-

oped at MIT which performs fundamentalplasma measurements during directionalplasma etching processes. It is anticipatedthat these measurements, now being usedto test and develop kinetic process andequipment models which simulate the glowdischarge and chemical kinetics, can belater employed for real-time control of theprocess. Specific chemical kinetics ofchlorofluorocarbon discharges have beenmodeled and used to successfully predictthe etching rate and directionality. Wafertemperature is monitored during etching bya fluoroptic probe and controlled by heliumpressurization between the wafer and theelectrode. Etch rate is monitored using

laser interferometry through an optical fiber;the electrical impedance of the discharge isdetermined by measuring the current andvoltage waveforms to the powered elec-trode. Spatially and temporally resolvedconcentration measurements of plasmaspecies are made using both plasma-induced emission and laser-induced fluor-escence. During etching, the ion bombard-ment flux, energy distribution, impingementangle distribution, and composition can bedetermined by the retarding grid and massspectrometric analysis of the ion flux whichpasses through a pinhole in the wafer/electrode surface.Professor Herbert H. SawinMassachusetts Institute of Technology

37

Design for TestSignificant cost and quality benefits

are derived from efficient, high-coverage test of lCs, provided that areapenalties are not excessive. The 1994SRC research goal of a reject ratio dueto electrical failure of 1 in 106 hasmandated that a significant emphasisbe placed on testability in the SRCresearch program. Progress was madein 1987 in automatic test pattern gen-eration, fault simulation, and design fortestability.

The hierarchical fault simulator,CHIEFS, developed at the University ofIllinois, has been extended to handlebidirectional transistors; and a newprogram, FOX, has been added to gen-erate a high-level fault description of amodule from a low-level (transistor)description. CHIEFS is being tested byapplication to a large commercial micro-processor. A hierarchical test patterngenerator, HITEC, which can handlemultiple output blocks and is applicableto sequential circuits, is also underdevelopment. HITEC uses the highlevel circuit structures without flatteningthem into gate-level primitives. Thehigh level structures can be describedin one of three ways: (1) interconnectionof lower level structures; (2) Booleandescription, e.g., a Boolean equation ortruth table; or (3) Functional behavior,e.g., a C program. The Boolean andbehavioral descriptions allow the testgeneration to proceed even before thelower level design of a circuit is com-plete. This feature should help toidentify testability problems early in thedesign cycle. An early version of HITECis operational and has been tried onseveral circuits. The observed perform-ance in these cases has been superiorto that of conventional test generationmethods which are based on gate-level descriptions.

Research

Research is also underway atCarnegie-Mellon University to developswitch-level dual-mode automatic testpattern generation techniques for inte-grated circuits. In dual mode testing,faulty circuit behavior is detected para-metrically by abnormal power supplycurrent levels; and behavioral testingdetects abnormal logical values at thecircuit outputs. At the board level ofdesign, the expert system single-boardcomputer design system, MICON, hasbeen augmented to produce test infor-mation for the designs that it automati-cally produces. The goal of a researchproject at the University of California atBerkeley is to improve test generationtechniques for sequential digital circuitswhile reducing the requirement for addi-tional scan logic. The basic idea is togenerate tests for a large number offaults for a given circuit, then to deter-mine a minimal subset of memory ele-ments that, if made observable andcontrollable, will provide easy detectionof most remaining non-redundant anddifficult-to-detect faults.

First CAST Stage

The Computer-AidedSelf-Test System

A three-year research effort at the Uni-versity of Rochester has produced theCAST (Computer-Aided Self-Test) System:a tool for designing self-testable VLSl chips.CAST is applicable to chip designs that maybe represented by data flow diagrams whichconsist of registers driven by a single two-phase non-overlapping clock, and combi-national logic blocks. CAST incorporates atwo-stage strategy for transforming appli-cable designs into self-testable designs.During the first stage, one of two availableprocesses can be used to place BIT (Built-In Test) structures within the chip design.The Built-in Exhaustive Self-Test processuses the Built-in Logic Block Observertechnique to provide the design with afunctionally exhaustive self-test capability.A lower BIT hardware overhead can beobtained at the expense of test effective-

38

Second CAST Stage

ness, using the Minimum Overhead Self-Test process that (given an upper limit onthe test running time) provides the designwith a pseudo-random functional self-testcapability. During the second CAST stage,the scan path is designed, the testingprocedure is specified, and the minimumrequired control for the BIT hardware isdetermined. CAST has been developedusing the C programming language andruns on the SUN 3 family of workstationsunder the SUN UNIX 3.4 operating system.Al/ stages of the design process are dis-played using X-windows. A standard Com-puter Hardware Description Language inter-face is currently under development.

Professor Alexander AlbickiUniversity of Rochester

Microelectronics ManufacturingEngineering Education

In 1986, the SRC initiated a programfor development of interdisciplinary cur-ricula at leading universities so thatquality undergraduates and candidatesfor the Master’s degree could gain thewide range of skills needed by today’ssemiconductor manufacturing engi-neers. During 1987, the SRC supporteda second year of the pilot project atFlorida A&M University/ The FloridaState University (FAMU/FSU) in Talla-hassee, and preparations were com-pleted for expansion of this program tofour additional schools by the beginningof 1988.

Faculty from FAMU/FSU aided inprogram expansion by preparing aRequest for Proposals for the develop-ment of Microelectronics Manufac-turing Engineering Curricula that wassent to twenty of the leading engi-neering institutions across the UnitedStates. Proposals were received fromthirteen universities; and the Universityof Minnesota, Rensselaer PolytechnicInstitute, the Rochester Institute ofTechnology, and the University ofTexas at Austin were selected toreceive the four new grants.

Multidepartmental teams are beingused at each of the five schools todefine and develop curricula relative tothe needs of the U.S. semiconductorindustry. The pilot project’s team con-sulted with industrial and academicpersonnel, and designed a curriculumquestionnaire for distribution to SRCmember companies at a workshop andthrough the mail. The results of thisstudy indicated that the courses con-sidered most essential are Statistics,

Semiconductor Physics, Semicon-ductor Processing, Microelectronics,Materials Science, Packaging, andComputer-Integrated Manufacturing.Courses in Solid State ElectronicsDevices (Solid State Physics), Micro-electronics, and SemiconductorProcessing have all been developedand incorporated into the FAMU/FSUcurriculum. Additional courses thathave been developed and will beadded to the curriculum in the comingyear are Semiconductor Materials,Fundamentals of MicroelectronicPackaging, and Computer-IntegratedManufacturing.

To encourage and facilitate inter-action among the participating univer-sities, faculty from each of the fiveprograms have been invited to attend aworkshop scheduled for June, 1988, atResearch Triangle Park, NC. Each teamwill be encouraged to share plans andexperiences toward stimulating thesupply of suitably trained engineers tomanage the semiconductor factoriesof the future.

39

The TAB and UACThe Technical Advisory Board (TAB) of the SRC

provides essential guidance on goals, priorities, rele-vance, and strategies for the research program, andcoordinates the transfer of research technology topotential users of the results. It consists of technicalrepresentatives of members and participants and isorganized to correspond to the SRC’s programstructure.

The University Advisory Committee (UAC) providesinsights from the university research community thatassist the SRC in management and directing itsactivities. The committee consists of representativeswith backgrounds in semiconductor research fromresearch universities.

University Advisory Committee (UAC)Professor Jacob A. Abraham

University of Illinois at Urbana/ChampaignDr. Ralph K. Cavin Ill

Semiconductor Research CorporationProfessor Stephen W. Director, Chairman

Carnegie-Mellon UniversityProfessor Paul Gray

University of California at BerkeleyProfessor David V. Kerns, Jr.

Vanderbilt UniversityProfessor Jay W. Lathrop

Clemson University

Professor W. W. LindemannUniversity of Minnesota

Professor Noel C. MacDonaldCornell University

Professor Nino A. MasnariNorth Carolina State University

Professor James L. MerzUniversity of California at Santa Barbara

Dr. Carlton OsburnMicroelectronics Center of North Carolina

Professor R. Fabian PeaseStanford University

Professor L. Rafael ReifMasschusetts Institute of Technology

Professor Andrew J. StecklRensselaer Polytechnic Institute

Professor Al TaschUniversity of Texas of Austin

Professor Kensall D. WiseUniversity of Michigan

Technical Advisory Board (TAB)Executive CommitteeAT&T Bell Laboratories

Richard M GoldsteinAdvanced Micro Devices, Incorporated

J. Philip DowningControl Data Corporation

James R. KeyDigital Equipment Corporation

Llanda M. RichardsonE. I. du Pont de Nemours & Company

Grant A. BeskeEaton Corporation

Stanley V. Jaskolski, TAB Co-ChairmanGeneral Electric Company

Marvin Garfinkel

General Motors/Delco ElectronicsEdward G. Whitaker

Harris CorporationTom L. Haycock

Hewlett-Packard CompanyPhilip J. Fleming

Honeywell IncorporatedJames M. Daughton

IBM CorporationBilly Lee Crowder

Intel CorporationJohn R. Carruthers

Motorola, IncorporatedEdward L. Hall

National Security AgencyK. Speierman

National Semiconductor CorporationCourt Skinner

Rockwell International CorporationJohn D. Bastian

Semiconductor Research CorporationJames F. Freedman, TAB Co-Chairman

Texas Instruments IncorporatedPallab ChatterjeeRobert A. Stehlin

Richard D LaScala, Secretary (SRC)

Ex Officio MembersGTE Laboratories, Incorporated Loral Systems Group

Dr. Harry F. Lockwood Melvin H. DavisGeneral Motors/Hughes Aircraft The Perkin-Elmer Corporation

Sheldon J. Welles Donald R. Herriott

Technology Transfer CommitteeAdvanced Micro Devices, Incorporated General Electric Company

Oolep lndreko Mario GhezzoControl Data Corporation Harris Corporation

James R. Key Tom L. Haycock, Chairman

Digital Equipment Corporation Hewlett-Packard CompanyDebra M. Rogers Phillip J. Fleming

Eaton Corporation IBM CorporationDaniel G. Smedley Michael R. Poponiak

The SEMI Group, IncorporatedLarry A. Kolito

Intel CorporationSuzanne Johnson

Motorola, IncorporatedJames N. Smith

National Semiconductor CorporationCourt Skinner

Rockwell lnternational CorporationJohn D. Bastian

42

Technical Advisory Board (TAB) (Continued)Design Sciences CommitteeAT&T Bell Laboratories

Richard M. GoldsteinAdvanced Micro Devices/Monolithic Memories

Jerry D. MoenchWilliam E. Moss

Control Data CorporationWally B. Edwards, Jr

Digital Equipment CorporationLlanda M. Richardson

E-Systems, IncorporatedCharles T. Brodnax

Eastman Kodak CompanyTeh-Hsuang Lee

GTE Laboratories, IncorporatedRob Moolenbeek

General Electric CompanyManuel A. d’Abreu

General Motors CorporationPaul J. Ainslie, Vice Chairman

General Motors/Hughes AircraftJoseph A. Muslin

Harris CorporationJames P. Spoto

Hewlett-Packard CompanyJames Duley

Honeywell IncorporatedRobert Payne

IBM CorporationAllan A. Anderson

lntel CorporationHenry Blume

Loral Systems GroupRobert Parker

Motorola, IncorporatedKen Ray

National Science FoundationBernie Chern

Manufacturing Sciences CommitteeAT&T Bell Laboratories General Motors/Hughes Aircraft

David J. Lando William “Ed” ArmstrongAdvanced Micro Devices/Monolithic Memories Harris Corporation

Colin W.T. Knight Joseph W. BoarmanJ. Thomas Wait Hewlett-Packard Company

Applied Materials, Incorporated Steve Jewell-LarsenJohn G. Stewart Honeywell Incorporated

Control Data Corporation Lawrence WelliverJames R. Key IBM Corporation

E. I. du Pont de Nemours & Company Donald F. Reilly, Chairman*Grant A. Beske Intel Corporation

Eastman Kodak Company Richard C. DehmelRajinder P. Khosla Motorola, Incorporated

Eaton Corporation Jack L. Saltich, Vice ChairmanDaniel G. Smedley National Science Foundation

GTE Laboratories, incorporated Michael WoznyKothandaraman Ravindhran National Security Agency

General Electric Company Donald F. CookConnie A. Neugebauer National Semiconductor Corporation

General Motors/De/co Electronics Chris LadasRonald K. Reger

National Security AgencyDennis Heinbuch

National Semiconductor CorporationJim Gordon

Rockwell International CorporationJohn D. Bastian

SEMI/SILVACO Data SystemsIvan Pesic

Silicon Systems, IncorporatedGary Kelson

Texas instruments incorporatedPallab Chatterjee, Chairman

Westinghouse Electric CorporationVincent Zagardo

Xerox CorporationDavid Franco

Rockwell International CorporationChris Chi

SEMI/Solid State Equipment CorporationRobert D. Richardson

Silicon Systems, IncorporatedWilliam L. Healey

Texas Instruments IncorporatedP.B Ghate

Union Carbide CorporationThomas A. Nelson

Varian Associates, incorporatedWillam E. Starks

Westinghouse Electric CorporationMichael E. Michael

Xerox CorporationMichael J. Lo

*Moiz M. Beguwala of Rockwell international Corporation served as Chairman throughout 1987 and until February, 1988

Microstructure Sciences CommitteeA T&T Bell Laboratories Harris Corporation

H.J. Levinstein A.L Rivoli, Vice ChairmanAdvanced Micro Devices, Incorporated Hewlett-Packard Company

Ron Das Gene ZellerControl Data Corporation

C.T. NaberE. I. du Pont de Nemours & Company

Jean Claude ChevrierEastman Kodak Company

David L. LoseeGTE Laboratories, Incorporated

D. Dean CaseyGeneral Electric Company

Marvin Garfinkel ChairmanGeneral Motors/De/co Electronics

David E. MossGeneral Motors/Hughes Aircraft

Richard C. Henderson

Honeywell IncorporatedJack Huang

IBM CorporationE.J. Rymaszewski

Intel CorporationMichael Garner

Monsanto CompanyHarold W. Korb

Motorola, IncorporatedClarence J. Tracy

National Science foundationDonald J. Silversmith

National Security AgencyNancy Welker

National Semiconductor CorporationCourt Skinner

The Perkin-Elmer CorporationHarry Sewell

Rockwell International CorporationBrooke Jones

SEMI/AG AssociatesJaim Nulman

SEMI/Micrion CorporationJohn Doherty

Texas Instruments IncorporatedRobert A. Stehlin

Union Carbide CorporationDennis F. Brestovansky

Xerox CorporationJames Vesely

Information current as of April 15, 1988

43

Research

Board of Directors

AT&TKlaus D. Bowers, ChairmanBruce R. Darnall*Advanced Micro Devices, Incorporated, and

Monolithic Memories, IncorporatedMichael J. CallahanAnthony B. Holbrook*Digital Equipment CorporationRobert B. PalmerWilliam C. Robinette, Jr. *General Electric CompanyKenneth A. PickarJohn Herman III*

General Motors CorporationRobert J. McMillin, Vice ChairmanNils L. Muench*

Harris CorporationJon E. CornellThomas J. Sanders*

Hewlett-Packard CompanyFred SchwettmannJack Anderson*

Honeywell IncorporatedBrian HegartylBM CorporationSanford L. KaneWilliam T. Siegle*Intel CorporationGerhard ParkerRobert N. Noyce*

Motorola, IncorporatedBob J. JenkinsW. J. Kitchen*

National Semiconductor CorporationE. Randy ParkerJames B. Owens Jr.*Rockwell International CorporationFrank MichellettiGilbert F. Amelio*

Semiconductor Research CorporationLarry W. SumneyTexas instruments IncorporatedG.R. Mohan RaoGregory J. Armstrong*The Perkin-Elmer CorporationGaynor N. KelleyDavid A. Huchital*

Ralph E. Darby, Jr., Corporate Secretary (SRC)Jonathan Greenfield, Legal Counsel (Ware & Freidenrich)

*Alternate Member

SRC Officers and Senior Staff

Larry W. SumneyPresidentRobert M. BurgerStaff Vice President and Chief Scientist

Ralph K. Cavin IllDirector, Design SciencesRalph E. Darby, Jr.Director, AdministrationJames F. FreedmanDirector, Research IntegrationWilliam C. HoltonDirector, Microstructure SciencesRichard A. LucicDirector, Technology TransferD. Howard PhillipsDirector, Manufacturing Sciences

Michael D. ConnellyManager, Information SystemsNorman F. Foster(Resident from AT&T)Program Manager, Manufacturing SciencesLinda L. GardnerManager, Intellectual PropertyJeffrey L. Hilbert(Resident from Motorola)Program Manager, Design Sciences

C. Edward Holland, Jr.(Resident from DoD)Manager, Governmental Affairs

Richard D. LaScalaManager, Contracts and GrantsPhillip A. Lutz(Resident from GM/Delco)Program Manager, Manufacturing SciencesKenneth L. Pocek(Resident from Intel)Program Manager, Design SciencesH. Bryant StonehamManager, Finance

lnformation current as of April 15, 1988

4 4

The “APN” is a silicon connection processing node that communicates values in the digital domain and does a nonlinearsum-of-products in the analog domain. On the chip shown above are four nodes, each having four 4-bit “synapses.” The chipwas fabricated in 3 micron CMOS. (see research highlight by Professor Hammerstrom. Oregon Graduate Center. on page 23).

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SRC Publication No. S88008