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Computer Architecture

Lecture 4: More ISA Tradeoffs

Prof. Onur Mutlu

Carnegie Mellon University

Spring 2012, 1/23/2012

Homework 0

Due now

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Reminder: Homeworks for Next Two Weeks

Homework 1

Due Monday Jan 28, midnight

Turn in via AFS (hand-in directories) or box outside CIC 4th floor

MIPS warmup, ISA concepts, basic performance evaluation

Homework 2

Will be assigned next week. Stay tuned…

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Reminder: Lab Assignment 1

Due next Friday (Feb 1), at the end of Friday lab

A functional C-level simulator for a subset of the MIPS ISA

Study the MIPS ISA Tutorial

TAs will cover this in Lab Sessions this week

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Review of Last Lecture

ISA Principles and Tradeoffs

Elements of the ISA

Sequencing model, instruction processing style

Instructions, data types, memory organization, registers, addressing modes, orthogonality, I/O device interfacing …

What is the benefit of autoincrement addressing mode?

What is the downside of having an autoincrement addressing mode?

Is the LC-3b ISA orthogonal?

Can all addressing modes be used with all instructions?

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Is the LC-3b ISA Orthogonal?

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LC-3b: Addressing Modes of ADD

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LC-3b: Addressing Modes of of JSR(R)

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Another Question

Does the LC-3b ISA contain complex instructions?

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Complex vs. Simple Instructions

Complex instruction: An instruction does a lot of work, e.g. many operations

Insert in a doubly linked list

Compute FFT

String copy

Simple instruction: An instruction does small amount of work, it is a primitive using which complex operations can be built

Add

XOR

Multiply

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Complex vs. Simple Instructions

Advantages of Complex instructions

+ Denser encoding smaller code size better memory

utilization, saves off-chip bandwidth, better cache hit rate (better packing of instructions)

+ Simpler compiler: no need to optimize small instructions as much

Disadvantages of Complex Instructions

- Larger chunks of work compiler has less opportunity to

optimize (limited in fine-grained optimizations it can do)

- More complex hardware translation from a high level to

control signals and optimization needs to be done by hardware

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ISA-level Tradeoffs: Semantic Gap

Where to place the ISA? Semantic gap

Closer to high-level language (HLL) Small semantic gap,

complex instructions

Closer to hardware control signals? Large semantic gap,

simple instructions

RISC vs. CISC machines

RISC: Reduced instruction set computer

CISC: Complex instruction set computer

FFT, QUICKSORT, POLY, FP instructions?

VAX INDEX instruction (array access with bounds checking)

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ISA-level Tradeoffs: Semantic Gap

Some tradeoffs (for you to think about)

Simple compiler, complex hardware vs. complex compiler, simple hardware

Caveat: Translation (indirection) can change the tradeoff!

Burden of backward compatibility

Performance?

Optimization opportunity: Example of VAX INDEX instruction: who (compiler vs. hardware) puts more effort into optimization?

Instruction size, code size

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X86: Small Semantic Gap: String Operations

An instruction operates on a string

Move one string of arbitrary length to another location

Compare two strings

Enabled by the ability to specify repeated execution of an instruction (in the ISA)

Using a “prefix” called REP prefix

Example: REP MOVS instruction

Only two bytes: REP prefix byte and MOVS opcode byte (F2 A4)

Implicit source and destination registers pointing to the two strings (ESI, EDI)

Implicit count register (ECX) specifies how long the string is

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X86: Small Semantic Gap: String Operations

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REP MOVS (DEST SRC)

How many instructions does this take in MIPS?

Small Semantic Gap Examples in VAX

FIND FIRST

Find the first set bit in a bit field

Helps OS resource allocation operations

SAVE CONTEXT, LOAD CONTEXT

Special context switching instructions

INSQUEUE, REMQUEUE

Operations on doubly linked list

INDEX

Array access with bounds checking

STRING Operations

Compare strings, find substrings, …

Cyclic Redundancy Check Instruction

EDITPC

Implements editing functions to display fixed format output

Digital Equipment Corp., “VAX11 780 Architecture Handbook,” 1977-78.

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Small versus Large Semantic Gap

CISC vs. RISC

Complex instruction set computer complex instructions

Initially motivated by “not good enough” code generation

Reduced instruction set computer simple instructions

John Cocke, mid 1970s, IBM 801

Goal: enable better compiler control and optimization

RISC motivated by

Memory stalls (no work done in a complex instruction when there is a memory stall?)

When is this correct?

Simplifying the hardware lower cost, higher frequency

Enabling the compiler to optimize the code better

Find fine-grained parallelism to reduce stalls

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How High or Low Can You Go?

Very large semantic gap

Each instruction specifies the complete set of control signals in the machine

Compiler generates control signals

Open microcode (John Cocke, circa 1970s)

Gave way to optimizing compilers

Very small semantic gap

ISA is (almost) the same as high-level language

Java machines, LISP machines, object-oriented machines, capability-based machines

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A Note on ISA Evolution

ISAs have evolved to reflect/satisfy the concerns of the day

Examples:

Limited on-chip and off-chip memory size

Limited compiler optimization technology

Limited memory bandwidth

Need for specialization in important applications (e.g., MMX)

Use of translation (in HW and SW) enabled underlying implementations to be similar, regardless of the ISA

Concept of dynamic/static interface

Contrast it with hardware/software interface

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Effect of Translation

One can translate from one ISA to another ISA to change the semantic gap tradeoffs

Examples

Intel’s and AMD’s x86 implementations translate x86 instructions into programmer-invisible microoperations (simple instructions) in hardware

Transmeta’s x86 implementations translated x86 instructions into “secret” VLIW instructions in software (code morphing software)

Think about the tradeoffs

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ISA-level Tradeoffs: Instruction Length

Fixed length: Length of all instructions the same

+ Easier to decode single instruction in hardware

+ Easier to decode multiple instructions concurrently

-- Wasted bits in instructions (Why is this bad?)

-- Harder-to-extend ISA (how to add new instructions?)

Variable length: Length of instructions different (determined by opcode and sub-opcode)

+ Compact encoding (Why is this good?)

Intel 432: Huffman encoding (sort of). 6 to 321 bit instructions. How?

-- More logic to decode a single instruction

-- Harder to decode multiple instructions concurrently

Tradeoffs Code size (memory space, bandwidth, latency) vs. hardware complexity

ISA extensibility and expressiveness

Performance? Smaller code vs. imperfect decode 21

ISA-level Tradeoffs: Uniform Decode

Uniform decode: Same bits in each instruction correspond to the same meaning

Opcode is always in the same location

Ditto operand specifiers, immediate values, …

Many “RISC” ISAs: Alpha, MIPS, SPARC

+ Easier decode, simpler hardware

+ Enables parallelism: generate target address before knowing the instruction is a branch

-- Restricts instruction format (fewer instructions?) or wastes space

Non-uniform decode

E.g., opcode can be the 1st-7th byte in x86

+ More compact and powerful instruction format

-- More complex decode logic

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x86 vs. Alpha Instruction Formats

x86:

Alpha:

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MIPS Instruction Format

R-type, 3 register operands

I-type, 2 register operands and 16-bit immediate operand

J-type, 26-bit immediate operand

Simple Decoding

4 bytes per instruction, regardless of format

must be 4-byte aligned (2 lsb of PC must be 2b’00)

format and fields easy to extract in hardware

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R-type 0 6-bit

rs 5-bit

rt 5-bit

rd 5-bit

shamt 5-bit

funct 6-bit

opcode 6-bit

rs 5-bit

rt 5-bit

immediate 16-bit

I-type

opcode 6-bit

immediate 26-bit

J-type

A Note on Length and Uniformity

Uniform decode usually goes with fixed length

In a variable length ISA, uniform decode can be a property of instructions of the same length

It is hard to think of it as a property of instructions of different lengths

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A Note on RISC vs. CISC

Usually, …

RISC

Simple instructions

Fixed length

Uniform decode

Few addressing modes

CISC

Complex instructions

Variable length

Non-uniform decode

Many addressing modes

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ISA-level Tradeoffs: Number of Registers

Affects:

Number of bits used for encoding register address

Number of values kept in fast storage (register file)

(uarch) Size, access time, power consumption of register file

Large number of registers:

+ Enables better register allocation (and optimizations) by compiler fewer saves/restores

-- Larger instruction size

-- Larger register file size

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