17MB95_SERVICE_MANUAL.pdf

2

Table of Contents

1. INTRODUCTION ........................................................................................................................... 3

2. TUNER ............................................................................................................................................ 4

3. AUDIO AMPLIFIER STAGES ...................................................................................................... 8

A. MAIN AMPLIFIER (TAS5719)(6-8 W option) ......................................................................... 8

B. MAIN AMPLIFIER (TS4962M)(2.5 W option) ....................................................................... 12

C. HEADPHONE AMPLIFIER STAGE ....................................................................................... 14

4. POWER STAGE ........................................................................................................................... 15

5. MICROCONTROLLER (MSTAR MSD8WB9BX)..................................................................... 24

6. 1Gb DDR3 SDRAM ..................................................................................................................... 28

7. 1Gb G-die DDR3 SDRAM ........................................................................................................... 29

8. 2Gbit (256M x 8 bit) NAND Flash Memory ................................................................................. 31

9. 16M-BIT [16M x 1] CMOS SERIAL FLASH EEPROM ............................................................ 35

10. USB Interface ................................................................................................................................ 38

11. CI Interface .................................................................................................................................... 41

12. Demodulator Stage ........................................................................................................................ 41

13. LNB supply and control IC ........................................................................................................... 47

14. Software Update ............................................................................................................................ 49

15. Troubleshooting ............................................................................................................................. 49

A. No Backlight Problem ........................................................................................................... 49

B. CI Module Problem ............................................................................................................... 51

C. Staying in Stand-by Mode ..................................................................................................... 53

D. IR Problem ............................................................................................................................ 54

E. Keypad Touchpad Problems.................................................................................................. 54

F. USB Problems ....................................................................................................................... 55

G. No Sound Problem ................................................................................................................ 56

H. Standby On/Off Problem ....................................................................................................... 56

I. No Signal Problem ................................................................................................................ 57

16. Service Menu Settings ................................................................................................................... 57

17. General Block Diagram ................................................................................................................. 63

3

1. INTRODUCTION

17MB95 main board is driven by MStar SOC. This IC is a single chip iDTV solution that

supports channel decoding, MPEG decoding, and media-center functionality enabled by a

high performance AV CODEC and CPU.

Key features includes,

Combo Front-End Demodulator

A multi standart A/V format decoder

The MACEpro video processor

Home theatre sound processor

Internet and Variety of Connectivity Support

Dual-stream decoder for 3D contents

Mlti-purpose CPU for OS and multimedia

Peripheral and power management

Supported peripherals are:

1 RF input VHF I, VHF III, UHF

1 Satellite input

1 Side AV (CVBS, R/L_Audio)

1 SCART socket(Common)

1 Side YPbPr

1 Side S-Video(Common)

1 PC input(Common)

3 HDMI input

1 Common interface(Common)

1 S/PDIF output

1 Headphone(Common)

2 USB

1 Ethernet-RJ45

1 External Touchpad(Common)

4

2. TUNER

A. SI2156 Terrestrial and Cable TV Tuner:

A.1. Description:

The Si2156 integrates a complete hybrid TV tuner supporting all worldwide terrestrial and

cable TV standards. Leveraging Silicon Labs field proven digital low-IF architecture, the

Si2156 maintains the unmatched performance and design simplicity of the Si2153 while

further reducing footprint size and bill of materials cost. No external LNAs, tracking filters,

wirewound inductors, or SAW filters are used.

Compared with competing silicon tuners and discrete MOPLL-based tuners, the Si2156

delivers superior picture quality and a higher number of received stations in crowded and

near/far real-world reception conditions. The high linearity and low noise RF front-end

delivers superior blocking performance and higher sensitivity in the presence of strong

undesired channels and interference.

The Si2156 integrates the complete signal path from antenna input to IF outputs for both

analog and digital transmission standards. Compared to traditional discrete MOPLL-based

tuners, the Si2156 eliminates hundreds of external components including external LNAs,

tracking filter varactors and inductors (unlike competing silicon tuners), and SAW filters,

resulting in the simplest, lowest-cost BOM for a hybrid TV tuner.

Interfacing the Si2156 seamlessly with the Si2165 DVB-T/C demodulator creates a

complete terrestrial and cable DVB-T/C receiver plus PAL/SECAM tuner.

A.2. Features:

- Worldwide hybrid TV tuner

- Analog TV: NTSC, PAL/SECAM

- Digital TV: ATSC/QAM, DVB-T/T2/C, ISDB-T/C, DTMB

- 42-1002 MHz frequency range

- Compliance to A/74, NorDig, D-Book, C-Book, ARIB, EN55020, OpenCable

specifications

- Best-in-class real-world reception

- Exceeds discrete MOPLL-based tuners

- Highly integrated, lowest BOM

- No SAW filters or wirewound inductors required

- Integrated LNAs and complete tracking filters

5

- No alignment, tuning or calibration required

- Digital low-IF architecture

- Integrated channel select filters

- Flexible output interface

- ALIF to analog TV demodulator or SoC

- DLIF to digital TV demodulator or SoC

- 3.3 and 1.8 V power supplies

- Standard CMOS process technology

- 5 x 5 mm, 32-pin QFN package

- RoHS compliant

Figure 1: Pin description

6

Table 1: Pin functions

7

B. M88TS2022 Satellite Tuner

B.1. Features and General Description

B.2. Pin Assigment

8

B.3. Absolute Maximum Ratings and Recommended Operating

Conditions

3. AUDIO AMPLIFIER STAGES

A. MAIN AMPLIFIER (TAS5719)(6-8 W option)

a. General Description

The TAS5717/TAS5719 is a 10-W/15-W, efficient,digital audio-power amplifier for

driving stereo bridge-tied speakers. One serial data input allows processing of up to two

discrete audio channels and seamless integration to most digital audio processors and MPEG

decoders. The device accepts a wide of input data and data rates. A fully programmable data

path routes these channels to the internal speaker drivers.

The TAS5717/9 is a slave-only device receiving all clocks from external sources. The

TAS5717/TAS5719 operates with a PWM carrier between a 384-kHz switching rate and a

352-KHz switching rate, depending on the input sample rate. Oversampling combined with a

fourth-order noise shaper provides a flat noise floor and excellent dynamic range from 20 Hz

to 20 kHz.

9

b. Features

Audio Input/Output

TAS5717 Supports 210 W and TAS5719 Supports 215 W Output

Wide PVDD Range, From 4.5 V to 26 V

Efficient Class-D Operation Eliminates Need for Heatsinks

Requires Only 3.3 V and PVDD

One Serial Audio Input (Two Audio Channels)

I2C Address Selection via PIN (Chip Select)

Supports 8-kHz to 48-kHz Sample Rate (LJ/RJ/I2S)

External Headphone-Amplifier Shutdown Signal

Integrated CAP-Free Headphone Amplifier

Stereo Headphone (Stereo 2-V RMS Line Driver) Outputs

Audio/PWM Processing

Independent Channel Volume Controls With 24-dB to Mute

Programmable Two-Band Dynamic Range Control

14 Programmable Biquads for Speaker EQ

Programmable Coefficients for DRC Filters

DC Blocking Filters

0.125-dB Fine Volume Support

General Features

Serial Control Interface Operational Without MCLK

Factory-Trimmed Internal Oscillator for Automatic Rate Detection

Surface Mount, 48-Pin, 7-mm 7-mm HTQFP Package

AD, BD, and Ternary PWM-Mode Support

Thermal and Short-Circuit Protection

10

Benefits

EQ: Speaker Equalization Improves Audio Performance

DRC: Dynamic Range Compression. Can Be Used As Power Limiter. Enables

Speaker Protection, Easy Listening, Night-Mode Listening

DirectPath Technology: Eliminates Bulky DC Blocking Capacitors

Stereo Headphone/Stereo Line Drivers: Adjust Gain via External Resistors, Dedicated

Active Headpone Mute Pin, High Signal-to-Noise Ratio

Two-Band DRC: Set Two Different Thresholds for Low- and High-Frequency

Content

c. Pin descriptions and functions:


11


12

Table 3: Recomnended operating conditions

B. MAIN AMPLIFIER (TS4962M)(2.5 W option)

a. General Description

The TS4962M is a differential Class-D BTL power amplifier. It is able to drive up to 2.3W

into a 4 load and 1.4W into a 8 load at 5V. It achieves outstanding efficiency (88%typ.)

compared to classical Class-AB audio amps. The gain of the device can be controlled via two

external gain-setting resistors. Pop & click reduction circuitry provides low on/off switch

noise while allowing the device to start within 5ms. A standby function (active low) allows

the reduction of current consumption to 10nA typ.

b. Features

- Operating from VCC = 2.4V to 5.5V

- Standby mode active low

- Output power: 3W into 4 and 1.75W into 8

- with 10% THD+N max and 5V power supply.

- Output power: 2.3W @5V or 0.75W @ 3.0V

- into 4 with 1% THD+N max.

- Output power: 1.4W @5V or 0.45W @ 3.0V

- into 8 with 1% THD+N max.

- Adjustable gain via external resistors

- Low current consumption 2mA @ 3V

- Efficiency: 88% typ.

- Signal to noise ratio: 85dB typ.

- PSRR: 63dB typ. @217Hz with 6dB gain

- PWM base frequency: 250kHz

13

- Low pop & click noise

- Thermal shutdown protection

- Available in flip-chip 9 x 300m (Pb-free)

c. Pin descriptions and functions:


14

Table 4: Recommended operating conditions

C. HEADPHONE AMPLIFIER STAGE

Headphone is a SoC (single on chip) configuration in mainboard, design scheme is shown

in figure 4.

Figure 4: Headphone

15

4. POWER STAGE

Figure 5: Power socket and power options

Power socket is used for taking voltages which are 3.3V, 12V, 5V and 24V(VDD_Audio).

These voltages are produced in power card. Also socket is used for giving dimming, backlight

and standbye signals with power card. t is shown in figure 5.

24V(VDD_Audio) goes directly to the audio side, through power socket other incoming

voltages from power card are converted several voltages.

Figure 6: Power steps

16

FDC642P

General Description and Features

TPS65251

a) General Description

The TPS65251 features three synchronous wide input range high efficiency buck

converters. The converters are designed to simplify its application while giving the designer

the option to optimize their usage according to the target application.

The converters can operate in 5-, 9-, 12- or 15-V systems and have integrated power

transistors. The output voltage can be set externally using a resistor divider to any value

between 0.8 V and close to the input supply. Each converter features enable pin that allows a

delayed start-up for sequencing purposes, soft start pin that allows adjustable soft-start time

by choosing the soft-start capacitor, and a current limit (RLIMx) pin that enables designer to

adjust current limit by selecting an external resistor and optimize the choice of inductor. The

current mode control allows a simple RC compensation.

The switching frequency of the converters can either be set with an external resistor

connected to ROSC pin or can be synchronized to an external clock connected to SYNC pin if

needed. The switching regulators are designed to operate from 300 kHz to 2.2 MHz. 180 out

of phase operation between Buck 1 and Buck 2, 3 (Buck 2 and 3 run in phase) minimizes the

input filter requirements.

17

TPS65251 features a supervisor circuit that monitors each converter output. The PGOOD

pin is asserted once sequencing is done, all PG signals are reported and a selectable end of

reset time lapses. The polarity of the PGOOD signal is active high.

TPS65251 also features a light load pulse skipping mode (PSM) by allowing the LOW_P

pin tied to V3V. The PSM mode allows for a reduction on the input power supplied to the

system when the host processor is in stand-by (low activity) mode.

b) Features

Wide Input Supply Voltage Range (4.5 V - 18 V)

0.8 V, 1% Accuracy Reference

Continuous Loading: 3 A (Buck 1), 2 A (Buck 2 and 3)

Maximum Current: 3.5 A (Buck 1), 2.5 A (Buck 2 and 3)

Adjustable Switching Frequency 300 kHz - 2.2 MHz Set By External Resistor

Dedicated Enable for Each Buck

External Synchronization Pin for Oscillator

External Enable/Sequencing and Soft Start Pins

Adjustable Current Limit Set By External Resistor

Soft Start Pins

Current-Mode Control With Simple Compensation Circuit

Power Good

Optional Low Power Mode Operation for Light Loads

QFN Package, 40-Pin 6 mm x 6 mm RHA

APPLICATIONS

Set Top Boxes

Blu-ray DVD

Security Camera

Car Audio/Video

DTV

DVR

18



19


MP1484


The MP1484 is a monolithic synchronous buck regulator. The device integrates top and

bottom 85m MOSFETS that provide 3A of continuous load current over a wide operating

input voltage of 4.75V to 18V. Current mode control provides fast transient response and

cycle-by-cycle current limit.

An adjustable soft-start prevents inrush current at turn-on and in shutdown mode, the

supply current drops below 1A.

The MP1484 is PIN compatible to the MP1482 2A/18V/Synchronous Step-Down Converter.

b) Features

3A Continuous Output Current

Wide 4.75V to 18V Operating Input Range

Integrated 85m Power MOSFET Switches

20

Output Adjustable from 0.925V to 20V

Up to 95% Efficiency

Programmable Soft-Start

Stable with Low ESR Ceramic Output Capacitors

Fixed 340KHz Frequency

Cycle-by-Cycle Over Current Protection

Input Under Voltage Lockout

Thermally Enhanced 8-Pin SOIC Package

APPLICATIONS

FPGA, ASIC, DSP Power Supplies

LCD TV

Green Electronics/Appliances

Notebook Computers

Figure 8: General description

21


APL5910


The APL5910 is a 1A ultra low dropout linear regulator. The IC needs two supply

voltages, one is a control voltage (VCNTL) for the control circuitry, the other is a main

supply voltage (VIN) for power conversion, to reduce power dissipation and provide

extremely low dropout voltage. The APL5910 integrates many functions. A Power-On- Reset

(POR) circuit monitors both supply voltages on VCNTL and VIN pins to prevent erroneous

operations. The functions of thermal shutdown and current-limit protect the device against

thermal and current over-loads. A POK indicates that the output voltage status with a delay

time set internally. It can control other converter for power sequence. The APL5910 can be

enabled by other power systems. Pulling and holding the EN voltage below 0.4V shuts off the

output.

The APL5910 is available in a SOP-8P package which features small size as SOP-8 and an

Exposed Pad to reduce the junction-to-case resistance to extend power range of applications.

b) Features

Ultra Low Dropout

- 0.12V (Typical) at 1AOutput Current

0.8V Reference Voltage

High Output Accuracy

- 1.5%over Line, Load, and Temperature Range

22

Fast Transient Response

Adjustable Output Voltage

Power-On-Reset Monitoring on Both VCNTL and VIN Pins

Internal Soft-Start

Current-Limit and ShortCurrent-Limit Protections

Thermal Shutdown with Hysteresis

Open-Drain VOUT Voltage Indicator (POK)

Low Shutdown Quiescent Current (< 30mA )

Shutdown/Enable Control Function

Simple SOP-8P Package with Exposed Pad

Lead Free and Green Devices Available (RoHS Compliant)

APPLICATIONS

Motherboards, VGA Cards

Notebook PCs

Add-in Cards

Figure 9: Pin configuration


23

Table 9: Pin description

LM1117


The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at

800mA of load current. It has the same pin-out as National Semiconductors industry standard

LM317.

The LM1117 is available in an adjustable version, which can set the output voltage from

1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed

voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V.

The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener

trimmed bandgap reference to assure output voltage accuracy to within 1%.

The LM1117 series is available in LLP, TO-263, SOT-223, TO-220, and TO-252 D-PAK

packages. A minimum of 10F tantalum capacitor is required at the output to improve the

transient response and stability.

b) Features

Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions

Space Saving SOT-223 and LLP Packages

Current Limiting and Thermal Protection

Output Current 800mA

Line Regulation 0.2% (Max)

Load Regulation 0.4% (Max)

Temperature Range:

24

- LM1117 0C to 125C

- LM1117I 40C to 125C

Applications

- 2.85V Model for SCSI-2 Active Termination

- Post Regulator for Switching DC/DC Converter

- High Efficiency Linear Regulators

- Battery Charger

- Battery Powered Instrumentation

5. MICROCONTROLLER (MSTAR MSD8WB9BX)


25

b) Features

28


6. 1Gb DDR3 SDRAM

Hynix H5TQ1G630FA

a) Description

The H5TQ1G6(8)3DFR-xxx series are a 1,073,741,824-bit CMOS Double Data Rate III

(DDR3) Synchronous DRAM, ideally suited for the main memory applications which

requires large memory density and high bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully

synchronous operations referenced to both rising and falling edges of the clock. While all

addresses and control inputs are latched on the rising edges of the CK (falling edges of the

CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling

edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high

bandwidth.

b) Features

DQ Power & Power supply : VDD & VDDQ = 1.5V +/- 0.075V

DQ Ground supply : VSSQ = Ground

Fully differential clock inputs (CK, CK) operation

Differential Data Strobe (DQS, DQS)

On chip DLL align DQ, DQS and DQS transition with CK transition

DM masks write data-in at the both rising and falling edges of the data strobe

All addresses and control inputs except data, data strobes and data masks latched on the

rising edges of the clock

Programmable CAS latency 6, 7, 8, 9, 10, 11, 12, 13 and 14 supported

Programmable additive latency 0, CL-1, and CL-2 supported

Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10

Programmable burst length 4/8 with both nibble sequential and interleave mode

Programmable PASR(Partial Array Self-Refresh) for Digital consumer Applications.

29

Programmable BL=4 supported (tCCD=2CLK) for Digi-tal consumer Applications.

Programmable ZQ calibration supported

BL switch on the fly

8banks

Average Refresh Cycle (Tcase of 0 oC~ 95 oC)

- 7.8 s at -40oC ~ 85 oC

- 3.9 s at 85oC ~ 95 oC

- Commercial Temperature ( 0oC ~ 85 oC)

- Industrial Temperature ( -40oC ~ 85 oC)

Auto Self Refresh supported

JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)

Driver strength selected by EMRS

Dynamic On Die Termination supported

Asynchronous RESET pin supported

TDQS (Termination Data Strobe) supported (x8 only)

Write Levelization supported

On Die Thermal Sensor supported

8 bit pre-fetch


7. 1Gb G-die DDR3 SDRAM

Samsung K4B1G1646G

a) Key Features

JEDEC standard 1.5V 0.075V Power Supply

VDDQ = 1.5V 0.075V

400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for

1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin 900MHz fCK for 1866Mb/sec/pin

30

8 Banks

Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,13

Programmable Additive Latency: 0, CL-2 or CL-1 clock

Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-

1333), 8 (DDR3-1600) and 9 (DDR3-1866)

8-bit pre-fetch

Burst Length: 8 (Interleave without any limit, sequential with starting address 000 only), 4

with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or

MRS]

Bi-directional Differential Data-Strobe

Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm 1%)

On Die Termination using ODT pin

Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at 85C < TCASE < 95 C

Asynchronous Reset

Package : 78 balls FBGA - x4/x8

All of Lead-Free products are compliant for RoHS

All of products are Halogen-free

Table 12: 1Gb DDR3 G-die Speed bins

b) Description

The 1Gb DDR3 SDRAM G-die is organized as a 32Mbit x 4 I/Os x 8banks, 16Mbit x 8

I/Os x 8banks device. This synchronous device achieves high speed double-data-rate transfer

rates of up to 1866Mb/sec/pin (DDR3- 1866) for general applications.

The chip is designed to comply with the following key DDR3 SDRAM fea-tures such as

posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using

ODT pin and Asynchronous Reset.

All of the control and address inputs are synchronized with a pair of exter-nally supplied

differential clocks. Inputs are latched at the crosspoint of dif-ferential clocks (CK rising and

31

CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in

a source synchronous fash-ion. The address bus is used to convey row, column, and bank

address information in a RAS/CAS multiplexing style. The DDR3 device operates with a

single 1.5V 0.075V power supply and 1.5V 0.075V VDDQ. The 1Gb DDR3 G-die device

is available in 78ball FBGAs(x4/x8).

Table 13: Absolute Maximum DC Ratings


8. 2Gbit (256M x 8 bit) NAND Flash Memory

H27U2G8F2CTR-BC

a) Key Features

DENSITY

- 2Gbit: 2048blocks

Nand FLASH INTERFACE

- NAND Interface

- ADDRESS / DATA Multiplexing

SUPPLY VOLTAGE

- Vcc = 3.0/1.8V Volt core supply voltage for Program,

Erase and Read operations.

MEMORY CELL ARRAY

- X8: (2K + 64) bytes x 64 pages x 2048 blocks

- X16: (1k+32) words x 64 pages x 2048 blocks

PAGE SIZE

- X8: (2048 + 64 spare) bytes

32

- X16:(1024 + 32spare) Words

Block SIZE

- X8: (128K + 4K spare) bytes

- X16:(64K + 2K spare) Words

PAGE READ / PROGRAM

- Random access: 25us (Max)

- Sequential access: 25ns / 45ns (3.0V/1.8V, min.)

- Program time(3.0V/1.8V): 200us / 250us (Typ)

- Multi-page program time (2 pages):

200us / 250us (3.0V/1.8V, Typ.)

BLOCK ERASE / MULTIPLE BLOCK ERASE

- Block erase time: 3.5 ms (Typ)

- Multi-block erase time (2 blocks):

3.5ms/ 3.5ms (3.0V/1.8V, Typ.)

SEQURITY

- OTP area

- Serial number (unique ID)

- Hardware program/erase disabled during Power transition

- Multiplane Architecture:

Array is split into two independent planes.

Parallel operations on both planes are available, having

program and erase time.

- Single and multiplane copy back program with automatic

EDC (error detection code)

- Single and multiplane page re-program

- Single and multiplane cache program

- Cache read

- Multiplane block erase

Reliability

- 100,000 Program / Erase cycles (with 1bit /528Byte ECC)

- 10 Year Data retention

ONFI 1.0 COMPLIANT COMMAND SET

ELECTRONICAL SIGNATURE

- Maunufacture ID: ADh

33

- Device ID

PACKAGE

- Lead/Halogen Free

- TSOP48 12 x 20 x 1.2 mm

- FBGA63 9 x 11 x 1.0 mm

b) Description

H27(U_S)2G8_6F2C series is a 256Mx8bit with spare 8Mx8 bit capacity. The device is

offered in 3.0/1.8 Vcc Power Supply, and with x8 and x16 I/O interface Its NAND cell

provides the most cost-effective solution for the solid state mass storage market. The memory

is divided into blocks that can be erased independently so it is possible to preserve valid data

while old data is erased.

The device contains 2048 blocks, composed by 64 pages. Memory array is split into 2

planes, each of them consisting of 1024 blocks. Like all other 2KB - page NAND Flash

devices, a program operation allows to write the 2112-byte page in typical 200us(3.3V) and

an erase operation can be performed in typical 3.5ms on a 128K-byte block.

In addition to this, thanks to multi-plane architecture, it is possible to program 2 pages at a

time (one per each plane) or to erase 2 blocks at a time (again, one per each plane). As a

consequence, multi-plane architecture allows program time to be reduced by 40% and erase

time to be reduction by 50%. In case of multi-plane operation, there is small degradation at

1.8V application in terms of program/erase time.

The multiplane operations are supported both with traditional and ONFI 1.0 protocols.

Data in the page can be read out at 25ns (3V version) and 45ns (1.8V version) cycle time per

byte. The I/O pins serve as the ports for address and data input/output as well as command

input. This interface allows a reduced pin count and easy migration towards different

densities, without any rearrangement of footprint. Commands, Data and Addresses are

synchronously introduced using CE#, WE#, ALE and CLE input pin. The on-chip

Program/Erase Controller automates all read, program and erase functions including pulse

repetition, where required, and internal verification and margining of data.

A WP# pin is available to provide hardware protection against program and erase operations.

The output pin RB# (open drain buffer) signals the status of the device during each

operation. In a system with multiple memories the RB# pins can be connected all together to

provide a global status signal. Each block can be programmed and erased up to 100,000

cycles with ECC (error correction code) on. To extend the lifetime of Nand Flash devices, the

34

implementation of an ECC is mandatory. The chip supports CE# don't care function. This

function allows the direct download of the code from the NAND Flash memory device by a

microcontroller, since the CE# transitions do not stop the read operation. In addition, device

supports ONFI 1.0 specification.

The copy back function allows the optimization of defective blocks management: when a

page program operation fails the data can be directly programmed in another page inside the

same array section without the time consuming serial

data insertion phase. Copy back operation automatically executes embedded error detection

operation: 1 bit error out of every 528-byte (x8) or 1 bit error out of every 264-word (x16) can

be detected. With this feature it is no longer necessary to use an external to detect copy back

operation errors. Multiplane copy back is also supported, both with traditional and ONFI 1.0

protocols. Data read out after copy back read (both for single and multiplane cases) is

allowed. In addition, Cache program and multi cache program operations improve the

programing throughput by programing data using the cache register.

The devices provide two innovative features: page re-program and multiplane page re

program. The page re-program allows to re-program one page. Normally, this operation is

performed after a previously failed page program operation.Similarly, the multiplane page re-

program allows to re-program two pages in parallel, one per each plane. The first page must

be in the first plane while the second page must be in the second plane; the multiplane page

re-program operation is performed after a previously failed multiplane page program

operation. The page re-program and multiplane page re-program guarantee imporve

performance, since data insertion can be omitted during re-program operations, and save ram

buffer at the host in the case of program failure. The devices, available in the TSOP48

(12X20mm) package, support the ONFI1.0 specfication and come with four sequrity features:

- OTP (one time programmable) area, which is a restricted access area where sensitive

data/code can be stored permantely.

- Serial number (unique identifier), which allows the devices to be uniquely indentified.

- Read ID2 extention

These security features are subject to an NDA (non-disclosure agreement) and are,

therefore, no described in the datasheet. For more details about them, contact your nearest

Hynix sales office.

35

Table 15: DC and operating characteristic

9. 16M-BIT [16M x 1] CMOS SERIAL FLASH EEPROM

MX25L1602 Mstar SPI Flash

a) Key Features

HIGH DENSITY NAND FLASH MEMORIES

GENERAL

16,777,216 x 1 bit structure

256 Equal Sectors with 8K-byte each

- Any sector can be erased

4096 Equal Segments with 512-byte each

- Provides sequential output within any segment

Single Power Supply Operation

- 3.0 to 3.6 volt for read, erase, and program operations

Latch-up protected to 100mA from -1V to Vcc +1V

Low Vcc write inhibit is equal to or less than 2.5V

36

PERFORMANCE

High Performance

- Fast access time: 20MHz serial clock (50pF + 1TTL Load)

- Fast program time: 5ms/page (typical, 128-byte per page)

- Fast erase time: 300ms/sector (typical, 8K-byte per sector)

Low Power Consumption

- Low active read current: 10mA (typical) at 17MHz

- Low active programming current: 10mA (typical)

- Low active erase current: 10mA (typical)

- Low standby current: 30uA (typical, CMOS)

Minimum 100,000 erase/program cycle

SOFTWARE FEATURES

Input Data Format

- 1-byte Command code, 3-byte address, 1-byte byte address

512-byte Sequential Read Operation

Built in 9-bit (A0 to A8) pre-settable address counter to support the 512-byte sequential read

operation

Auto Erase and Auto Program Algorithm

- Automatically erases and verifies data at selected sector

- Automatically programs and verifies data at selected page by an internal algroithm

that automatically times the program pulse widths (Any page to be programed should have

page in the erased state first)

Status Register Feature

- Provides detection of program and erase operation completion.

- Provides auto erase/ program error report

HARDWARE FEATURES

SCLK Input

- Serial clock input

SI Input

- Serial Data Input

SO Output

- Serial Data Output

37

PACKAGE

- 28-pin SOP (330mil)

b) General Description

The MX25L1602 is a CMOS 16,777,216 bit serial Flash EEPROM, which is configured as

2,097,152 x 8 internally. The MX25L1602 features a serial peripheral interface and software

protocol allowing operation on a simple 3- wire bus. The three bus signals are a clock input

(SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is

enabled by CS input.

The MX25L1602 provide sequential read operation on whole chip. The sequential read

operation is executed on a segment (512 byte) basis. User may start to read from any byte of

the segment. While the end of the segment is reached, the device will wrap around to the

beginning of the segment and continuously outputs data until CS goes high.

After program/erase command is issued, auto program/ erase algorithms which

program/erase and verify the specified page locations will be executed. Program command is

executed on a page (128 bytes) basis, and erase command is executed on both chip and sector

(8K bytes) basis.

To provide user with ease of interface, a status register is included to indicate the status of

the chip. The status read command can be issued to detect completion and error flag status of

a program or erase operation.

When the device is not in operation and CS is high, it is put in standby mode and draws

less than 30uA DC current.

The MX25L1602 utilizes MXIC's proprietary memory cell which reliably stores memory

contents even after 100,000 program and erase cycles.

38

Figure: Pin configuration.

Table 16: Pin description

10. USB Interface

Mstar IC has two input port for USB, therefore air mause, internal wi-fi interface and

USB2 are combined with HUB. This property is optional. If air mause and wi-fi interfaces are

not alined, two USB are connected directly to main IC.

39

Figure 10: USB description

USB2512B


The SMSC USB251xB/xBi hub is a family of low-power, configurable, MTT (multi

transaction translator) hub controller IC products for embedded USB solutions. The x in the

part number indicates the number of downstream ports available, while the B indicates battery

charging support. The SMSC hub supports lowspeed, full-speed, and hi-speed (if operating as

a hispeed hub) downstream devices on all of the enabled downstream ports.

b) Features

- USB251xB/xBi products are fully footprint compatible with USB251x/xi/xA/xAi

products as direct drop-in replacements

Cost savings include using the same PCB components and application of

USB-IF Compliance by Similarity

- Full power management with individual or ganged power control of each downstream

port

- Fully integrated USB termination and pull-up/pulldown resistors

- Supports a single external 3.3 V supply source; internal regulators provide 1.2 V

internal core voltage

- Onboard 24 MHz crystal driver, ceramic resonator, or external 24/48 MHz clock input

- Customizable vendor ID, product ID, and device ID

- 4 kilovolts of HBM JESD22-A114F ESD protection (powered and unpowered)

- Supports self- or bus-powered operation

40

- Supports the USB Battery Charging specification Rev. 1.1 for Charging Downstream

Ports (CDP)

- 36-pin QFN (6x6 mm) Lead-free RoHS compliant package

- USB251xBi products support the industrial temperature range of -40C to +85C

- USB251xB products support the extended commercial temperature range of 0C to

+85C

c) Applications

- LCD monitors and TVs

- Multi-function USB peripherals

- PC motherboards

- Set-top boxes, DVD players, DVR/PVR

- Printers and scanners

- PC media drive bay

- Portable hub boxes

- Mobile PC docking

- Embedded systems

Figure 11: Pin configurations

41

11. CI Interface

17MB95 Digital CI ve Smart Card Interface Block diagram:

Figure 12: CI interface

12. Demodulator Stage

A. MSB1231 DVB-T2

a) Key Features

42

b) General Description

c) Block Diagram

43

d) Pinning

44

e) Absolute Maximum Ratings and Recommended Operating Conditions

45

B. M88DS3002 DVB-S/S2 Demodulator

a) Key Features and General Description

46

b) Block Diagram

c) Pin Information

47

a) Absolute Maximum Ratings and Recommended Operating Conditions

13. LNB supply and control IC

MP8125


The MP8125 is a voltage regulator designed to provide efficient, low noise power to the

Satellite receivers RF LNB (Low Noise Block) converter via coaxial cable through a DiSEqC

1.x compatible link that receives instructions from a dedicated controller.

The MP8125 integrates a current mode boost regulator followed by a tracking linear

regulator. The boost regulator provides a clean and quiet power source that will not

contaminate the low noise RF signal down converted to the receiver. The tracking linear

regulator protects the output against overload or short.

The MP8125 provides a number of features described in the European EUTELSAT

specification (DiSEqC) including: voltage selection of horizontal or vertical polarization

directions of LNB and a selectable VOUT compensation for voltage drop on the long coaxial

cable. In accordance with DiSEqC standard, a tone signal of 22kHz is generated by an internal

oscillator and can be activated or deactivated onto output by EXTM pin.

The MP8125 is available in thermally enhanced TSSOP16 package.

48

b) Key Features

DiSEqC 1.x Compatibility

Up to 550mA Output Current

8V to 14V Input Voltage

Boost Converter with Internal Switch

Low Noise LDO Output

Built-in 22kHz Tone Signal Generator

Programmable Current Limit

1V Line Drop Compensation

Adjustable Soft-start Time

POK Indicator

Short Circuit Protection

Over Temperature Protection

TSSOP16 Exposed Pad Package

APPLICATIONS

LNB Power Supply and Control for Satellite Set Top Boxes

c) Package Reference

49

a) Absolute Maximum Ratings and Recommended Operating Conditions

14. Software Update

14.1 Main SW update

In MB95 project there is only one software. From following steps software update procedure

can be seen:

1. MB90_en.bin, mboot.bin and usb_auto_update_A1.txt documents should copy directly

inside of a flash memory(not in a folder).

2. Insert flash memory to the tv when tv is powered off.

3. While pushing the OK button in remote control, power on the and wait. TV will power-up

itself.

4. If First Time Installation screen comes, it means software update procedure is successful.

15. Troubleshooting

A. No Backlight Problem

Problem: If TV is working, led is normal and there is no picture and backlight on the panel.

Possible couses: Backlight pin, dimming pin, backlight supply, stby on/off pin

BACKLIGHT_ON/OFF pin should be high when the backlight is ON. R119 must be low

when the backlight is OFF. If it is a problem, please check Q10 and the panel cables. Also it

can be tested in TP50 in main board.

50

Dimming pin should be high or square wave in open position. If it is low, please check S60

for Mstar side and panel or power cables, connectors.

Backlight power supply should be in panel specs. Please check Q33, shown below; also it can

be checked TP53.

51

STBY_ON/OFF_NOT should be low for tv on condition, please check Q11s collector.

B. CI Module Problem

Problem: CI is not working when CI module inserted.

Possible couses: Supply, suply control pin, detect pins, mechanical positions of pins.

CI supply should be 5V when CI module inserted. If it is not 5V please check

CI_PWR_CTRL, this pin should be low.

52

Please check mechanical position of CI module. Is it inserted properly or not?

Detect ports should be low. If it is not low please check CI connector pins, CI module

pins.

53

C. Staying in Stand-by Mode

Problem: Staying in stand-by mode, no other operation

This problem indicates a short on Vcc voltages. Protect pin should be logic high while normal

operation. When there is a short circuit protect pin will be logic low. If you detect logic low

on protect pin, unplug the TV set and control voltage points with a multimeter to find the

shorted voltage to ground.

54

D. IR Problem

Problem: LED or IR not working

Check LED card supply on MB95 chasis.

E. Keypad Touchpad Problems

Problem: Keypad or Touchpad is not working

Check keypad supply on MB95.

55

F. USB Problems

Problem: USB is not working or no USB Detection.

Check USB Supply, It should be nearly 5V. Also USB Enable should be logic high.

56

G. No Sound Problem

Problem: No audio at main TV speaker outputs.

Check supply voltages of 24V VDD_AUDIO, 3.3V AUDIO_AVDD and AUDIO_DVDD

with a voltage-meter. There may be a problem in headphone connector or headphone detect

circuit (when headphone is connected, speakers are automatically muted). Measure voltage at

HP_DETECT pin, it should be 3.3v.

H. Standby On/Off Problem

Problem: Device can not boot, TV hangs in standby mode.

There may be a problem about power supply. Check main supplies with a voltage-meter. Also

there may be a problem about SW. Try to update TV with latest SW. Additionally it is good

to check SW printouts via Teraterm. These printouts may give a clue about the problem. You

can use Scart-1 for terraterm connection.

57

I. No Signal Problem

Problem: No signal in TV mode.

Check tuner supply voltage; 5V_VCC, 3V3_TUNER and 1V8_TUNER. Check tuner options

are correctly set in Service menu. Check AGC voltage at IF_AGC pin of tuner.

16. Service Menu Settings

In order to reach service menu, first Press MENU buton, then write 4725 by uisng

remote controller.

You can see the service menu main screen below. You can check SW releases by using this

menu. In addition, you can make changes on video, audio etc. by using video settings, audio

settings titles.

58

Service Menu Main Screen

Video Settings

59

Audio Settings

Options-1 Menu

60

Options-2 Menu

Options-3 Menu

61

Tuner Settings Menu

Source Settings Menu

62

Diagnostic Menu

63

17. General Block Diagram

17mb95-210

01_HDMI_GPIO_PROT

26-06-2012_15:33

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

A3PROJECT NAME :VESTELSCH NAME :

DRAWN BY :

T. SHT:

330k

R5

3V3_STBY

4k7

R13

12

3V3_STBY

100RR114

MSD8WB9BXU4

AE25

AE1

U23T25T24T23A25 A1

J6H6H5G5

F6N23P23N25N24

N6L6D3K4M6M7M4J4L5K6M5K5

W21T22AB22U22AA18

B3A3C3

F4A9F7A8B8D6D7E4D4

B7D5E2B6F5E3C7 GPIO36

GPIO37GPIO38GPIO39GPIO40GPIO41GPIO42

GPIO43/UART2_TXGPIO44/UART2_RXGPIO45GPIO46GPIO47/UART4_TXGPIO48/UART4_RXGPIO49GPIO51GPIO52

GPIO58GPIO61GPIO62

GPIO131GPIO132GPIO133GPIO134GPIO135

GPIO6GPIO7/PM_UART1_TX

GPIO8GPIO12/CSZ1

GPIO10GPIO11/PM_UART1_RX

GPIO13GPIO14GPIO15GPIO16GPIO17GPIO18

PWM0PWM1PWM2PWM3

PWM_PM

SAR0SAR1SAR2SAR3NC

_0

NC_1

NC_2

NC_3

NC_4

NC_5

NC_6

NC_7

9

47k

R14

12

STBY_ON/OFF_NOT

1k2

R8

U4MSD8WB9BX

D1D2

AD12

AC13

B5B4C5C4C6A6

T6

R5T4R6F2F3H2H3G2G1G3F1

AD4W6V6R2R3U2U3T2T1T3R1

T5U6U5J2J3L2L3K2K1K3J1

N4AD1V4V5M2M3P2P3N2N1N3M1 RXA0N

RXA0PRXA1NRXA1PRXA2NRXA2PRXACKNRXACKPDDCDA_CKDDCDA_DAHOTPLUGAARC0

RXB0NRXB0PRXB1NRXB1PRXB2NRXB2PRXBCKNRXBCKPDDCDB_CKDDCDB_DAHOTPLUGB

RXC0NRXC0PRXC1NRXC1PRXC2NRXC2PRXCCKNRXCCKP

DDCDC_CKDDCDC_DAHOTPLUGC

RXD0NRXD0PRXD1NRXD1PRXD2NRXD2PRXDCKNRXDCKP

DDCDD_CKDDCDD_DAHOTPLUGD

CECRNRPGPIO56/LED[1]

TPGPIO55/LED[0]

TN

DP_P1

DM_P1

DP_P0

DM_P0

3

BC848BQ2

1

2

3

HDMI1_RX0N

CN4

12345678910111213141516171819

2021

4k7R11

1 2

HDMI0_RX0PHDMI0_RX1NHDMI0_RX1PHDMI0_RX2NHDMI0_RX2PHDMI0_CLKN

HDMI0_RX0N

HDMI0_CLKP

HDMI0_ARC

6V31uF

C14HDMI0_ARC

4k7

R14

41

23V

3_ST

BY3V3_VCC

R143

4k7

12

4k7

R14

21

2

R9710R1

47k

R19

12

47k

R30

12

R22 47k

12

47k

R31

12

10RR98

12

R9910R1 2

CN6

12345678910111213141516171819

2021

CEC

10RR100

1

10RR106

1 2

R11210R1

R12410R2

10RR141

1 2

HDMI1_CLKP

HDMI1_CLKN

HDMI1_RX0P

HDMI1_RX0N

HDMI1_RX1P

HDMI1_RX1N

HDMI1_RX2P

HDMI1_RX2N

10RR158

1 2

R16010R1 2

10RR166

1 2 HDMI2_HPDIN

HDMI0_SCLHDMI0_SDA

CEC

HDMI1_SCLHDMI1_SDA

HDMI1_5VHDMI1_HPDIN10R

R511 2

R5210R1 2

10RR53

1 2

10RR54

1 2

R5510R2

R5610R1

10RR57

1 2

10RR58

1

CECR5910R1 2

10RR60

12

47k

R23

12

47k

R24

12

10RR61

1

10RR62

12

R25 47k

12

10RR63

12

R6410R1 2

10RR65

12

R6610R1 2

R6710R1 2

R6810R 12

R6910R1 2

R7010R1 2

R7110R1 2

R7210R1 2 HDMI0_HPDIN

HDMI0_5V

HDMI0_RX2P

HDMI0_CLKP

HDMI0_CLKN

HDMI0_RX0N

HDMI0_RX0PHDMI0_RX1N

HDMI0_RX1PHDMI0_RX2N

HDMI0_SCLHDMI0_SDA

HDMI0_HPDIN

HDMI0_5V

R821k1 2

R831k1 2

1k2

R10

HDMI1_RX0PHDMI1_RX1NHDMI1_RX1PHDMI1_RX2NHDMI1_RX2PHDMI1_CLKNHDMI1_CLKPHDMI1_SCLHDMI1_SDA

R841k1 2Q5

BC848B1

2

3

HDMI1_HPDIN R851k1 2

HDMI1_5V

R86100R

HDMI2_5V

HDMI2_SDA

CEC

HDMI2_SCL

HDMI2_RX2N

HDMI2_RX2P

ETH_TXN

ETH_TXP

ETH_RXPETH_RXN

HDMI2_RX1N

HDMI2_RX1P

HDMI2_RX0N

HDMI2_RX0P

HDMI2_CLKN

HDMI2_CLKP

R32 47k

12

CN5

12345678910111213141516171819

2021

USB2_DN

USB2_DP

USB1_DP

USB1_DN

HDMI2_5V

Q4BC848B

1

2

3

HDMI2_HPDINR391k 12

1k2

R33

R401k 12

R14k71 23V3_VCC

3V3_VCC

R116

5k1

5k1

R122

ETH_GRN

ETH_YEL

R125

5k1

5k1

R130

3V3_

STBY

LED2

100RR261

LNB_POKR273100R

LED1

AMP_MUTE

HP_MUTEHP_DETECT

BACKLIGHT_DIM

PANEL_VCC_ON/OFF

R140

4k7

12

3V3_

VCC

1V8_VCC_TUNER

R614

33k

R66318k

R66218k

33k

R613

BC848BQ36

DVD_WAKEUP

HDMI0_5V

PWM1

3V3_

STBY

D19

C5V

6

4k7

R260

12

3V3_VCC

HDMI2_RX0PHDMI2_RX1NHDMI2_RX1PHDMI2_RX2NHDMI2_RX2PHDMI2_CLKN

HDMI2_RX0N

HDMI2_CLKPHDMI2_SCLHDMI2_SDA

PWM0

3V3_

STBY

R12

94k

71

2R12

84k

71

23V

3_ST

BY

10k

R18

31

2

BC848BQ7

3V3_VCC

TOUCHPAD_SCL

TOUCHPAD_SDA

R342100R

3V3_STBY4k7R127

1 2

R1264k71 2

R347100R PC_DET

PWM_OUT_LED3

R12

34k

71

23V

3_ST

BY

SC_PIN8

BACKLIGHT_ON/O

FF

S27

3V3_VCC

R12

14k

71

2

4k7R120

12

4k7R119

BC848BQ10

3D_ENABLE

3V3_VCC

USB_ENABLE2USB_ENABLE1

TUNER_RST

LINEDROPEXT_RESET

PCM_CD1

CI_PWR_CTRL

FLASH_WP

HDMI1_5V

SPI_CS

R111

4k7

12

4k7

R11

01

23V

3_ST

BY

PANEL_VCC

PROTECT

3V3_STBY

4k7

R109

12

KEYBOARD

R10

810

k

5V_VCC

12V_VCC

R258220R

C562100nF16V

C6261uF16V

U28MAX809LTR

3

2 1GNDRST

VCC

4k7

R12

12

DVD_IR_ON/OFF

DVD_SENSE

R7152k7

R6971k

R10715k

33R

R738

R737

33R

USB

_OCD2

USB

_OCD1 4k7

R4

12

R3

4k7

12

AUX_RESET

AUX_RESET

5V_VCC

BAW56

D26

10kR195

1 2

10kR194

1 2

TP7 PROTECT

C52100nF

10V1

2

R19210k 12

R61133k 12

3V3_STBY

10kR191

1 2

R19010k1 2

R18

910

k1

2

BAW56

D24

R18810k1 2

24V_VCC_AU

Q8BC848B

R18610k1 2R18510k1 2

R343100R

12V_VCC

10kR712

1 2

Q35BC858B

3V3_VCC_TUNER

HDMI2_5VR16818k

R214

33k

S2_RESET

HDMI1

HDMI2

NC

HDMI3

GPIO

HDMI / USB

1V2 - 1V25 -1V5 - 2V5 - 3V3 FROM ICs POWER GOOD PINS

SHORT CCT PROTECTION

17mb9510

ALP KIRAZ-BARAN UBUKU02_MSTAR_DDR3

06-04-2012_10:54

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F


DRAWN BY :

T. SHT:

U4MSD8WB9BX

J20J21K25K24G23G25F25E20F20F24G20D20L20H24A24B25B24

K21H21L21H20K20H22L22G21

K23M23H23M24J23L24J24L23

D23E21F23C25C24D21D24D22E23F21E24G22F22D25B23

A18B18C18B19A17C17B16F11E13B15F13E14A21E15C12B12A12

C20D16A20E16C21F16B20G16

D15A22F14B22F15B21G15D17

B13E11A15C13C16D12B14D11A14E12C15F12B11C14A11 A_DDR3_A0

A_DDR3_A1A_DDR3_A2A_DDR3_A3A_DDR3_A4A_DDR3_A5A_DDR3_A6A_DDR3_A7A_DDR3_A8A_DDR3_A9A_DDR3_A10A_DDR3_A11A_DDR3_A12A_DDR3_A13A_DDR3_A14

A_DDR3_DQL0A_DDR3_DQL1A_DDR3_DQL2A_DDR3_DQL3A_DDR3_DQL4A_DDR3_DQL5A_DDR3_DQL6A_DDR3_DQL7

A_DDR3_DQU0A_DDR3_DQU1A_DDR3_DQU2A_DDR3_DQU3A_DDR3_DQU4A_DDR3_DQU5A_DDR3_DQU6A_DDR3_DQU7

A_DDR3_CASZA_DDR3_RASZA_DDR3_WEZA_DDR3_DMLA_DDR3_DMUA_DDR3_ODTA_DDR3_BA0A_DDR3_BA1A_DDR3_BA2A_DDR3_RESETA_DDR3_CKEA_DDR3_MCLKA_DDR3_MCLKZA_DDR3_DQSLA_DDR3_DQSLBA_DDR3_DQSUA_DDR3_DQSUB

B_DDR3_A0B_DDR3_A1B_DDR3_A2B_DDR3_A3B_DDR3_A4B_DDR3_A5B_DDR3_A6B_DDR3_A7B_DDR3_A8B_DDR3_A9B_DDR3_A10B_DDR3_A11B_DDR3_A12B_DDR3_A13B_DDR3_A14

B_DDR3_DQL0B_DDR3_DQL1B_DDR3_DQL2B_DDR3_DQL3B_DDR3_DQL4B_DDR3_DQL5B_DDR3_DQL6B_DDR3_DQL7

B_DDR3_DQU0B_DDR3_DQU1B_DDR3_DQU2B_DDR3_DQU3B_DDR3_DQU4B_DDR3_DQU5B_DDR3_DQU6B_DDR3_DQU7

B_DDR3_CASZB_DDR3_RASZB_DDR3_WEZB_DDR3_DMLB_DDR3_DMUB_DDR3_ODTB_DDR3_BA0B_DDR3_BA1B_DDR3_BA2

B_DDR3_RESETB_DDR3_CKE

B_DDR3_MCLKB_DDR3_MCLKZB_DDR3_DQSLB_DDR3_DQSLBB_DDR3_DQSUB_DDR3_DQSUB

1

DDR0_VREFDQ

DDR0_DMUDDR0_DML

DDR0_DQSUBDDR0_DQSU

DDR0_DQSLBDDR0_DQSL

DDR0_DQL0DDR0_DQL1DDR0_DQL2DDR0_DQL3DDR0_DQL4DDR0_DQL5

DDR0_RESETB

DDR0_WEBDDR0_CASBDDR0_RASB

DDR0_CKE

DDR0_

CK

DDR0_

CKB

DDR0_BA2DDR0_BA1

DDR0_A12

DDR0_A10DDR0_A11

DDR0_A09DDR0_A08

DDR0_A06DDR0_A05DDR0_A04DDR0_A03DDR0_A02

DDR0_A00DDR0_A01

DDR0_A07

DDR0_A13

DDR0_BA0

DDR0_DQL6DDR0_DQL7

DDR0_DQU0DDR0_DQU1DDR0_DQU2DDR0_DQU3DDR0_DQU4DDR0_DQU5DDR0_DQU6DDR0_DQU7

1V5_DDR0

DDR0_VREFCA

DDR1_VREFDQ

1V5_VCC 1V5_VCC

1kR408

R409

1k

R4101k

DDR0_ODT

R32

156

R

50V

1nF

C322

240RR418

U7H5TQ2G63BFR-PB

A9

B3

E1

G8

J2

J8

M1

M9

P1

P9

T1

T9

B1

B9

D1

D8

E2

E8

F9

G1

G9

K1

D3E7

C7B7

G3F3

A3B8A2A7C2C8C3D7

H7G2H8H3F8F2F7E3

M8H1

B2

D9

G7

K2

K8

N1

N9

R1

R9

A1

A8

C1

C9

D2

E9

F1

H2

H9

L8T2

L3K3J3

L2

K9

K7J7

M3N8M2

J9T7L9M7L1J1

T3N7R7L7R3T8R2R8P2P8N2P3P7N3 A0

A1A2A3A4A5A6A7A8A9A10/APA11A12/BCA13

NC1NC2NC3NC4NC5NC6

BA0BA1BA2

CK_0CK_1

CKE

CS

RASCASWE

RESETZQ

VDDQ_

9VDDQ_

8VDDQ_

7VDDQ_

6VDDQ_

5VDDQ_

4VDDQ_

3VDDQ_

2VDDQ_

1

VDD_9

VDD_8

VDD_7

VDD_6

VDD_5

VDD_4

VDD_3

VDD_2

VDD_1

VREF_DQVREF_CA

DQL0DQL1DQL2DQL3DQL4DQL5DQL6DQL7

DQU0DQU1DQU2DQU3DQU4DQU5DQU6DQU7

DQSL_0DQSL_1

DQSU_1DQSU_0

DMLDMU

ODT

VSS

Q_9

VSS

Q_8

VSS

Q_7

VSS

Q_6

VSS

Q_5

VSS

Q_4

VSS

Q_3

VSS

Q_2

VSS

Q_1

VSS

_12

VSS

_11

VSS

_10

VSS

_9VSS

_8VSS

_7VSS

_6VSS

_5VSS

_4VSS

_3VSS

_2VSS

_1

DDR0_A00DDR0_A01DDR0_A02DDR0_A03DDR0_A04DDR0_A05DDR0_A06DDR0_A07DDR0_A08DDR0_A09DDR0_A10DDR0_A11DDR0_A12

DDR0_A13

DDR0_DQL0DDR0_DQL1DDR0_DQL2DDR0_DQL3DDR0_DQL4DDR0_DQL5DDR0_DQL6DDR0_DQL7


DDR0_CASBDDR0_RASBDDR0_WEBDDR0_DMLDDR0_DMUDDR0_ODTDDR0_BA0DDR0_BA1DDR0_BA2

DDR0_RESETBDDR0_CKEDDR0_CK

DDR0_CKBDDR0_DQSL

DDR0_DQSLBDDR0_DQSU

DDR0_DQSUB

1V5_VCC60R

F12

R32

256

R16

V10

nF

C34

2

C246

100nF

16V

R411

1k 50V

1nF

C323

16V

100nF

C247

DDR1_VREFCADDR1_VREFDQ

C21310uF10V

C248100nF16V 16V

100nFC249 C250

100nF16V

DDR1_DMUDDR1_DML

DDR1_DQSUBDDR1_DQSU

DDR1_DQSLBDDR1_DQSL

DDR1_DQL0DDR1_DQL1DDR1_DQL2DDR1_DQL3DDR1_DQL4DDR1_DQL5

DDR1_RESETB

DDR1_WEBDDR1_CASBDDR1_RASB

DDR1_BA2DDR1_BA1

DDR1_A12

DDR1_A10DDR1_A11

DDR1_A09DDR1_A08

DDR1_A06DDR1_A05DDR1_A04DDR1_A03DDR1_A02

DDR1_A00DDR1_A01

DDR1_A07

DDR1_A13

DDR1_BA0

DDR1_DQL6DDR1_DQL7


1V5_DDR1

16V100nFC251

R421240R

U8H5TQ2G63BFR-PB

A9

B3

E1

G8

J2

J8

M1

M9

P1

P9

T1

T9

B1

B9

D1

D8

E2

E8

F9

G1

G9

K1

D3E7

C7B7

G3F3

A3B8A2A7C2C8C3D7

H7G2H8H3F8F2F7E3

M8H1

B2

D9

G7

K2

K8

N1

N9

R1

R9

A1

A8

C1

C9

D2

E9

F1

H2

H9

L8T2

L3K3J3

L2

K9

K7J7

M3N8M2

J9T7L9M7L1J1

T3N7R7L7R3T8R2R8P2P8N2P3P7N3 A0

A1A2A3A4A5A6A7A8A9A10/APA11A12/BCA13

NC1NC2NC3NC4NC5NC6

BA0BA1BA2

CK_0CK_1

CKE

CS

RASCASWE

RESETZQ

VDDQ_

9VDDQ_

8VDDQ_

7VDDQ_

6VDDQ_

5VDDQ_

4VDDQ_

3VDDQ_

2VDDQ_

1

VDD_9

VDD_8

VDD_7

VDD_6

VDD_5

VDD_4

VDD_3

VDD_2

VDD_1

VREF_DQVREF_CA

DQL0DQL1DQL2DQL3DQL4DQL5DQL6DQL7

DQU0DQU1DQU2DQU3DQU4DQU5DQU6DQU7

DQSL_0DQSL_1

DQSU_1DQSU_0

DMLDMU

ODT

VSS

Q_9

VSS

Q_8

VSS

Q_7

VSS

Q_6

VSS

Q_5

VSS

Q_4

VSS

Q_3

VSS

Q_2

VSS

Q_1

VSS

_12

VSS

_11

VSS

_10

VSS

_9VSS

_8VSS

_7VSS

_6VSS

_5VSS

_4VSS

_3VSS

_2VSS

_1

DDR1_ODT

DDR1_CKE

DDR1_

CK

DDR1_

CKB

R32

356

RC34

3

10nF

16V

R32

456

R

C252100nF16V 16V

100nFC253 C254

100nF16V 16V

100nFC255 C256

100nF16V

16V100nFC257 C258

100nF16V 16V

100nFC259 C260

100nF16V

DDR1_A00DDR1_A01DDR1_A02DDR1_A03DDR1_A04DDR1_A05DDR1_A06DDR1_A07DDR1_A08DDR1_A09DDR1_A10DDR1_A11DDR1_A12

DDR1_A13

DDR1_DQL0DDR1_DQL1DDR1_DQL2DDR1_DQL3

DDR1_DQU0

DDR1_DQL4DDR1_DQL5DDR1_DQL6DDR1_DQL7

DDR1_DQU1DDR1_DQU2DDR1_DQU3DDR1_DQU4DDR1_DQU5DDR1_DQU6DDR1_DQU7

DDR1_DQSUBDDR1_DQSUDDR1_DQSLBDDR1_DQSLDDR1_CKBDDR1_CKDDR1_CKEDDR1_RESETBDDR1_BA2DDR1_BA1DDR1_BA0DDR1_ODTDDR1_DMUDDR1_DMLDDR1_WEBDDR1_RASBDDR1_CASB

16V100nFC261 C262

100nF16V

DDR0_VREFCA

16V

100nF

C263

C324

50V

1nF

R412

1k

1kR413

1V5_VCC

DDR1_VREFCA

16V100nFC264 C265

100nF16V 16V

100nFC266

1V5_VCC

R4141k

1kR415

C325

1nF

50V

16V

100nF

C267

DDR0_VREFDQ

16V100nFC268

1V5_DDR0

10V10uFC214

F13

60R C269100nF16V

1V5_VCC

16V100nFC270 C271

100nF16V

C272100nF16V

100nF16V

C273 C274100nF16V

100nF16V

C275 C276100nF16V

100nF16V

C277

C278100nF16V

100nF16V

C279

16V100nFC280 C281

100nF16V

C282

16V100nF

C283100nF16V 16V

100nFC284 C285

100nF16V 16V

100nFC286 C287

100nF16V

1V5_DDR1

PL1

PL2

PL3

PL4

GROUND TERMINALS

DDR3

TS1_VLD

CI_PWR4k7R320

TP209

X10

24MHz

3142

2V5_VCCTP32

16V100nFC20

TP1091

TP115

ETH_GRN

ETH_YEL

R134510R

R137510R

CN10

14

13

12

11

8

7

10

9

6

1

5

4

3

2 TD-

TCT

RD+

RD-

TD+

RCT

GR+

GR-

NC1

NC2

YL+

YL-

SHLD1

SHLD2

ETH_TXN

ETH_TXP

C21100nF16V

R170

47R

R169

47R

ETH_RXN

ETH_RXP

16V

C22100nF

R172

47R

47R

R171

03-04-2012_10:24

03_CI_ETH_NAND 10ALP KIRAZ-BARAN UBUKU

17mb95

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F


DRAWN BY :

T. SHT:

CN9

68676665646362616059585756555453525150494847464544434241403938373635

34333231302928272625242322212019181716151413121110987654321

33RR503

UART-RX-SC

R1504k7

UART-TX-SC

3V3_STBY3V3_STBY

R1514k7

4k7R152

TS1CLK TS1_CLKR50433R

U10MX25L512

1234 5

678VCC

HOLD#SCLKSIGND

WP#SOCS#

U4MSD8WB9BX

U21Y18AA20T21AB19AD21AB18AC19AD20Y19

AE21AC20AB20AB17AD19AE20W22AB16V21AA22T20W19R20Y22AA21

AD18AA19AE18AC18AE17AB21AD22V20

C1C2B1B2A2

P20Y21P22P21AC21Y20W20R21 NF_ALE

NF_WPZNF_CEZNF_CLENF_REZNF_WEZNF_RBZNF_CEZ1

SPI_CKSPI_DISPI_DOTEST1SPI_CZ

PCM_D[0]/NF_AD[0]PCM_D[1]/NF_AD[1]PCM_D[2]/NF_AD[2]PCM_D[3]/NF_AD[3]PCM_D[4]/NF_AD[4]PCM_D[5]/NF_AD[5]PCM_D[6]/NF_AD[6]PCM_D[7]/NF_AD[7]

PCM_A[0]PCM_A[1]PCM_A[2]PCM_A[3]PCM_A[4]PCM_A[5]PCM_A[6]PCM_A[7]PCM_A[8]PCM_A[9]PCM_A[10]PCM_A[11]PCM_A[12]PCM_A[13]PCM_A[14]

PCM_IRQA_NPCM_OE_N

PCM_IORD_NPCM_CE_NPCM_WE_NPCM_CD_NPCM_RST

PCM_REG_NPCM_IOWR_NPCM_WAIT_N

4

100nF10V

C98

U13

NAND128-A

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

2524

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1 NC1

NC2

NC3

NC4

NC5

NC6

RB

R

E

NC7

NC8

VDD1

VSS1

NC9

NC10

CL

AL

W

WP

NC11

NC12

NC13

NC14

NC15 NC16

NC17

NC18

NC19

I/O0

I/O1

I/O2

I/O3

NC20

NC21

NC22

VSS2

VDD2

NC23

NC24

NC25

I/O4

I/O5

I/O6

I/O7

NC26

NC27

NC28

NC29

R240

10k

SPI_CLKSPI_DISPI_DO

3V3_STBY

NAND_ALENAND_WPZNAND_CEZNAND_CLENAND_REZNAND_WEZNAND_RBZ

SPI_CLK

SPI_DI

SPI_DO

SPI_CS

4k7

R15

3

3V3_STBY3V3_STBY

FLASH_WPR50533R

NAND_REZ

3V3_STBY

33RR506

R50733R

R50833R

33RR509

3V3_NAND

NAND_CEZ

NAND_RBZ

3k9

R574

3V3_NAND

NAND_CLE

NAND_ALE

NAND_WEZ

NAND_WPZ

33RR577

1

2

3

4 5

6

7

8

R4

R1

R3

R2

R57833R

1

2

3

4 5

6

7

8

R4

R1

R3

R2

33RR579

1

2

3

4 5

6

7

8

R4

R1

R3

R2

R58033R

1

2

3

4 5

6

7

8

R4

R1

R3

R2

6V3

22uFC210

3V3_NAND3V3_VCC

C291100nF

16V

C292

16V

100nF

F51

60R

3V3_NAND

PCMNANDD0PCMNANDD1PCMNANDD2PCMNANDD3PCMNANDD4PCMNANDD5PCMNANDD6PCMNANDD7

PCMA0PCMA1PCMA2PCMA3PCMA4PCMA5PCMA6PCMA7PCMA8PCMA9PCMA10PCMA11PCMA12PCMA13PCMA14

PCMWAIT

PCMOEPCMIORDPCMCEPCMWEPCMCD2PCMRSTPCMREGPCMIOWR

PCMWAIT

PCMNANDD2

PCMNANDD1

PCMNANDD0

PCMA0

PCMRST

PCMA5

PCMA4

PCM_IOWRPCMNANDD6

PCMNANDD5

PCMNANDD4

PCMNANDD3

PCMA1

PCMA2

PCMA3

PCMREG

33RR581

1

2

3

4 5

6

7

8

R4

R1

R3

R2

R58233R

1

2

3

4 5

6

7

8

R4

R1

R3

R2

33RR583

1

2

3

4 5

6

7

8

R4

R1

R3

R2

R58433R

1

2

3

4 5

6

7

8

R4

R1

R3

R2

PCMNANDD7

PCMCE

PCMA10

PCMIORD

PCMA6

PCMA7

PCMIRQA

PCMA12

PCMWE

PCMA14

PCMA13

PCMA8

PCMA9

PCMIOWR

PCMA11

PCMOE

R51033R PCM_CD2

PCM_NAND_D2

PCM_NAND_D1

PCM_NAND_D0

PCM_A0

PCM_NAND_D6

PCM_NAND_D5

PCM_NAND_D4

PCM_NAND_D3

PCM_A1

PCM_A2

PCM_A3

PCM_REG

PCM_IORD

PCM_A4

PCM_A5

PCM_RST

PCM_A6

PCM_A7

PCM_WAIT

PCM_A12

PCM_WE

PCM_A14

PCM_A13

PCM_A8

PCM_A9

PCM_IOWR

PCM_A11

PCM_OE

PCM_IORD

PCM_A10

PCM_CE

PCM_NAND_D7

PCMCD2

PCM_NAND_D0

PCM_NAND_D1

PCM_NAND_D2

PCM_NAND_D3

PCM_NAND_D4

PCM_NAND_D5

PCM_NAND_D6

PCM_NAND_D7

PCM_NAND_D3PCM_NAND_D4PCM_NAND_D5PCM_NAND_D6PCM_NAND_D7

PCM_NAND_D2PCM_NAND_D1PCM_NAND_D0PCM_A0PCM_A1PCM_A2PCM_A3PCM_A4PCM_A5PCM_A6PCM_A7PCM_A12

PCM_A10

PCM_A11PCM_A9PCM_A8PCM_A13PCM_A14

PCM_CE

PCM_OE

PCM_WE

PCMIRQA

R15

44k

7

CI_PWR

TP211

CI_PWR

TP64

1

10V100nFC99

1

2 C100100nF10V

1

2

5V_VCC60R

F15

BSH103

Q30

1

2 3

12V_VCC 47kR316

1 2

10V

100nF

C101

12

R31747k1 2

BC847BQ31

1

2

3

CI_PWR_CTRL

10V10uFC3

R24210k1 2

CI_PWRCI_PWR

TS1_VLDTS1_CLK

PCM_CD1

PCM_CD2

PCM_IRQA

PCM_IRQA

PCM_RST

4k7

R15

5

CI_PWR

PCM_WAIT

PCM_REG

TS0D0

TS1D5 TS1_D533RR585

8

7

6

5 4

3

2

1

R4

R1

R3

R2

TS1D7

TS1D6

TS1_D7

TS1_D6

TS0D1TS0D2TS0D3TS0D4TS0D5TS0D6TS0D7TS0CLKTS0VLDTS0SYNC

TS1SYNCTS1VLDTS1CLKTS1D7TS1D6TS1D5TS1D4TS1D3TS1D2TS1D1TS1D0

U4MSD8WB9BX

Y14Y15AB15AA15AB14AA14AA13Y13AA16AA17Y16

AD13AE15AC16AC17AD17AD16AC15AD15AE14AD14AC14

R25R24

P24R23R4P5

G4

AE2AE3

N5 RESET

XINXOUT

IRIN

DDCA_CK/UART0_RXDDCA_DA/UART0_TXUART3_RX/GPIO64UART3_TX/GPIO65

DDCR_CKDDCR_DA

TS1_D[0]TS1_D[1]TS1_D[2]TS1_D[3]TS1_D[4]TS1_D[5]TS1_D[6]TS1_D[7]TS1_CLKTS1_VLD

TS1_SYNC

TS0_D[0]TS0_D[1]TS0_D[2]TS0_D[3]TS0_D[4]TS0_D[5]TS0_D[6]TS0_D[7]TS0_CLKTS0_VLD

TS0_SYNC

8

TS0_SYNC

TS0_CLK

TS0VLD

TS0SYNC

TS0CLK

C44810pF

50V

TS0_VLD

TS0_D0

33RR587

8

7

6

5 4

3

2

1

R4

R1

R3

R2

TS0D2

TS0D1

TS0D0

TS0_D1 TS1_D4

TS0_D2

TS1D3

TS1D4

TS1VLD

R58833R

8

7

6

5 4

3

2

1

R4

R1

R3

R2 TS1_D3

TS1_D2TS1D2

TS0D7 TS0_D7

TS0_D3TS0_D4TS0_D5TS0_D6

TS1_SYNC

33RR589

8

7

6

5 4

3

2

1

R4

R1

R3

R2

TS1D1

TS1D0

TS1SYNC

TS1_D1

TS1_D0

TS0D4

TS0D5

TS0D6

R59033R

8

7

6

5 4

3

2

1

R4

R1

R3

R2 TS0_D4

TS0_D6

TS0_D5

TS0_D3TS0D3

TS0_D7

TS1_SYNCTS1_D0TS1_D1TS1_D2TS1_D3

TS0_VLDTS0_SYNC

TS0_D0TS0_D1TS0_D2

TS1_D4TS1_D5TS1_D6TS1_D7

TS0_CLK50V

10pFC378

R24

310

k10k

R244

3V3_VCC

3V3_VCC

S65

R39

51M

33pF

C39

0

50V

50V

C39

133

pF

4k7

R156

12

R157

4k7

12

3V3_VCC

SYS_SCLSYS_SDA

12pF

C39

2

50V

RESET

C102100nF10V

1

2

3V3_STBY

R24

510

k

22uFC394

16V

R3311k

1N41

48

D3

10V

100n

F

C10

3 21

RESETR361100R 12

R362100R 12IR_IN

6V3

220uF

C149

1N5819

D5

4k7R76

R1844k7

3V3_VCC

4k7R716

R7354k7

3V3_VCC

3V3_VCC

4k7R808

R58633R

50V

10pFC451

TP1101TP116

TP113

TP11

4

TP117

C1271uF

16V

60R

F52

75RR876

D36

C5V6

1 2

6V3

22uF

C4

TP210

R87775R

75RR878

R87975R

75RR880

R88175R

75RR882

R88375R

10V

10uF

C1197

MSTAR SPI FLASH

RESET

Place these capacitorsclose to transformer

nc

Place these resistors

CI/NAND

close to MSTAR

Ethe

rnet

lin

es m

ust

be 1

00oh

m di

ffer

enti

al p

airs

close to MSTAR

chassis ground.

transformer.any parts or traces under thedifferential pairs. Do not placeroute as matched lengthAlso keep traces short and

speed nets, except for the

Place these resistors

50V

C1

12pF

R308470R

33RR187

TUNER_SCL

R307100R

F164

60R1 2

S69

R312

820R

3V3_VCC_SI

R7979k1

6V3

C44

9

10uF

S751 247RR606

1 2

1n2F50V

C1441n2FC153

50V

390nH

L1

50V

C1541n2F

1n2FC155

50V

C156

50V1n2F

1V8_VCC_SI

DIGITAL_IF_P

100nF

10V

C158

S98

S99

D_IF_AGC

100nF

C159

10V

IF_AGC

16V

22nF

C162

S100

C1571n2F50V

C1634n7F50V

100nFC164

3V3_VCC_SI

1V8_VCC_TUNER 60R

F651 2

100nF16V

C165

3V3_VCC_TUNER

60R

F681 2

R73470R

S92

24MHz

X11

31

42

17mb9510

ALP KIRAZ-BARAN UBUKU04_TUNER_T2_DEMOD

27-03-2012_16:58

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F


DRAWN BY :

T. SHT:

TUNER_SDA

TUNER_SCL

50V1nFC326

S66

VGA_G

VGA_B

VGA_HSNCVGA_VSNC

VGA_R

VGA_G R51133R 47nF

C182 16VC183

R59368R

47nF16VC184R512

33RC185R59468R

68RR595

47nF16VC186

C18716V47nF 33R

R513SC_CVBS_IN

16V C18847nF

R59668R

CVBS0_OUT

C189 16V47nF

SC_FB

33RR514

SC_R 16VC190

47nF68RR597

SC_G R59868R

C19133RR515 C192 16V

47nF

R59968R

C193SC_B C194 16V

47nF33RR516SC_CVBS_IN

SC_R33RR517

C195

33RR518

33RR519

47nFC196 16V

33RR520

47nFC197

C19816V47nF

C199 16V47nF

R52133RC200 16V

47nF

R60068R

68RR601 C20133R

R522 C202 16V47nF

R60268R

C203 47nF16VC204R523

33RY_IN

PR_IN

PB_IN

Y_IN

S67

C3271nF

SAV_CVBS

U11MX25L512

1234 5

678VCC

HOLD#SCLKSIGND

WP#SOCS#

R52433R

C175 1uF

6V3

3V3_VCC

75R

R55

61

2

R55

775

R1

2

75R

R55

81

2

1nFC329

S68

R56

075

R1

2

DVD_CVBS

R247

10k

FLASH_WP_T2

3V3_VCC

3V3_VCCR1594k7

SPI_CS_T2SPI_DO_T2

SPI_DI_T2SPI_CLK_T2

C105

10V100nF

1N5819

D14

MSB1231U17

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49 GPIO[0]

VDDP_4

VDDC_3

GND_10

VDDP_5

I2CM_SCL

I2CM_SDA

RF_AGC

IF_AGC

GND_11

VDDC_4

VDDP_6

GND_12

I2CS_SCL

I2CS_SDA

GPIO[3]

AVDD_33_0

SAR_RSSI

GND_6

AVDD_33_1QMQPIMIP

GND_7

AVDD_25

AVDD_33_2

XOUT

XIN

GND_8

AVDD_33_3

GND_9

GPIO[11]

VDDP_3

VDDC_2

GND_5

VDDP_2

GPIO_2

SPI_CZ

SPI_DO

SPI_DI

SPI_CLK

GPIO_1

GND_4

VDDC_1

GND_3

VDDP_1

RESETZ

GND_2

TS_

ERR

TS_

CLK

TS_

DATA

[7]

TS_

DATA

[6]

TS_

DATA

[5]

TS_

DATA

[4]

VDDC_0

GND_1

VDDP_0

TS_

DATA

[3]

TS_

DATA

[2]

TS_

DATA

[1]

TS_

DATA

[0]

TS_

VLD

TS_

SYNC

3V3_VDDP

60R

F18

C21710uF10V

C293

16V100nF100nF

16V

C294C295

16V100nF100nF

16V

C296

16V100nFC297

1V2_VCC 1V2_VDD

1V2_

VDD

1V2_VDD

1V2_VDD1V2_VDD

1V2_VDD

F19

60R

60R

F20

F21

60R

60R

F22

100nF16V

C298

10V10uFC218

C21910uF10V

C299

16V100nF

100nF16V

C300C220

10V10uF

10uF10V

C221 C301

16V100nF

3V3_VCC

3V3_VCC

3V3_VCC

3V3_VCC

AVDD_APLL

AVDD_MPLL_T2

AVDD33_ADC

AVDD_SAR

2V5_VCC60R

F23AVDD25_ADC

10V10uFC222

16V100nFC302

AVDD_SAR

AVDD33_ADC

AVDD_MPLL_T2

AVDD_APLL

AVDD25_ADC

C431

50V

27pF

U4MSD8WB9BX

AE5AC6AD2AD3

AD5AC5

AD8AC8

AC7AD7

AD6AE6

AB4AA4

AB5W4W5Y4

Y5

AB8AA5AA6AB6Y6AA7Y7AA8

AC4AC3AA2Y2AA3AA1AB3AB1AB2

AC2AC1V1V3V2W3W1W2Y3 RIN0M

RIN0PGIN0MGIN0PBIN0MBIN0PSOGIN0HSYNC0VSYNC0

RIN1MRIN1PGIN1MGIN1PBIN1MBIN1PSOGIN1HSYNC1VSYNC1

RIN2MRIN2PGIN2MGIN2PBIN2MBIN2PSOGIN2HSYNC2

VCOM

CVBS0CVBS1CVBS2CVBS3

CVBSOUT1CVBSOUT2

IPIM

VIFPVIFM

SIFPSIFM

IFAGCRFAGC

TGPIO0/GPIO73TGPIO1/GPIO74TGPIO2/GPIO75TGPIO3/GPIO76

5DIGITAL_IF_P

100nF

C106

10V

10VC107

100nF

S70

S71

S72

DIGITAL_IF_N

100RR364

IF_AGC

6V3

22uF

C368

IF_P_T2

IF_N_T2

IF_P_T2

IF_N_T2

10V10uFC223

100nF16V

C303

16V100nFC304 C305

100nF16V

C306

16V100nF

C307

16V100nF

16V100nFC308 C309

100nF16V

3V3_VDDP3V3_VCC

3V3_

VDDP

3V3_VDDP

3V3_VDDP

3V3_VDDP3V3_VDDP

3V3_VDDP

C432

27pF

50V

IF_AGC_T2

DIGITAL_IF_N

S73

100nF

C108

10V

C109

10V100nFDIGITAL_IF_P

3V3_VCC

C110

10V

100nF

1kR33360R

F86

IF_AGC

IF_AGC_T2

EXT_RESET

C2

16V

100n

F

SPI_CS_T2

SPI_DO_T2

SPI_DI_T2

SPI_CLK_T2

FLASH_WP_T2S74

R3324k7

3V3_VCC

R161

4k7

12

4k7

R162

12

TUNER_SCLTUNER_SDA

S76

R37947R

47RR380

33R

R59

1

1 2 3 45678

R4

R1

R3

R2

TS1

_D0

TS1

_D1

TS1

_D2

TS1

_D3

TS1

_D4

TS1

_D5

TS1

_D6

TS1

_D7

R59

233

R8765

4 3 2 1

R4

R1

R3

R2

TS1_CLKR52533R

50V

C39

3

12pF

33RR526

R52733R

TS1_SYNC

TS1_VLDTP65

R25110k3V3_VCC

S77

10kR252

3V3_VCC

TP118TP119

TP120

TP121

TP122

TP123

S80

SH1

21

60R

F24

TP111 1

100R

R60

31

2

6V3

100u

FC43

5

3V3_VCC 1V8_VCC_TUNER

LM1117U14

1

23

4

VOUT

IN OUT

ADJ

U18SI2156

1 2 3 4 5 6 7 8

9

10

11

12

13

14

15

16

24 23 22 21 20 19 18 17

32

31

30

29

28

27

26

25 GND1

GND2

GND3

GPIO

INTB

RSTB

GND4

VDD_IO

XTAL_O

XTAL_I

VDD_H1

VDD_H2

RF_SHLD

RF_IN

RF_IP

RF_SHLD1

XOUT

BCLK

VDD_L

DLIF_P

DLIF_N

ALIF_P

VDD_H

ALIF_N

DLIF_AGC

ALIF_AGC

ADDR

GND

VDD_D

SDA

SCL

VDD_S

1V8_VCC_SI

3V3_VCC_SI

3V3_VCC_SI

3V3_VCC_SI

180R

F67

1 234

C112

50V

120pF

C113

120pF50V

L5

220nH

220nH

L6

L4

270nH50V

47pF

C566

RF_IN_N

C15100nF16V

RF_IN_N

RF_IN_P

RF_IN_P

X1

27MHz

31 42

DIGITAL_IF_N

3V3_VCC_SI

S82

3V3_VCC_TUNER

10kR196

S83

S84

S87

C6

12pF

1V8_

VCC_

SI

TUNER_SDAC1012pF

3V3_VCC_SI

JK11

68RR609

100RR407

12

TP112 1

100R

R60

41

2

D_IF_AGC

5V_VCC

C62

4

10uF

10V

C44

010

0uF

6V3

F165

60R1 2

TUNER_RST

S89

16V100nFC29

ESD0P8RFL

D8

4 3

21

LM1117U6

1

23

4

VOUT

IN OUT

ADJ

1k

F210

F211

1k

S213

750R

NC

OPTIONAL RESISTORS

OPTIONAL

NC

Close To Concept ICClose To SI2156

pin4

pin1pin32

T2 DEMOD SPI FLASH nc

nc

NC:1100000(R:1,W:0)

pin10pin19

TUNER

T2 DEMOD

VIDEO

pin20

High : D2 I2C Address**pin49

Low : F2

30067048

24 MHz CRYSTAL

pin14

nc

CN212

34

56

78

910

1112

1314

1516

1718

1920

24V_VCC_AU

DIMMING

BACKLIGHT_ON/OFF

5V_STBY

3V3_STBY

5V_VCC5V_VCC

TP89

12V_STBY

12V_STBY12V_STBY

TPS54528

5

6

7

8

4

3

2

1

U9EN

VFB

VREG5

VSS

VIN

VBST

SSW

GND

3V3_VCC3V3_VCC

3V3_VCC 3V3_VCC

12V_STBY 12V_STBY

S824V_VCC_AU

S25

12V_STBY

CN3

12

34

56

78

910

1112

1314

1516

1718

1920

S32STBY_ON/OFF_NOT

STBY_ON/OFF

5V_VCC 5V_VCC

3V3_STBY

5V_STBY

BACKLIGHT_ON/OFF S33

DIMMING

24V_VCC_AU

7A/32VDC

FS4

TP33

TP34

TP35

2k2

R35

TP36

12V_STBYFS1

7A/32VDC22kR36

1kR41

1 2

R4410k1 2

1k2

R34

Q27

FDC64

2P13

4 5 6

2

22k

R37

TP37

TP3812V_VCC

DIMMING

BACKLIGHT_ON/OFF

Q6

BC848B

JK2

5

4

3

2

1

Q19BC848B

TP48

TP50

TP51

FDC64

2PQ2

8

134 5 6

2

R96120k

C2422uF 6V3

R167

5k6

4k7

R335

12

R652220R

R28947k

6V3

22uF

C25

R288100R

10kR45

12

U21LM1117

1

23

4

VOUT

IN OUT

ADJ

FDC64

2PQ4

3

1 3456

2

6V3

22uF

C11

98

R29022k

10uF

10V

C225

60RF11 2

3V3_VCC

R821

18k

1V26_VCC100nF

C117

10V

TP105

TP106

TP107

TP108

1V5_DDR0

VDDC

10kR884

12

6V3

22uF

C12

28

Q46BC848B

BC848B

Q47

R13

910

k1

2

3V3_VCC

TPS_ENABLE

TPS_ENABLE

R16410k1 2

10kR163

12

R772k2

5V_STBYR2843k912V_STBY

10kR176

1 2 STBY_ON/OFF

R28210k1 2 STBY_ON/OFF_NOT

Q44

FDC642P

1 3456

2

10V220nFC5

7A/32VDC

FS2S10

S15

R4610k 12

12V_VCC

MOSFET_CONTROL

CN8

6

5

4

3

2

1

L3 10uH

06-07-2012_14:53

05_POWER 10ALP KIRAZ-BARAN UBUKU

17mb95

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F


DRAWN BY :

T. SHT:

12V_INV

12V_INV

1V2_VCC

C5V

6

D20

16V10uF

C1187

C304u7F10V

U19TPS65251

12345678910

11

12

13

14

15

16

17

18

19

20

30292827262524232221

40

39

38

37

36

35

34

33

32

31GND_1

VIN_0

VIN_1

VIN_2

GND_2

LX3_0

LX3_1

VIN3

BST3

EN3

RLIM2

SS2

COMP2

FB2

LOW_P

GND_0

PGOOD

V7V

V3V

AGNDEN2

BST2

VIN2

LX2_1

LX2_0

LX1_1

LX1_0

VIN1

BST

EN1

RLIM1

SS1

CMP1

FB1

ROSC

SYNC

FB3

CMP3

SS3

RLIM3

120kR644C472

4n7F50V

R646

20k

50V

4n7F

C473

FB3

10uF16V

C488

FB1R647

20k

C475

50V4n7F

R394100k

4n7F

C477

50V

60R

F531 2

12V_VCCC205

47nF16V

16V 10uF

C1189

4u7H

L40

C1210

22uF

6V3

S85

R822560R

R255

10k

C478

4n7F

50V

FB1

C1212

22uF

6V3

6V3

22uF

C1211

47nF

C206

16V

16V10uF

C1188

12V_

VCC

1V5_VCC

S86

FB2

50V

4n7F

C479

R65

17k

5

R101560R

R256

10k

FB2

R645120k

4n7F50V

C480

C48

1

4n7F

50V

R64

820

k

R257

10k

FB3

C483

4n7F

50V

TP90

F58

60R12

12V_VCC

16V10uF

C1190

4u7H

L38

F59 60R

12

60R

F6012

C119110uF

16V16V10uFC463

12V_VCCC207

16V47nF

R658

390k

U15

APL5910

1

2

3

4 5

6

7

8GND

FB

VOUT

NCVCNTL

VIN

EN

POK

S88 125V_VCC

5V_VCC

3V3_VCC

S216

R1654k7 12

33kR250

C22410uF10V

F17360R1 2

PROTECT

R81210k

R81147k

FDC64

2PQ2

9

134 5 6

2

R21

533k

12

12V_STBY

F63

60R1 2

C15110uF10V

3V3_VCC

5V_VCC

5V_VCC S6 12

U5

APL5910

1

2

3

4 5

6

7

8GND

FB

VOUT

NCVCNTL

VIN

EN

POK

10V

C152

100nF

MOSFET_CONTROLSTBY_ON/OFF_NOT

STBY_ON/OFF

S90

S91

2V5_VCC

6V3

22uFC132

1V5_VCCF66

60R1 2

S79PROTECT

12V_STBY12V_VCC

10kR48

12

VFB

10kR49

12

16V1uFC128

50V

8n2F

C129

12V_VCC

22uFC130

16V

C55

16V100nF22uF

16V

C13112V_STBY

60R

F31 2

60R

F41 2

100nF16V

C92

PROTECT

C133

22uF

6V3

S81

60R

F71 2

F10

60R1 2

C119100nF10V

1

2

6V3

22uF

C1213

5V_STBY 3V3_STBY

TP72 1

C1214

22uF

6V3

F14

60R1 2

BC848BQ21

47RR173

1 2

C13

4

25V

220n

F21 33k

R21

61

2

FDC64

2PQ3

2

134 5 6

2

C137

6V3220uF

C138

6V3220uF

TP52

MOSFET_CONTROLR4710k 12

5V_VCC

1kR42

5V_STBY

BC848BQ22

R17447R1 2

25V

C13

5

220n

F21 R21

733

k1

2

5V_VCC

5V_STBY

22kR38

4k7R15

50V22pFC139VFB

R19710k1 23V3_STBY STBY_ON/OFF

STBY_ON/OFF_NOTQ11BC848B

F62

60R1 2

10uH

L39

R19810k1 2

S5

16V10uFC460

C46110uF16V

6V3

22uF

C1209

C1206

50V4n7F

4n7F50V

C1207

C1208

50V4n7F

power_pin3

power_pin3

power_pin1

power_pin1

power cable

BTB

nc

ADAPTER SOCKET

12V_STBY

W/SAT

INVERTER SOCKET!

!

W_ADAPTER

30049469 1.13k

3V3_STBY

LDO2

LDO1

2V5_VCC

DC/DC4

DC/DC2

DC/DC3

! VIN2

VOUT2

VIN3

VOUT3

VOUT1

VIN1

DC/DC1

R2

R1

1V25_VCCR2

12V_VCC4A

SW1

nc

NC

SW2

0R

30069495 AP2111 ???

TPS54528

LDO3R1

5V_VCC

10k

R283

12

3V3_VCC

D8_TX_B_3_PD8_TX_B_3_N

S71

2

S521

2

S641

2

S781

2

S941

2

S951

2

S961

2

S971

2

S1011

2

S1021

2

S1031

2

S1041

2

S1051

2

D8_TX_B_CLK_PD8_TX_B_CLK_N

D8_TX_B_2_P

27-06-2012_15:24

06_LVDS

17MB95_SERVICE_MANUAL.pdf

Documents

Transcript of 17MB95_SERVICE_MANUAL.pdf