17.11.05 ONEBAT MeetingNovember 17, 2005

EPFL contribution

Samuel Rey-Mermet, Paul Muralt

17.11.05Outline

- New design for PEN- New photolithographic masks for PEN- Process flow- CGO dry etching- Lift-off- Ni plating- Patent- Main achievements- Milestones- Future work

17.11.05 New designs for PEN

PATENT PENDING

Ni grid without current collector

Ni grid with current collector

17.11.05

New photolithographic masks6 Masks:

Current collector, electrolyte, seed layer, mould, anode and membrane.

Grid and current collector line width: 5 um

Hexagone side: 50 umHexagone diagonal: 100 um

Contact anode(4 x 6 mm2)

Contact cathode(6 x 4 mm2)

Membrane(diam.5 mm)

2.4

cm

Connecting linesfor eplating

Ni grid

Current collector

17.11.05 Process Flow

Current collectordeposition

Photo. Mask 1CC etch

Dry etch CC

Deposition ofelectrolyte

PATENT PENDING

17.11.05 Process Flow

Photo. Mask 2Electrolyte etch

Electrolyte dryetch

Photo. Mask 3Seed layer

Deposition seedlayer

PATENT PENDING

17.11.05 Process Flow

Lift-off seed layer

Photo. Mask 4Mould eplating

Grid eplating

Resist removal

PATENT PENDING

17.11.05 Process Flow

Depostion porousanode (anode etch ?)

Photo. Mask 6Si etch

Si backside etch

Depostion porouscathode

PATENT PENDING

17.11.05 Process Flow Summary

16 main steps: Wafer 1 is before step 13

Critical points:

Lift-off definition

Cr/Au must be replaced by Ni

Cathode & Anode deposition

(LC Ni-CGO ~Ok, NMW)

Si dry etch (first test ok)

Dicing (Laser?)

17.11.05 CGO dry etching

ECRPlasma

RF chuck

2.45 GHz

RF 13.56 MHzWater cooled

Effect of the working pressure and rf power (chuck) on the etching rate of PZT thin film, selectivity for 60 W.

0

20

40

60

80

100

0.0001 0.0010 0.0100 0.1000 1.0000

PRESSURE [Pa]

Etc

hin

g R

ate

[nm

/min

]

0

1

2

3

4

5

Sel

ecti

vity

PZ

T/P

R

100 W RF60 W RF40 W RFSelectivity PZT/PR

Vbeam

Vacc

Ar, CF4, CCl4

17.11.05 CGO dry etching

Etching rate for Vbeam/Vacc=2, at 5 x 10-4 mBar, with 16 sccm Ar, 2 sccm CCl4, 4 sccm CF4, 80 W RF bias power

17.11.05 Evaporation

1 m

Designed for lift-off

1.5 10-6 mBar after 1h.

Cr, Au, Ti, Al, Ni

17.11.05 Lift-off

Lift-off is improved

Remaining parts of the seed-layer, broken grids…

100 um

100 um

17.11.05Ni eplating

100 um

Pt CC 100 nm thick

CGO 150-200 nm thick

Ni grid 5 um thick

17.11.05 PatentA PCT patent application is being prepared and filed before

December 16.

Annoying: Patent on grid by semiconductor process (CVD) US 2005/0115889 (Liliput?) filed in 9/2003, 8 months after our invention.

Lucky: No conductive grid, no electrolytic deposition claimed

17.11.05 Main achievements

100 m

50 m

Ni grids

Ni grids with CGO

17.11.05Milestones

• WP 1.1 Electrolyte– Dense, crack free, CGO 80/20 OK

– Conductivity=0.5 S/m @500°C OK

– Microstructure charact. OK

– Electrical charac. of membrane not OK

– Stress measur. OK

• WP 1.2 Anode– Ni-CGO, 500 S/cm @ RT in air, ~OK

porosity?

– Thermal stability not tested, grid ok

– Stress measur. not tested, no problem

• WP 1.3 Cathode– LSCF tested by PLD, not OK

– Stress not tested,

– Stress measur. not tested,

17.11.05Milestones

• WP 1.4 Microfab. and electrical testing– PEN with contacts in progress (anode, cathode from NMW)– 1st PEN in progress (step 12 of 16)– Concept Ni grid OK– Redesign PEN and contact Mask OK, Process Flow in progress– Integration of Ni grid Improvement in progress

17.11.05Next

Fabrication of a PEN including Ni-grid and NMW electrodes wafer 1: status:step #12/16

13=anode dep (NMW), 14/15=Si-etch, 16=cathode dep (NMW)

wafers 2-3: with better seed layer lift off and better Ni-grid

Thermal stability testing of this 1st PEN.

Electrical testing of this 1st PEN.