16th IEEE International Conference on High … IEEE International Conference on High Performance...

Proceedings

16th IEEE International Conference on

High Performance Computing and Communications

HPCC 2014

11th IEEE International Conference on

Embedded Software and Systems

ICESS 2014

6th International Symposium on

Cyberspace Safety and Security

CSS 2014

Organized by

FEMTO-ST Institute, Ecole Centrale Paris, Ecole des Mines de Paris

Sponsored by

IEEE IEEE Computer Society

IEEE Technical Committee on Scalable Computing

20-22 August 2014

Paris, France

Los Alamitos, California

Washington • Tokyo

2014 IEEE InternationalConference on High

Performance Computingand Communications (HPCC),2014 IEEE 6th InternationalSymposium on CyberspaceSafety and Security (CSS)

and 2014 IEEE 11thInternational Conferenceon Embedded Softwareand Systems (ICESS)

HPCC 2014Table of Contents

Message from the HPCC/ICESS/CSS 2014

General Chairs..........................................................................................................................................xxv

Message from the HPCC 2014 Program

Chairs........................................................................................................................................................xxvi

Message from the ICESS 2014 Program

Chairs.......................................................................................................................................................xxvii

Message from CSS 2014 Program Chairs ...........................................................................................xxviii

HPCC 2014 Organizing Committee........................................................................................................xxix

ICESS 2014 Organizing Committee.....................................................................................................xxxvii

CSS 2014 Organizing Committee ..............................................................................................................xl

v

IEEE International Conference onHigh PerformanceComputing and Communications (HPCC 2014)

HPCC DAr 1: Distributed ArchitectureEnabling PGAS Productivity with Hardware Support for Shared AddressMapping: A UPC Case Study .......................................................................................................................1

Olivier Serres, Abdullah Kayi, Ahmad Anbar, and Tarek El-Ghazawi

HoL-Blocking Avoidance Routing Algorithms in Direct Topologies ............................................................11Roberto Peñaranda Cebrian, Crispín Gómez Requena,María Engracia Gómez Requena, Pedro López Rodríguez, and Jose Duato Marín

Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches ..................................................19Vicente Lorente, Alejandro Valero, Salvador Petit, Pierfrancesco Foglia,and Julio Sahuquillo

HPCC DAr 2: Distributed ArchitectureDynamic WCET Estimation for Real-Time Multicore Embedded SystemsSupporting DVFS ........................................................................................................................................27

José Luis March, Salvador Petit, Julio Sahuquillo, Houcine Hassan,and José Duato

A Flexible and Scalable Affinity Lock for the Kernel ...................................................................................34Benlong Zhang, Junbin Kang, Tianyu Wo, Yuda Wang, and Renyu Yang

Remapping NUCA: Improving NUCA Cache's Power Efficiency ................................................................38Hui Wang, Chunrong Lai, Yicong Huang, Shih-Lien Lu, Rui Wang,Zhongzhi Luan, and Depei Qian

An Energy-Efficient Multi-GPU Supercomputer ..........................................................................................42David Rohr, Sebastian Kalcher, Matthias Bach, Abdulqadir A. Alaqeeliy,Hani M. Alzaidy, Dominic Eschweiler, Volker Lindenstruth,Sakhar B. Alkhereyfy, Ahmad Alharthiy, Abdulelah Almubaraky,Ibraheem Alqwaizy, and Riman Bin Suliman

HPCC DAl 1: Distributed AlgorithmsSCADOPT: An Open-Source HPC Framework for Solving PDE ConstrainedOptimization Problems Using AD ...............................................................................................................46

Kim Feldhoff, Martin Flehmig, Ulf Markwardt, Wolfgang E. Nagel, Maria Schütte,and Andrea Walther

Accelerated Solution of Helmholtz Equation with Iterative Krylov Methodson GPU .......................................................................................................................................................54

Abal-Kassim Cheik Ahamed and Frédéric Magoulès

vi

Spectral Domain Decomposition Method for Natural Lighting and MedievalGlass Rendering .........................................................................................................................................62

Guillaume Gbikpi-Benissan, Rémi Cerise, Patrick Callet, and Frédéric Magoulès

A Synchronous Parallel Max-Flow Algorithm for Real-World Networks .....................................................68Guojing Cong

HPCC DAl 2: Distributed AlgorithmsBenefit of Unbalanced Traffic Distribution for Improving Local OptimizationEfficiency in Network-on-Chip .....................................................................................................................76

Weiwei Fu, Mingmin Yuan, Tianzhou Chen, Qingsong Shi, Li Liu, and Minghui Wu

Research on Mahalanobis Distance Algorithm Optimization Based on OpenCL .......................................84Qingchun Xie, Yunquan Zhang, Haipeng Jia, and Yongquan Lu

HSR: Hierarchical Source Routing Model for Network-on-Chip .................................................................92Mingmin Yuan, Weiwei Fu, Tianzhou Chen, and Minghui Wu

HPCC DAl 3: Distributed AlgorithmsAn Exploration on Quantity and Layout of Wireless Nodes for Hybrid WirelessNetwork-on-Chip .......................................................................................................................................100

Mingmin Yuan, Weiwei Fu, Tianzhou Chen, and Minghui Wu

Acceleration of Stereo-Matching on Multi-core CPU and GPU ................................................................108Tian Xu, Paul Cockshott, and Susanne Oehler

A Technique for the Long Term Preservation of Finite Element Meshes .................................................116Peter Iványi

HPCC DAl 4: Distributed AlgorithmsParallel Sub-structuring Methods for Solving Sparse Linear Systems ona Cluster of GPUs .....................................................................................................................................121

Abal-Kassim Cheik Ahamed and Frédéric Magoulès

Fast and Green Computing with Graphics Processing Units for Solving SparseLinear Systems .........................................................................................................................................129

Abal-Kassim Cheik Ahamed, Alban Desmaison, and Frédéric Magoulès

Coupling and Simulation of Fluid-Structure Interaction Problemsfor Automotive Sun-Roof on Graphics Processing Unit ............................................................................137

Liang S. Lai, Choi-Hong Lai, Abal-Kassim Cheik Ahamed, and Frédéric Magoulès

vii

HPCC DAl 5: Distributed AlgorithmsComparison of Xeon Phi and Kepler GPU Performance for Finite ElementNumerical Integration ................................................................................................................................145

Krzysztof Banaś and Filip Kruzel

Efficient Work-Stealing with Blocking Deques ..........................................................................................149Liu Chi, Song Ping, Liu Yi, and Hao Qinfen

Optimizing Cache Locality for Irregular Data Accesses on Many-Core IntelXeon Phi Accelerator Chip ........................................................................................................................153

Nhat-Phuong Tran, Dong Hoon Choi, and Myungho Lee

HPCC DAl 6: Distributed AlgorithmsLU Factorization of Small Matrices: Accelerating Batched DGETRF onthe GPU ....................................................................................................................................................157

Tingxing Dong, Azzam Haidar, Piotr Luszczek, James Austin Harris,Stanimire Tomov, and Jack Dongarra

GPU Acceleration of Newton's Method for Large Systems of PolynomialEquations in Double Double and Quad Double Arithmetic .......................................................................161

Jan Verschelde and Xiangcheng Yu

An Adaptive Task Granularity Based Scheduling for Task-centric Parallelism ........................................165Jianmin Bi, Xiaofei Liao, Yu Zhang, Chencheng Ye, Hai Jin, and Laurence T. Yang

HPCC CCWS 1: Cloud Computing and Web ServicesAn Energy-Efficient VM Placement in Cloud Datacenter ..........................................................................173

Fei Teng, Danting Deng, Lei Yu, and Frédéric Magoulès

Reducing Memory in Software-Based Thread-Level Speculation for JavaScriptVirtual Machine Execution of Web Applications .......................................................................................181

Jan Kasper Martinsen, Håkan Grahn, Anders Isberg, and Henrik Sundström

Algorithms for Balanced Graph Bi-partitioning ..........................................................................................185Jigang Wu, Guiyuan Jiang, Lili Zheng, and Suiping Zhou

Optimizing the Topologies of Virtual Networks for Cloud-Based Big DataProcessing ................................................................................................................................................189

Cong Xu, Jiahai Yang, Hui Yu, Haizhuo Lin, and Hui Zhang

HPCC CCWS 2: Cloud Computing and Web ServicesAccelerating the Massive VMs Booting Up ...............................................................................................197

Dayang Zheng, Hai Jin, Xiaofei Liao, and Yu Zhang

Performance Driven Cloud Resource Provisioning ..................................................................................205Jay Kiruthika and Souheil Khaddaj

viii

The HPS3 Service: Reduction of Cost and Transfer Time for Storing Dataon Clouds ..................................................................................................................................................213

Jorge Veiga, Guillermo L. Taboada, Xoán C. Pardo, and Juan Touriño

Securing Cloud Users at Runtime via a Market Mechanism: A Casefor Federated Identity ................................................................................................................................221

Giannis Tziakouris, Carlos Joseph Mera Gómez, and Rami Bahsoon

HPCC CCWS 3: Cloud Computing and Web ServicesCost-Effective Virtual Machine Image Replication Management for Cloud DataCenters .....................................................................................................................................................229

Dian Shen, Fang Dong, Junxue Zhang, and Junzhou Luo

ZDLC-Based Modelling and Simulation of Enterprise Systems ...............................................................237B. Makoond, A. Elias, S. Ross-Talbot, S. Khaddaj, and S. Franczuk

Virtual Machine Scheduling Considering Both Computing and Cooling Energy ......................................244Xiang Li, Xiaohong Jiang, and Yanzhang He

HPCC CCWS 4: Cloud Computing and Web ServicesCloud Energy Broker: Towards SLA-Driven Green Energy Planning for IaaSProviders ...................................................................................................................................................248

Md Sabbir Hasan, Yousri Kouki, Thomas Ledoux, and Jean Louis Pazat

Enabling Prioritized Cloud I/O Service in Hadoop Distributed File System ..............................................256Tsozen Yeh and Yifeng Sun

Implementation of the KVM Hypervisor on Several Cloud Platforms: Tuningthe Apache CloudStack Agent ..................................................................................................................260

Fernando Gomez Folgar, Antonio Garcia Loureiro, Tomas Fernandez Pena,J. Isaac Zablah, and Natalia Seoane

HPCC CCWS 5: Cloud Computing and Web ServicesHarnessing Memory Page Distribution for Network-Efficient Live Migration ............................................264

Kashifuddin Qazi, Yang Li, and Andrew Sohn

Service Deployment in Cloud ...................................................................................................................268Amel Haji, Asma Ben Letaifa, and Sami Tabbane

MOBBS: A Multi-tiered Block Storage System for Virtual Machines UsingObject-Based Storage ..............................................................................................................................272

Sixiang Ma, Haopeng Chen, Heng Lu, Bin Wei, and Pujiang He

ix

HPCC SEC 1: Scientific and Engineering ComputingImproving the Scalability of a Hurricane Forecast System in Mixed-ParallelEnvironments ............................................................................................................................................276

Thiago Santos Quirino, Javier Delgado, and Xuejin Zhang

CESMTuner: An Auto-tuning Framework for the Community Earth SystemModel ........................................................................................................................................................282

Ding Nan, Xue Wei, Ji Xu, Xu Haoyu, and Song Zhenya

The Virtual Open Page Buffer for Multi-core and Multi-thread Processors ..............................................290Hongwei Zhou, Rangyu Deng, Zefu Dai, Xiaobo Yan, Ying Zhang, and Caixia Sun

HPCC SEC 2: Scientific and Engineering ComputingOn the Performance of the WRF Numerical Model over Complex Terrain ona High Performance Computing Cluster ...................................................................................................298

Nicholas Christakis, Theodoros Katsaounis, George Kossioris,and Michael Plexousakis

Power Consumption Analysis of Parallel Algorithms on GPUs ................................................................304Frédéric Magoulès, Abal-Kassim Cheik Ahamed, Alban Desmaison,Jean-Christophe Léchenet, François Mayer, Haifa Ben Salem, and Thomas Zhu

targetDP: an Abstraction of Lattice Based Parallelism with PortablePerformance .............................................................................................................................................312

Alan Gray and Kevin Stratford

HPCC SEC 3: Scientific and Engineering ComputingCommunication Optimal Least Squares Solver ........................................................................................316

Pawan Kumar

FLLOP: A Massively Parallel Solver Combining FETI Domain DecompositionMethod and Quadratic Programming ........................................................................................................320

Vaclav Hapla, Martin Cermak, Alexandros Markopoulos, and David Horak

Performance Implication of Multicore Cache Locking on General-PurposeProcessors ................................................................................................................................................328

Matthew Loach and Wei Zhang

HPCC SEC 4: Scientific and Engineering ComputingSRFTL: An Adaptive Superblock-Based Real-Time Flash Translation Layerfor NAND Flash Memory ...........................................................................................................................332

Xin Li, Zhaoyan Shen, Lei Ju, and Zhiping Jia

x

Exploiting Hybrid SPM-Cache Architectures to Reduce Energy Consumptionfor Embedded Computing .........................................................................................................................340

Wei Zhang and Lan Wu

Texture-Directed Mobile GPU Power Management for Closed-Source Games .......................................348Beilei Sun, Xi Li, Jiachen Song, Zhinan Cheng, Yuan Xu, and Xuehai Zhou

HPCC DAT 1: Distributed Applications and TechnologiesPredicting Performance of Hybrid Master/Worker Applications UsingModel-Based Regression Trees ...............................................................................................................355

Abel Castellanos, Andreu Moreno, Joan Sorribes, and Tomàs Margalef

Leveraging Hierarchical Data Locality in Parallel Programming Models ..................................................363Ahmad Anbar, Engin Kayraklioglu, Olivier Serres, and Tarek El-Ghazawi

Trajectory Pattern Mining over a Cloud-Based Framework for UrbanComputing ................................................................................................................................................367

Albino Altomare, Eugenio Cesario, Carmela Comito, Fabrizio Marozzo,and Domenico Talia

GPU Maps for the Space of Computation in Triangular Domain Problems ..............................................375Cristobal A. Navarro and Nancy Hitschfeld

HPCC DAT 2: Distributed Applications and TechnologiesLook before You Leap: Using the Right Hardware Resources to AccelerateApplications ..............................................................................................................................................383

Jie Shen, Ana Lucia Varbanescu, and Henk Sips

An Integrated Hardware-Software Approach to Task Graph Management ..............................................392Nina Engelhardt, Tamer Dallou, Ahmed Elhossini, and Ben Juurlink

A Metadata Update Strategy for Large Directories in Wide-Area File Systems .......................................400Guoliang Liu, Zhenjun Liu, Liuying Ma, Shuai Zhang, Jing Huang, and Xiuguo Bao

HPCC DAT 3: Distributed Applications and TechnologiesModelling and Stochastic Simulation of Synthetic Biological Boolean Gates ...........................................404

Daven Sanassy, Harold Fellermann, Natalio Krasnogor, Savas Konur,Laurentiu M. Mierla, Marian Gheorghe, Christophe Ladroue, and Sara Kalvala

High Performance Simulations of Kernel P Systems ................................................................................409Mehmet E. Bakir, Savas Konur, Marian Gheorghe, Ionut Niculescu,and Florentin Ipate

Optimizing GPU Virtualization with Address Mapping and Delayed Submission .....................................413Xiaolin Wang, Hanbing Wang, Yan Sang, Zhenlin Wang, and Yingwei Luo

Buffer on Last Level Cache for CPU and GPGPU Data Sharing .............................................................417Licheng Yu, Tianzhou Chen, Minghui Wu, and Li Liu

xi

HPCC MCN 1: Mobile Computing and NetworkingConflict-Free Opportunistic Centralized Time Slot Assignment in CognitiveRadio Sensor Networks ............................................................................................................................421

Ons Mabrouk, Pascale Minet, Hanen Idoudi, and Leila Saidane

Network Aware and Power-Based Resource Allocation in Mobile Ad HocComputational Grid ...................................................................................................................................428

Sayed Chhattan Shah, Sajjad Hussain Chauhdary, Muhammad Bilal,and Myong-Soon Park

An Inter-frame Correlation Based Error Concealment of Immittance SpectralCoefficients for Mobile Speech and Audio Codecs ...................................................................................436

Yuhong Yang, Shaolong Dong, Ruimin Hu, Yanye Wang, Li Gao,and Maosheng Zhang

HPCC MCN 2: Mobile Computing and NetworkingPerformance Analysis for New Call Bounding Scheme with SFRin LTE-Advanced Networks ......................................................................................................................442

Mahammad A. Safwat, Hesham M. El-Badawy, Ahmad Yehya, and H. El-Motaafy

Adaptive Detection for STBCS in IEEE802.11AC ....................................................................................452Debasish Ghose, Smriti Kana Roy, Hung-Ta Pai, and Chun-Yi Wei

HPCC MCN 3: Mobile Computing and NetworkingOn Delivery Delay-Constrained Throughput and End-to-End Delay in MANETs .....................................456

Yujian Fang, Yuezhi Zhou, Xiaohong Jiang, and Yaoxue Zhang

Source Misrouting in King Topologies ......................................................................................................464E. Stafford, C. Martinez, Jose Luis Bosque, Fernando Vallejo,Cristobal Camarero, Borja Perez, and Ramón Beivide

Avoiding Tree Saturation in the Face of Many Hotspots with Few Buffers ...............................................472Bradley C. Kuszmaul and William H. Kuszmaul

HPCC MCN 4: Mobile Computing and NetworkingSimultaneous Optical Path-Setup for Reconfigurable Photonic Networksin Tiled CMPs ...........................................................................................................................................482

Paolo Grani and Sandro Bartolini

Packet Storage at Multi-gigabit Rates Using Off-the-Shelf Systems ........................................................486Victor Moreno, Pedro M. Santiago Del Río, Javier Ramos,José Luis García-Dorado, Ivan Gonzalez, Francisco J. Gomez-Arribas,and Javier Aracil

xii

SyncSnap: Synchronized Live Memory Snapshots of Virtual MachineNetworks ...................................................................................................................................................490

Bin Shi, Bo Li, Lei Cui, Jieyu Zhao, and Jianxin Li

A Multi-layer Hierarchical Inter-cloud Connectivity Model for Sequential PacketInspection of Tenant Sessions Accessing BI as a Service .......................................................................498

Hussain Al-Aqrabi, Lu Liu, Richard Hill, and Nick Antonopoulos

HPCC SCUC 1: Security, Collaborative and UbiquitousComputingDeveloping Scalable Agents in Blueprint ..................................................................................................506

Alex Muscar

Host-Based Card Emulation: Development, Security, and Ecosystem ImpactAnalysis ....................................................................................................................................................514

Mouhannad Alattar and Mohammed Achemlal

A Pairing-Free Certificateless Authenticated Group Key Agreement Protocol .........................................518Gu Xiaozhuo, Xu Taizhong, Zhou Weihua, and Wang Yongming

HPCC SCUC 2: Security, Collaborative and UbiquitousComputingCGK: A Collaborative Group Key Management Scheme .........................................................................522

Fatma Hendaoui, Hamdi Eltaief, Habib Youssef, and Abdelbasset Trad

A Provisioning Service for Automatic Command Line Applications Deploymentin Computing Clouds ................................................................................................................................526

Evgeny Pyshkin and Andrey Kuznetsov

CGSIL: Collaborative Geo-clustering Search-Based Indoor Localization ................................................530Thong Minh Doan, Han Nguyen Dinh, Nam Tuan Nguyen, and An Truong Pham

IEEE International Conference onEmbedded Softwareand Systems (ICESS 2014)

ICESS 1: Energy Measurement and ManagementCharacterizing Energy Consumption of Real-Time and Media Benchmarkson Hybrid SPM-Caches ............................................................................................................................534

Lan Wu, Yiqiang Ding, and Wei Zhang

Learning Based Power Management for Periodic Real-Time Tasks ........................................................542Fakhruddin Muhammad Mahbub Ul Islam and Man Lin

Energy Consumption Estimation of Software Components Based on ProgramFlowcharts ................................................................................................................................................550

Patrick Heinrich, Hannes Bergler, and Dirk Eilers

xiii

An Operation Scenario Model for Energy Harvesting Embedded Systemsand an Algorithm to Maximize the Operation Quality ...............................................................................554

Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi,and Naofumi Takagi

ICESS 2: Platforms and SystemsModeling Basic Aspects of Cyber-Physical Systems, Part II (ExtendedAbstract) ...................................................................................................................................................558

Yingfu Zeng, Chad Rose, Paul Brauner, Walid Taha, Jawad Masood,Roland Philippsen, Marcia O‘Malley, and Robert Cartwright

An FPGA Based Resources Efficient Solution for the OmniVision Digital VGACameras Family ........................................................................................................................................566

Elmar Yusifli, Reda Yahiaoui, Saeed Mian Qaisar, and Tijani Gharbi

Design and Implementation of Low-Power Location Tracking System Basedon IEEE 802.11 .........................................................................................................................................570

Sanghyun Son, Yongsu Jeon, and Yunju Baek

ICESS 3: Architecture and Systems"CERE": A CachE Recommendation Engine: Efficient Evolutionary CacheHierarchy Design Space Exploration ........................................................................................................574

Gabriel Yessin, Abdel-Hameed A. Badawy, Vikram Narayana, David Mayhew,and Tarek El-Ghazawi

Online Data Allocation for Hybrid Memories on Embedded Tele-healthSystems ....................................................................................................................................................582

Meikang Qiu, Longbin Chen, Yongxin Zhu, Jingtong Hu, and Xiao Qin

Formulating Optimized Storage and Memory Space Specifications for LinuxNetwork Embedded Systems ...................................................................................................................588

Kleomenis Tsiligkos and Apostolos Meliones

ICESS 4: Real-Time SchedulingScheduling Analysis of TDMA-Constrained Tasks: Illustration with SoftwareRadio Protocols ........................................................................................................................................593

Shuai Li, Stéphane Rubini, Frank Singhoff, and Michel Bourdellès

Efficient Online Benefit-Aware Multiprocessor Scheduling Using an OnlineChoice of Approximation Algorithms .........................................................................................................603

Behnaz Sanati and Albert M.K. Cheng

Dynamic Reservation-Based Mixed-Criticality Task Set Scheduling ........................................................611Zheng Li, Shangping Ren, and Gang Quan

xiv

Minimal Schedulability Testing Interval for Real-Time Periodic Taskswith Arbitrary Release Offsets ..................................................................................................................619

Yu Jiang, Qiang Zhou, Xingliang Zou, and Albert M.K. Cheng

ICESS 5: Network ProtocolsVulnerability Analysis of Clock Synchronization Protocol Using Stochastic PetriNet ............................................................................................................................................................623

Shen Jiajun and Feng Dongqin

Contiki80211: An IEEE 802.11 Radio Link Layer for the Contiki OS ........................................................629Ioannis Glaropoulos, Vladimir Vukadinovic, and Stefan Mangold

ICESS 6: Hardware/Software Co-DesignPlanning and Optimization of Resources Deployment: Application to CrisisManagement .............................................................................................................................................633

Jason Mahdjoub and Francis Rousseaux

Monitoring Lick Responses in Animal Behavioral Experiments Using a PSoC ........................................641Qingshan Shan, David Bullock, Christian J. Sumner, and Trevor M. Shackleton

Embedded Face Detection Application Based on Local Binary Patterns .................................................649Laurentiu Acasandrei and Angel Barriga

ICESS 7: Energy-Efficient Scheduling and ResourceAllocationVoltage Island Aware Energy Efficient Scheduling of Real-Time Taskson Multi-core Processors ..........................................................................................................................653

Jun Liu and Jinhua Guo

Energy Efficient Dynamic Core Allocation for Video Decoding in EmbeddedMulticore Architectures .............................................................................................................................661

Rajesh Kumar Pal, Kolin Paul, and Sanjiva Prasad

BATS: An Energy-Efficient Approach to Real-Time Schedulingand Synchronization .................................................................................................................................669

Jun Wu

ICESS 8: System on Chip (SoC) and Multicore SystemsCABSR: Congestion Agent Based Source Routing for Network-on-Chip ................................................677

Mingmin Yuan, Weiwei Fu, Tianzhou Chen, Wei Hu, and Minghui Wu

On Cache-Aware Task Partitioning for Multicore Embedded Real-TimeSystems ....................................................................................................................................................685

Aaron Lindsay and Binoy Ravindran

xv

Task Migration for Energy Saving in Real-Time Multiprocessor Systems ................................................693Gang Zeng, Yutaka Matsubara, Hiroyuki Tomiyama, and Hiroaki Takada

ICESS 9: Embedded OSDeadline-Aware Interrupt Coalescing in Controller Area Network (CAN) .................................................701

Christian Herber, Andre Richter, Thomas Wild, and Andreas Herkersdorf

SmartMig: A Case for Page Migration and Self-Interleaving for On-ChipDistributed Memory Systems ....................................................................................................................709

Weiwei Fu, Mingmin Yuan, Tianzhou Chen, Qingsong Shi, Li Liu, and Minghui Wu

A Temporal Partition-Based Linux CPU Scheduler ..................................................................................713Xingliang Zou, Albert M.K. Cheng, Yu Li, and Yu Jiang

A Novel Fault Diagnosis in Reversible Logic Circuit .................................................................................717Bikromadittya Mondal and Susanta Chakraborty

ICESS 10: Hardware/Software Co-DesignA Locality-Preserving Write Buffer Design for Page-Mapping MultichannelSSDs .........................................................................................................................................................721

Sheng-Min Huang and Li-Pin Chang

The RESCUE Approach - Towards Compositional Hardware/SoftwareCo-verification ...........................................................................................................................................729

Paula Herber

XGRID: A Scalable Many-Core Embedded Processor .............................................................................733Volkan Gunes and Tony Givargis

Advanced DSP Based Narrowband PLC Modem for Smart Grids Applications .......................................737Mohamed Chaker Bali and Chiheb Rebai

ICESS 11: Embedded SecurityA Process for the Detection of Design-Level Hardware Trojans UsingVerification Methods .................................................................................................................................741

Christian Krieg, Michael Rathmair, and Florian Schupfer

An Efficient Admission Control Algorithm for Virtual Sensor Networks ....................................................747Sawand M. Ajmal, Stefano Paris, Zonghua Zhang, and Farid Naït-Abdesselam

Wireless Video Sensor Network Platform and Its Application for Public Safety .......................................755Hyuntae Cho, Yunju Baek, and Chong-Min Kyung

xvi

The 6th International Symposium on Cyberspace Safetyand Security (CSS 2014)

CSS 1: Full Paper TrackUI-Dressing to Detect Phishing .................................................................................................................759

Luigi Lo Iacono, Hoai Viet Nguyen, Tobias Hirsch, Maurice Baiers,and Sebastian Möller

EP2AC: An Efficient Privacy-Preserving Data Access Control Schemefor Data-Oriented Wireless Sensor Networks ...........................................................................................767

Piyi Yang and Tanveer A Zia

Snake: An End-to-End Encrypted Online Social Network ........................................................................775Alessandro Barenghi, Michele Beretta, Alessandro Di Federico, and Gerardo Pelosi

CSS 2Robust Edge Based Image Steganography through Pixel Intensity Adjustment ......................................783

Saiful Islam and Phalguni Gupta

Online Taint Propagation Analysis with Precise Pointer-to Analysisfor Detecting Bugs in Binaries ..................................................................................................................790

Gen Li, Ying Zhang, Shuang-Xi Wang, and Kailu

Data Interception through Broken Concurrency in Kernel Land ...............................................................797Julian L. Rrushi

CSS 3Out-of-Band Authentication Model with Hashcash Brute-Force Prevention .............................................806

George Violaris and Ioanna Dionysiou

A Secure Two-Phase Data Deduplication Scheme ..................................................................................814Pierre Meye, Philippe Raïpin, Frédéric Tronel, and Emmanuelle Anceaume

Bivariate Non-parametric Anomaly Detection ...........................................................................................822Christian Callegari, Stefano Giordano, and Michele Pagano

CSS 4: Short Paper TrackSecurity Mechanisms for a Cooperative Firewall ......................................................................................826

Hammad Kabir, Raimo Kantola, and Jesús Llorente Santos

Virtual Firewall Performance as a Waypoint on a Software Defined OverlayNetwork .....................................................................................................................................................831

Casimer Decusatis and Peter Mueller

xvii

Machine Learning Based Cross-Site Scripting Detection in Online SocialNetwork .....................................................................................................................................................835

Rui Wang, Xiaoqi Jia, Qinlei Li, and Shengzhi Zhang

CSS 5Asynchronous Covert Communication Using BitTorrent Trackers ...........................................................839

Mathieu Cunche, Mohamed-Ali Kaafar, and Roksana Boreli

Cloud Federation? We Are Not Ready Yet ...............................................................................................843Jacques Bou Abdo, Jacques Demerjian, Hakima Chaouchi, Kabalan Barbar,Guy Pujolle, and Talar Atechian

Proof of Retrieval and Ownership Protocols for Images through SPIHTCompression .............................................................................................................................................847

Fatema Rashid, Ali Miri, and Isaac Woungang

Workshops

AHPCN: 6th International Symposium on Advances of HighPerformance Computing and NetworkingOnline Performance Analysis: An Event-Based Workflow Designtowards Exascale ......................................................................................................................................851

Michael Wagner, Tobias Hilbrich, and Holger Brunst

Analysis of Header Usage Patterns of HTTP Request Messages ...........................................................859Maria Carla Calzarossa and Luisa Massari

Comparison of the Predictive Powers of Phenotypes Combinedby Anthropometric Index and Triglyceride for Hypertension Diagnosis Basedon Data Mining ..........................................................................................................................................866

Bum Ju Lee and Jong Yeol Kim

A Speculative Mechanism for Barrier Synchronization .............................................................................870Meng Jinglei, Chen Tianzhou, Pan Ping, Yao Jun, and Wu Minghui

AHPCN 2Extending K-Scope Fortran Source Code Analyzer with Visualizationof Performance Profiling Data and Remote Parsing of Source Code .......................................................878

Masaaki Terai, Peter Bryzgalov, Toshiyuki Maeda, and Kazuo Minami

Task-Based Parallelization of Unstructured Meshes Assembly Using D&CStrategy ....................................................................................................................................................886

Eric Petit, Loïc Thébault, Nathalie Möller, Quang Dinh, and William Jalby

xviii

A Performance Analysis of Long-Term Archiving Techniques .................................................................890Martín Vigil, Christian Weinert, Kjell Braden, Denise Demirel,and Johannes Buchmann

Archi 1: First International Workshop on Computing SystemArchitecturesSimulation of Asynchronous Iterative Algorithms Using SimGrid .............................................................902

Charles-Emile Ramamonjisoa, Lilia Ziane Khodja, David Laiymani,Arnaud Giersch, and Raphaël Couturier

Hybrid Ontology-Based Matching for Distributed Discovery of SWS in P2PSystems ....................................................................................................................................................908

Adel Boukhadra, Karima Benatchba, and Amar Balla

Analyses on Performance of Gromacs in Hybrid MPI+OpenMP+CUDA Cluster .....................................916Ce Li, Wenbo Chen, Yang Zhang, and Qifeng Bai

Archi 2: First International Workshop on Computing SystemArchitecturesOptical Interconnects between Microprocessor and Memories ................................................................924

Daxin Luo, Yaoda Liu, Xiaoying Liu, Bin Zhang, Gang Li, Qi Liao, Qinfen Hao,and Zhulin Wei

Exploiting the Inter-cluster Record Reuse for Stream Processors ...........................................................928Ying Zhang, Gen Li, Caixia Sun, Hongwei Zhou, and Fayuan Wang

Mobile Computers as Scientific Computing Machines ..............................................................................934WA Smit and BM Herbst

ALG&MOD: First International Workshop on Algorithmicand ModelingNew Bounds of a Measure in Information Theory ....................................................................................939

Mihaela-Alexandra Popescu, Oana Slusanschi, Alexandru-Corneliu Olteanu,and Florin Pop

A Semantic Rule-Based Approach Towards Process Mining for PersonalisedAdaptive Learning .....................................................................................................................................941

Kingsley Okoye, Abdel-Rahman H. Tawil, Usman Naeem, Rabih Bashroush,and Elyes Lamine

SignalPU: A Programming Model for DSP Applications on Paralleland Heterogeneous Clusters ....................................................................................................................949

Farouk Mansouri, Sylvain Huet, and Dominique Houzet

xix

App: First International Workshop on HPC ApplicationsHide-as-you-Type: An Approach to Natural Language Steganographythrough Sentence Modification .................................................................................................................957

Charles A. Clarke, Eckhard Pfluegel, and Dimitris Tsaptsinos

Experience Report State-Replication-Based Matching System ...............................................................965Yiqun Ding, Fan Li, Bo Zhou, Wei Li, Xinyu Wang, and Tong Wu

Real-Time Environmental Monitoring for Cloud-Based HydrogeologicalModeling with HydroGeoSphere ...............................................................................................................971

Andrei Lapin, Eryk Schiller, Peter Kropf, Oliver Schilling, Philip Brunner,Almerima Jamakovic-Kapic, Torsten Braun, and Sergio Maffioletti

AMDA 1: First International Workshop on Advancesin Memory and Data AccessEx-Tmem: Extending Transcendent Memory with Non-volatile Memoryfor Virtual Machines ..................................................................................................................................978

Vimalraj Venkatesan, Wei Qingsong, and Y.C. Tay

A Bloom Filter Bank Based Hash Table for High Speed Packet Processing ...........................................986Nicola Bonelli, Christian Callegari, Stefano Giordano, and Gregorio Procissi

A Compiler Translate Directive-Based Language to Optimized CUDA ....................................................994Feng Li, Hong An, Weihao Liang, Xiaoqiang Li, Yichao Cheng, and Xia Jiang

AMDA 2Exploiting the Fine Grain SSD Internal Parallelism for OLTP and ScientificWorkloads ...............................................................................................................................................1002

Soraya Zertal

A Novel Approach for Fair and Secure Resource Allocation in Storage CloudArchitectures Based on DRF Mechanism ...............................................................................................1010

Maha Jebalia, Asma Ben Letaïfa, Mohamed Hamdi, and Sami Tabbane

O&S: First International Workshop on Optimizationand SchedulingCore Affinity Code Block Schedule to Reduce Inter-core Data Synchronizationof SpMT ..................................................................................................................................................1014

John Ye, Songyuan Li, Tianzhou Chen, Minghui Wu, and Li Liu

xx

M2M2 1: 6th International Workshop on Multicoreand Multithreaded Architectures and AlgorithmsFast and Accurate Code Placement of Embedded Software for HybridOn-Chip Memory Architecture ................................................................................................................1020

Zimeng Zhou, Lei Ju, Zhiping Jia, and Xin Li

Dual-Page Mode: Exploring Parallelism in MLC Flash SSDs .................................................................1028Yimo Du, Youtao Zhang, and Nong Xiao

A Dynamically Adaptive Approach for Speculative Loop Execution in SMTArchitectures ...........................................................................................................................................1036

Meirong Li and Yinliang Zhao

M2M2 2Embedded Multicore Processors and SIMD Instructions for Emotional-BasedMobile Robotic Agents ............................................................................................................................1044

Francisco Almenar Pedros, Carlos Domínguez, Juan-Miguel Martínez,Houcine Hassan, and Pedro López

Security Effectiveness and a Hardware Firewall for MPSoCs ................................................................1052Miltos D. Grammatikakis, Kyprianos Papadimitriou, Polydoros Petrakis,Antonis Papagrigoriou, George Kornaros, Ioannis Christoforakis,and Marcello Coppola

Skeleton Paradigm for Developing E-Science Applications on DistributedPlatforms .................................................................................................................................................1060

Mohamed Ben Belgacem and Nabil Abdennadher

WCT 1: First International Workshop on Cloud TechnologiesA Coalitional Game-Theoretic Approach for QoS-Based and Secure DataStorage in Cloud Environment ................................................................................................................1068

Maha Jebalia, Asma Ben Letaïfa, Mohamed Hamdi, and Sami Tabbane

Selective Task Scheduling for Time-Targeted Workflow Execution on Cloud ........................................1075In-Yong Jung and Chang-Sung Jeong

Service Level Agreement (SLA)-Based Resource Management for ImprovingCloud Services ........................................................................................................................................1080

Kaiqi Xiong

Cost-Optimized Resource Provision for Cloud Applications ...................................................................1088Yuxi Shen, Haopeng Chen, Lingxuan Shen, Cheng Mei, and Xing Pu

xxi

WCT 2Trusted Platforms to Secure Mobile Cloud Computing ...........................................................................1096

Samia Bouzefrane and Le Vinh Thinh

Clustering-Based Query Result Authentication for Encrypted Databasesin Cloud ...................................................................................................................................................1104

Miyoung Jang, Min Yoon, Deulnyeok Youn, and Jae-Woo Chang

Cloud Brokerage Model for Resource Pricing and Refund .....................................................................1111Mohammad Aazam and Eui-Nam Huh

Analysis and Detection of DoS Attacks in Cloud Computing by Using QSEAlgorithm .................................................................................................................................................1117

Pallavali Radha Krishna Reddy and Samia Bouzefrane

WCT 3Design and Implementation of a New Load Estimation Strategy in Cloud .............................................1125

Utpal Biswas, Sourav Banerjee, Prateep Bhattacharjee, and Mayukh Dey

A Density-Aware Data Encryption Scheme for Outsourced Databases in CloudComputing ..............................................................................................................................................1129

Min Yoon, Miyoung Jang, Young-Sung Shin, and Jae-Woo Chang

Migrating Scientific Workflows to the Cloud: Through Graph-Partitioning,Scheduling and Peer-to-Peer Data Sharing ...........................................................................................1137

Satish Narayana Srirama and Jaagup Viil

Towards an Easy-to-Use Web Application Server and Cloud PaaS for WebDevelopment Education ..........................................................................................................................1145

Philipp Brune, Michael Leiser, and Erica Janke

GPU: First International Workshop on Graphical ProcessingUnitOn Implementing Sparse Matrix Multi-vector Multiplication on GPUs ....................................................1149

Walid Abu-Sufah and Khalid Ahmad

Flexible Parallelized Empirical Mode Decomposition in CUDA for HilbertHuang Transform ....................................................................................................................................1157

Kevin P.Y. Huang, Charles H.P. Wen, and Herming Chiueh

JolokiaC++: An Annotation Based Compiler Framework for GPGPUs ..................................................1166Vibha Patel, Sanjeev Aggarwal, and Amey Karkare

GPU Accelerated 3D Image Deformation Using Thin-Plate Splines ......................................................1174Weixin Luo, Xuan Yang, Xiaoxiao Nan, and Bingfeng Hu

xxii

WNet 1: Workshop on Wireless Network TechnologiesTwo New Multicast Algorithms in 3D Mesh and Torus Networks ...........................................................1182

Hovhannes A. Harutyunyan and Shegjian Wang

Optimizing a Calibration Software for Radio Astronomy .........................................................................1190Souley Madougou, Ana Lucia Varbanescu, and Rob Van Nieuwpoort

Deterministic Blocker Tag Detection Scheme by Comparing Expectedand Observed Slot Status in UHF RFID Inventory Management Systems ............................................1198

Ryo Hattori, Kentaroh Toyoda, and Iwao Sasase

Improving Vertical Handover over Heterogeneous Technologies Using a CrossLayer Framework ....................................................................................................................................1202

Mariem Thaalbi and Nabil Tabbane

WNet 2Throughput Enhancement in Cooperative Wireless Ad Hoc Networks ..................................................1209

Muhammad Khalil Afzal, Byung-Seo Kim, and Sung Won Kim

Bounding the Worst-Case Execution Time of Static NUCA Caches ......................................................1213Yiqiang Ding and Wei Zhang

Concurrent Moving-Based Connection Restoration Scheme between Actorsto Ensure the Continuous Connectivity in WSANs .................................................................................1217

Yuya Tamura, Takuma Koga, Shinichiro Hara, Kentaroh Toyoda, and Iwao Sasase

PPCSS 1: 6th International Symposium on Cyberspace Safetyand Security WorkshopPrivacy Risks in Publication of Taxi GPS Data .......................................................................................1221

Peipei Sui, Tianyu Wo, Zhangle Wen, and Xianxian Li

Security Evaluation for Cyber Situational Awareness .............................................................................1229Igor Kotenko and Elena Doynikova

PPCSS 2NoteLocker: Simple Secure Storage Service .........................................................................................1237

Petros Zaris and Harald Gjermundrød

Assessing and Managing ICT Risk with Partial Information ...................................................................1245Fabrizio Baiardi, Fabio Corò, Federico Tonelli, Alessandro Bertolini,Roberto Bertolotti, and Daniela Pestonesi

What Private Information Are You Disclosing? A Privacy-Preserving SystemSupervised by Yourself ...........................................................................................................................1253

Alberto Huertas Celdrán, Manuel Gil Pérez, Félix J. García Clemente,and Gregorio Martínez Pérez

xxiii

Efficient Privacy Preserving Multicast DNS Service Discovery ..............................................................1261Daniel Kaiser and Marcel Waldvogel

EMCA: Workshop on Embedded Multi-core Computingand ApplicationsAn Embedded-Based Distributed Private Cloud: Power Quality EventClassification ...........................................................................................................................................1269

Xiang-Yao Zheng, Chia-Pang Chen, and Joe-Air Jiang

Conductor Temperature Estimation Using the Hadoop MapReduce Frameworkfor Smart Grid Applications .....................................................................................................................1275

Sheng-Kai Pan, Chia-Pang Chen, and Joe-Air Jiang

Parallel Subcircuit Extraction Algorithm on GPGPUs .............................................................................1280Che-Lun Hung, Hsiao-Hsi Wang, Chun-Ting Fu, and Chia-Shin Ou

ETD: First International Workshop on HPC-CFDin Energy/Transport DomainsParallel 3D Sweep Kernel with PARSEC ................................................................................................1285

Salli Moustafa, Mathieu Faverge, Laurent Plagne, and Pierre Ramet

Numerical Verification of Large Scale CFD Simulations: One Way to Preparethe Exascale Challenge ..........................................................................................................................1287

Christophe Denis

Task-Based Programming for Seismic Imaging: Preliminary Results ....................................................1291Lionel Boillot, George Bosilca, Emmanuel Agullo, and Henri Calandra

Author Index ..........................................................................................................................................1299

xxiv

A Process for the Detection of Design-LevelHardware Trojans Using Verification Methods

Christian Krieg, Michael Rathmair and Florian SchupferInstitute of Computer Technology

Vienna University of Technology

Vienna, Austria

[email protected], {rathmair|schupfer}@ict.tuwien.ac.at

Abstract—Hardware Trojans have emerged as a serious threatthe past years. Several methods to detect possible hardwareTrojans have been published, most of them aiming at detectionduring post-fabrication tests. Nevertheless, hardware Trojansare more probable to be inserted at design-level, as resourcesrequired to do so are much lower than those at fabrication. Atdesign-level, verification methods have been shown to serve forTrojan detection. In this paper, we propose a design processto utilize verification methods in hardware Trojan detection,being able to be integrated into a state-of-the-art design flowfor embedded systems. We outline the fundamental basics ofverification methods and go then into the details of each step inthe process. We identify assets and attackers, and outline whichmethods are suited to defend against which type of attack.

I. INTRODUCTION

Hardware Trojans have been under intense research in thepast years. They are digital and/or analog/mixed-signal systemsthat serve a shadow purpose besides their specified function-ality. This additional functionality is inserted maliciously, isunspecified and undocumented. In order to remain stealthyduring fabrication and functional tests, hardware Trojans incor-porate an activation mechanism, a so-called trigger. A triggermainly relies on rare occurrence of values and sequences andaims at activation of malicious functionality when the system isalready deployed. [1]–[3] In former threat models, a maliciousmanufacturer is assumed which inserts extra functionalityinto physical designs. Therefore, detection methods focus onhow to detect malicious functionality added this way. Duringfunctional tests, test vectors are applied to the circuit under testwhich take into consideration the activation strategy of a Trojancircuit. This way, specific regions are activated or rare signalsare stimulated to force the activation of malicious circuitry.Concurrently, a side-channel analysis (SCA) is performedto measure the impact of malicious circuitry on parameterssuch as power consumption, leakage currents and timing. Theresults of the SCA are then compared to a simulation modelof the circuit which is assumed Trojan-free, a so-called goldenmodel. If they differ too much, a Trojan is to be suspected. [3]Applying SCA for Trojan detection is a promising method forenvironments where Trojan-free reference models are avail-able. However, the assumption of Trojan absence in suchmodels must be justifiable. In [4], a hardware security lifecycle is presented, which is a good basis for security assurancein hardware systems. However it lacks a specific methodologyto detect design-level hardware Trojans. Register transfer level(RTL) verification is recognized in [5] to detect design-levelTrojans. Logic encryption is identified in [6] to protect various

representations of a design. While this approach is effectivefor outside-attackers, it is inapplicable in detecting design-level Trojans inserted by a malicious designer. Verificationat design-level is fairly used in recent design flows [4], [7].Therefore, in this paper we propose a design process aimingat detecting malicious hardware structures and/or behavior atdesign level, inserted by a malicious designer. Different levelsof abstraction are considered. The proposed design processextensively makes use of formal verification methods in orderto find extra functionality in hardware designs, thus enablingassessment of Trojan absence in golden models.

II. VERIFICATION OF HW-DESIGNS

In contrast to validation, which is used to ensure that thesystem fulfills its intended purpose (“building the right sys-tem”), verification is a method which checks if an implemen-tation of a system corresponds to its specification (“buildingthe system right”) Verification of hardware systems can beeither complete or incomplete. Recent verification methodsimply high computational complexity because of exponentialgrowth of the state space (“state space explosion”). Therefore,simplifications are performed in order to reduce complexity(design partitioning) and to assess the number of states thatare subject to a verification process (reachability analysis).To the simplified design, simulative and formal verificationmethods can be applied. Simulative verification methods workon the principle of falsification and check for presence of errors(instead of absence). They are applicable to entire systems,as implementation details are neglected. Therefore, errors thathave been identified are relative to the degree of abstraction.Due to computational complexity, formal verification methodsare applicable only to subsystems. Formal verification methodswork on the principle of (mathematical) proof to show theabsence of errors in an abstraction of the design. Formalmethods are complete relative to both the specification andthe abstraction. [8]

A. Design Partitioning

Design partitioning is used to reduce complexity of a givendesign in order to enable formal verification. A system isdivided into functional subparts which are separately verified(fig. 1). If all subparts pass verification, and all interconnec-tions among all subparts pass verification too, then a systemcan as a whole be seen as verified. One approach to partitiona given design in less complex subparts is to determine thecones of all latches and primary outputs as shown in [9].

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DesignPartitioning

SpecificationPartitions

Figure 1: Design Partitioning.

These cones can be treated as partitions of the design. Basedon the structural overlapping of the fan-in cones, latches canbe further partitioned by grouping uncorrelated latches [10].

B. Reachability Analysis

Reachability analysis is a search problem in a directedsystem state graph. The result of a reachability analysis isa set of target states satisfied by starting at the initial stateand reached by repeatedly applying valid state transitions [11].Reachability requirements are specified in order to constrainthe reachability of states, such as “A state must be reachable”.If states do not satisfy these constraints, they are suspect toimplement Trojan behavior. With reachability analysis, statescan be identified which are hard or unable to reach perspecification. Such states can indicate a possible Trojan statewhich is entered after a trigger event occurred (fig. 2). [12]

C. Structural Checking

Structural checking operates at low levels of abstraction,i.e., gate or transistor level. A netlist at the respective levelis analyzed such that all connections between signals areidentified [13]. Structural constraints are defined in a waythat restrict interconnections between signals (e.g., “only twobranches are allowed from a signal”, “a signal must notconnect partition 1 with partition 2”, etc.). The concept ofstructural checking is depicted in fig. 3. This way, modifica-tions of netlists can be detected. Structural checking is closelyrelated to design rule checking [12].

D. Equivalence Checking

Equivalence Checking is used to verify if an implementa-tion is functionally equal to its specification. In this context,the term specification refers to a representation of the design ata higher level of abstraction (e.g., RTL), which by a synthesisprocess is mapped to a representation at a lower level ofabstraction (e.g., gate level), the implementation. Therefore,equivalence checking aims at the correct implementation of aspecification, or, the correct translation of a representation froma higher level of abstraction to a lower level of abstraction. Toprove functional equivalence, both the specification and theimplementation are translated into a reduced, ordered binary

ModelTrans-

formation

ImplementationM

ReachabilityConstraints

PropertyGeneration

Properties

p1, p2, ..., pn

?

|=yes/no

Figure 2: Reachability Analysis.

NetlistAnalysis

&

&

&

&

ImplementationsigA sigB

in1 out2in1 out3in2 out1. . . . . .

StructuralConstraints

PropertyGeneration

Properties

p1, p2, ..., pn

?

|=yes/no

Figure 3: Structural Checking.

decision diagram (ROBDD) representation. The ROBDD rep-resents a canonical form, which is a unique representation ofthe functionality for a fixed variable order. Both ROBDDs arethen checked for equivalence (fig. 4). Besides ROBDD-basedequivalence checking, also satisfiability (SAT)-based equiva-lence checking is used due to good scalability properties. [14]Equivalence Checking can be applied to identify modifica-tions during synthesis or modifications of the implementation.Therefore, the risk of malicious synthesis tools or intrudersthat compromise the implementation can be mitigated.

E. Model Checking

Model checking is used to check specifications if theysatisfy a given set of properties. Formally, model checkingalgorithms operate on a finite transition representation (M ) ofa hardware function and check whether a property (p) holdson this model (M |= p) [15], [16]. Properties are formulatedin propositional temporal logic (PTL), which are expressionschecked on a path of the model (path formulas) or satisfiedin a single state (state formulas). Model checking can beapplied to identify if an implementation incorporates maliciousbehavior. Malicious behavior is defined by Trojan properties,which means that for any possible scenario a property has tobe defined, which then is checked against the model (fig. 5).

F. Threat Model

For our design process we assume a malicious designer,which adds extra functionality to the RTL design of a system.The added functionality is not specified and not documented,and serves a shadow purpose. We therefore call it maliciousfunctionality. Malicious functionality can be either structuralor behavioral. In order to detect malicious functionality, theRTL description of the design has to be fully available, aswhite-box verification is performed. In our approach, third-party intellectual property cores (3PIPs) are verifiable only ifthey are available as RTL description. Therefore, we assume

Synthesis

Specification Implementation

?≡

yes/no

Figure 4: Equivalence Checking.

742742742742

ModelTrans-

formation

ImplementationM

TestSpecification

PropertyGeneration

Properties

p1, p2, ..., pn

?

|=yes/no

Figure 5: Model Checking.

a security policy which restricts the use of 3PIPs to RTL.Also, we assume a specification to be trustworthy, i.e., it iscarefully checked against the security policy of the designhouse. A compromised specification can not be identified byverification. Instead, a specification is assumed to undergothorough validation.

III. VERIFICATION PROCESS

In this section, we describe a state-of-the-art approach tosystem specification and implementation and how testing andverification is embedded into this process. We identify possibleattack vectors and investigate how verification methods canhelp in detecting and preventing the inclusion of maliciousstructures and behavior. Figure 6 illustrates this process, high-lighting which method is utilized in which step of the process.The figure shows which step of the process is performedwhen, by whom, and visualizes the inputs and outputs for eachsubprocess. With the help of a simple example we illustrate theverification process in order to show the applicability of ourapproach. A simple universal synchronous receiver/transmitter(UART) transmission unit is to be designed, which sends dataover a serial interface.

A. System Specification

The system specification is created on the basis of require-ments and includes a precise description of the system behav-ior, as well as properties that are required from the systemimplementation [8]. Behavior is described in an (executable)behavioral model, whereas the properties that are requiredfrom the implementation are specified in the test specification(see section III-B). As an example, the transmission unit of aUART is to be designed. The function of a UART transmissionunit is to bitwisely send the contents of a register over atransmission line. In order to keep complexity low, we reducethe functionality of the transmitter to demonstrate the designprocess. The informal specification of the UART transmissionunit is as follows: “The transmission unit reads a data register,and sends each data bit over a single transmission line. A loadsignal indicates that the data in the data register are valid. A txsignal indicates that the transmission line is ready. A snt signalindicates that the last bit was sent.” It is inherent to informalspecifications that these are ambiguous, incomplete and poorlystructured which complicates verification [8]. Therefore, weformalize the specification using a finite state machine (FSM),which is depicted in fig. 7a. The formal specification of theUART transmission unit (fig. 7a) provides an exact descriptionof the system behavior. Although implementation details havenot been anticipated, design decisions already have been madein determining the system states and signals that influencetransitions in the FSM.

idle

stop

shift

load

ld

ld

txtx

txsnt

txsnt

txtx

(a) Formal

“The transmission unit reads a data regis-ter, and sends each data bit over a singletransmission line. A load signal indicatesthat the data in the data register are valid.A tx signal indicates that the transmissionline is ready. An snt signal indicates thatthe last bit was sent.”

(b) Informal

Figure 7: System specification of the example UART.

B. Test Specification

On the basis of the system specification, the test specifica-tion is created which takes into account requirements regardingthe implementation of the system. These can be functionalor non-functional requirements. In our case, we describefunctional requirements that specify malicious behavior whichis not desirable and therefore constrains the implementation.Malicious behavior is derived from the security policy of thedesign house, as well as of known or potential attacks tohardware/software system designs. Based on a known potentialattack where extra states are added during implementation [17],we specify for the UART transmitter unit the only legitimatetransitions. This is possible because a formal specification is athand. Figure 8 shows the property specifications in linear timelogic (LTL). The properties shown in fig. 8 describe the validtransitions of the FSM which specifies the UART transmissionunit. All transitions deviating from this behavior are detectedduring verification (or, more precisely, during model checking),indicating possible Trojan behavior.

C. System Implementation

The system is implemented based on the system spec-ification. In this step, potentially malicious structures andbehavior can be inserted by a malicious designer. The re-sulting document is a description of the system at arbitrarylevels of abstraction which reach from RTL to physical. Thesubprocess of implementation incorporates several steps ofsynthesis, where each step maps a representation of the designto a lower level of abstraction. In this context, we call therepresentation at the higher level of abstraction a specification,and the representation at the lower level of abstraction animplementation. Thus, a single representation of the designcan be both a specification and an implementation. It onlydepends on the context in which the representation is treated.If we explicitly want to refer to the specification in which thesystem behavior is specified, we call it system specification(cf. section III-A). In our threat model (cf. section II-F) weassume a malicious designer (or, in this context: a maliciousimplementer). The malicious designer adds extra functionalityto the UART transmission unit, which enables it to covertly

1 G ( ( s t a t e = i d l e ) −> X ( s t a t e = i d l e | s t a t e = l o a d ) )2 G ( ( s t a t e = l o a d ) −> X ( s t a t e = l o a d | s t a t e = s h i f t ) )3 G ( ( s t a t e = s h i f t ) −> X ( s t a t e = s h i f t | s t a t e = s t o p ) )4 G ( ( s t a t e = s t o p ) −> X ( s t a t e = s t o p | s t a t e = i d l e ) )

Figure 8: Specification of properties that constrain the system with regard tomalicious behavior. Legitimate transitions of the FSM are specified.

743743743743

CorrectedSpecification

• Behavioral Constraints• Reachability Constraints• Structural Constraints

• Design Partitioning• Model Transformation• Reachability Analysis• Property Generation

• Structural Checking• Equivalence Checking• Model Checking

• Structural Evaluation• Equivalence Evaluation• Property Evaluation

System Architect Implementer Verification Engineer

The function of thesystem is specified

SystemSpecification

1

System tests andverifications arespecified

TestSpecification

2

The specificationis implemented

SystemDesign(RTL)

3

Tests areplanned

Test Plan

4

Tests areperformed

TestDocumentation

(golden reference)

5

Results areevluated

TestEvaluation

Documentation

6Errors

The specificationis corrected

7

The implemen-tation is corrected

8

CorrectedImplementation

Figure 6: Process of Testing and Verification.1

idle

stop

shift

load

ld

ld

txtx

txsnt

txsnt

txtx

tload

tshift

t

u

t

(a) FSM

case stNext iswhen st_idle =>if t = ’1’thenstNext <= st_tload;

elsestNext <= st_idle;

end if;when tload =>if u = ’1’ thenstNext <= tshift;

when tshift =>if t = ’0’ thenstNext <= st_idle;

end if;end case;

(b) VHDL

Figure 9: Implementation of the example UART, incorporating extra function-ality added by a malicious designer. Extra states are drawn thick, dashed red(or gray) lines. Extra code is printed in red (or gray).

transmit data when the original UART is in its idle state.Figure 9a shows the compromised design as an FSM represen-

tation. Two states are added in order to covertly transmit dataover the UART. In fig. 9b, illustrative VHDL code is listed,which shows the mechanism for entering the extra states. Codewhich implements data transmission is deliberately omitted infavor of understanding.

D. Test Planning

With the system specification, implementation and testspecification at hand, tests and verifications are planned forthe entire design. This step incorporates reasonably partitioningthe design into useful subparts and transforming descriptions(or, models) to appropriate representations (e.g., from an FSMto a ROBDD representation). In order to assess the statesthat are subject to verification, reachability analysis is carriedout for subparts that result from design partitioning. Also, theproperties that are specified in the test specification (see sec-tion III-B) and constrain the implementation with regard toTrojan behavior, are mapped to the design. The complexityof our example design of the UART transmission unit isfairly low, which is why we relinquish design partitioning

1Stickman taken from openclipart.org, authored by BleonaFoniqi

744744744744

and reachability analysis. Therefore, the properties specifiedin section III-B are directly mapped to the implementeddesign, as listed in fig. 10. For our case study, we use thenew symbolic model verifier (NuSMV) tool [18] for modelchecking. Therefore, the properties listed in fig. 10 follow thesyntax of the NuSMV language. In order to verify if the modelof the system implementation satisfies these properties, also thesystem implementation has to be transformed into the NuSMVlanguage. There are methods to automatically perform modeltransformation [19], [20]. However, there is no tool available,wherefore we manually transform the implementation intoNuSMV. The result of the model transformation is listed infig. 11.

E. Verification and Testing

Having accomplished the preparing tasks, it is now time toperform the tests and verifications. For the purpose of detectingTrojan functionality that has been inserted at different steps inthe design flow, the following verification methods are appliedto the implementation. In order to prove if the implementationis functionally equivalent to the specification, an equivalencecheck is performed. This should reveal compromised synthesistools or alterations of a synthesized design. Model check-ing is used to check if potential Trojan behavior has beenadded to the design. Properties that have been generated inthe test planning phase of the process and describe Trojanbehavior are checked against the ROBDD-representation ofthe system model. If Trojan behavior is detected in the design,a counterexample is generated by the model checking tool,which highlights the location of possible malicious inclusions.Model checking aims at revealing malicious components thathave been inserted by malicious designers. To check if theimplementation was altered at a low level of abstraction (e.g.,gate or transistor level), it is submitted to structural checking.In structural checking, the interconnections between signalsare checked against structural constraints that are specified inthe test specification (see section III-D). The results of eachverification are stored in the test documentation.

Our attack scenario assumes a malicious designer whichadds extra states into the FSM representation of the exampleUART transmission module. For demonstration purposes, weperform model checking in order to verify if the model ofthe implementation satisfies the behavioral constraints thathave been specified in the test specification (cf. section III-B).As expected, the NuSMV model checker produces a counterexample because the implementation does not correspond to itsspecification. Figure 12 lists the output of the NuSMV modelchecking tool. Lines 10 to 12 of fig. 12 reveal that the model

1 LTLSPEC G ( (state = st_idle) ->2 X ( state = st_idle | state = st_load) )3 LTLSPEC G ( (state = st_load) ->4 X ( state = st_load | state = st_shift) )5 LTLSPEC G ( (state = st_shift) ->6 X ( state = st_shift | state = st_stop) )7 LTLSPEC G ( (state = st_stop) ->8 X ( state = st_stop | state = st_idle) )

Figure 10: Test Planning. The system properties are mapped to the implemen-tation (state and signal names) and to the tool chain that is used for verification(syntax).

1 MODULE main2 VAR3 uart_tx: mod_uart_tx;456 MODULE mod_uart_tx7 VAR8 state: {st_idle, st_load, st_shift,9 st_stop, tload, tshift};

10 ld: boolean;11 tx: boolean;12 snt: boolean;13 t: boolean;14 u: boolean;1516 ASSIGN17 init(state) := st_idle;18 init(ld) := FALSE;19 init(tx) := FALSE;20 init(snt) := FALSE;21 init(t) := FALSE;22 init(u) := FALSE;2324 next(state) :=25 case26 state = st_idle & ld : st_load;27 state = st_idle & !ld & !t : st_idle;28 state = st_idle & !ld & t : tload;29 state = st_idle & !ld & !t : st_idle;30 state = st_load & tx : st_shift;31 state = st_load & !tx : st_load;32 state = st_shift & tx & snt : st_stop;33 state = st_shift & tx & !snt : st_shift;34 state = st_stop & tx : st_idle;35 state = st_stop & !tx : st_stop;36 state = tload & u: tshift;37 state = tshift & !t: st_idle;38 TRUE: state;39 esac;4041 LTLSPEC G ( (state = st_load) ->42 X (state = st_load | state = st_shift));43 LTLSPEC G ( (state = st_shift) ->44 X (state = st_shift | state = st_stop));45 LTLSPEC G ( (state = st_stop) ->46 X (state = st_stop | state = st_idle));47 LTLSPEC G ( (state = st_idle) ->48 X (state = st_idle | state = st_load));

Figure 11: Test Planning. The system implementation is transformed to theinput language of the NuSMV model checking tool. This working examplealso includes the system properties from fig. 10.

of the implementation does not behave as it is specified. Asa proof, a counterexample is generated as shown in lines 15to 30. It is shown in line 28 that the specification is violatedwhen the (unspecified and maliciously added) state tload isentered.

F. Evaluation and Correction

The test documentation is handed over to the verificationengineer. For every incident which has been reported, the ver-ification engineer locates the cause for the incident and furtherinvestigates reasons for failing verification. Any incident canbe traced back to either a specification or implementation error.The verification engineer tracks each incident back to its rootcause, and documents it in the test evaluation documentation.The evaluation documentation is committed to both the systemarchitect and the implementer, which subsequently remove thediscrepancies detected during verification by correcting thedesign and/or the specification. The corrected versions of thespecification and the implementation again are submitted toverification, and subsequently evaluated. This is an iterative

745745745745

1 -- specification G (state = st_load ->2 X (state = st_load | state = st_shift))3 IN uart_tx is true4 -- specification G (state = st_shift ->5 X (state = st_shift | state = st_stop))6 IN uart_tx is true7 -- specification G (state = st_stop ->8 X (state = st_stop | state = st_idle))9 IN uart_tx is true

10 -- specification G (state = st_idle ->11 X (state = st_idle | state = st_load))12 IN uart_tx is false13 -- as demonstrated by the following execution14 sequence15 Trace Description: LTL Counterexample16 Trace Type: Counterexample17 -> State: 1.1 <-18 uart_tx.state = st_idle19 uart_tx.ld = FALSE20 uart_tx.tx = FALSE21 uart_tx.snt = FALSE22 uart_tx.t = FALSE23 uart_tx.u = FALSE24 -> State: 1.2 <-25 uart_tx.t = TRUE26 -- Loop starts here27 -> State: 1.3 <-28 uart_tx.state = tload29 uart_tx.t = FALSE30 -> State: 1.4 <-

Figure 12: Verification. The output of the NuSMV model checker shows thatthe implementation does not behave as specified.

process which lasts as long as no more failures arise. Whenthis is the case, the test documentation (which contains theerror-free version of the implementation) is also referred toas golden reference. In our example, the verification engineeruses the information listed in fig. 12 to trace back the error. Inour example, she traces it back to the implementation of theUART transmission unit, appropriately classifies the error inthe test evaluation documentation which is then handed overboth to the system architect and the implementer.

IV. CONCLUSIONS

In this paper, we have shown how verification methodscan be applied for detecting and locating hardware Trojansat design level. We pointed out methods for different attackvectors and demonstrated how maliciously added function-ality can be identified with model checking techniques. Inorder to improve the robustness of the verification flow, theimplementer shall not have access to the test specification.Otherwise, the implementer will be able to obfuscate maliciousfunctionality such that a subsequent verification will not beable to detect it. The implementer is intended to removemalicious functionality entirely from the design. However,trust cannot be assumed, but has to be enforced by rigorouslyverifying that the system behaves non-maliciously.

ACKNOWLEDGMENT

This work has been supported by the Austrian researchfunding association (FFG) FIT-IT program under contract no.835922.

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