1654 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 57, NO. …sirenko/PapersNJIT/05485169.pdf · 1654...

1654 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 57, NO. 3, JUNE 2010

ASIC for SDD-Based X-Ray SpectrometersGianluigi De Geronimo, Pavel Rehak, Kim Ackley, Gabriella Carini, Wei Chen, Jack Fried, Jeffrey Keister,

Shaorui Li, Zheng Li, Donald A. Pinelli, D. Peter Siddons, Emerson Vernon, Jessica A. Gaskin,Brian D. Ramsey, and Trevor A. Tyson

Abstract—We present an application-specific integrated circuit(ASIC) for high-resolution x-ray spectrometers (XRS). The ASICreads out signals from pixelated silicon drift detectors (SDDs).The pixel does not have an integrated field effect transistor (FET);rather, readout is accomplished by wire-bonding the anodes tothe inputs of the ASIC. The ASIC dissipates 32 mW, and offers16 channels of low-noise charge amplification, high-order shapingwith baseline stabilization, discrimination, a novel pile-up rejector,and peak detection with an analog memory. The readout is sparseand based on custom low-power tristatable low-voltage differentialsignaling (LPT-LVDS). A unit of 64 SDD pixels, read out by fourASICs, covers an area of 12.8 �� and dissipates with the sensorbiased about 15 ��

�. As a tile-based system, the 64-pixelunits cover a large detection area. Our preliminary measurementsat �� show a FWHM of 145 eV at the 5.9 keV peak of a ��

��

source, and less than 80 eV on a test-pulse line at 200 eV.

Index Terms—ASIC, charge sharing, high rate, LVDS, PUR,SDD.

I. INTRODUCTION

T HE work discussed here is part of a joint effort betweenthe Marshall Space Flight Center and Brookhaven Na-

tional Laboratory to develop a prototype high-resolution x-rayspectrometer (XRS) for measuring the abundances of light ele-ments fluoresced by ambient radiation. The intended use of theXRS is for elemental mapping of planets surfaces during spaceexplorations [1]. We are developing two versions: the first, witha large sensitive area, is suitable for orbit around the moon [2],[3]; the second, a more radiation-resistant, high-rate version, toserve in extreme environments, such as that of Jupiter and Eu-ropa [4]. The first version requires a detection area of 500and an energy resolution better than 100 eV at 280 eV, witha power budget of 20 . The second version has sim-ilar energy-resolution requirements, but must sustain high rates(up to 1 ) with a more relaxed power budget, and

Manuscript received November 13, 2009; revised January 28, 2010; acceptedFebruary 23, 2010. Date of current version June 16, 2010.

G. De Geronimo, P. Rehak, K. Ackley, G. Carini, W. Chen, J. Fried,J. Keister, S. Li, Z. Li, D. A. Pinelli, D. P. Siddons, and E. Vernon arewith the Brookhaven National Laboratory, Upton, NY 11973 USA (e-mail:[email protected]; [email protected]; [email protected]; [email protected];[email protected]; [email protected]; [email protected]; [email protected];[email protected]; [email protected]; [email protected]; [email protected]).

J. A. Gaskin and B. D. Ramsey are with the Marshall Space FlightCenter, Huntsville, AL 35805 USA (e-mail: [email protected];[email protected]).

T. A. Tyson is with the New Jersey Institute of Technology, Newark, NJ 07102USA (e-mail: [email protected])

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TNS.2010.2044809

an order-of-magnitude lower detection area. Detector cooling,not encompassed in the power budget, is assured for operationsdown to .

The stringent requirements on the detector area, resolution,rate, and power suggest either using standard silicon diodeswith high pixelation (a pixel area of few hundred ) andbump-bonded front-end electronics, or employing silicon driftdetectors (SDDs) [5], [6] with moderate pixelation (a pixel areaof few tens of ) and wire-bonded front-end electronics. Asdiscussed in [7], the latter was adopted since more attractive interms of resolution, interconnects, and charge sharing.

Other research groups reported promising results in terms ofrate and resolution with pixelated SDDs with the input transistor(e.g., junction field effect transistor, JFET) integrated with eachpixel [8]–[13]. However, integrating the FET imposes an addi-tional technological challenge, might impose a lower limit in thepower dissipation (some mW in the JFET itself), and requiressomewhat higher complexity in the front-end electronics and in-terconnects to achieve the required stability, especially at highcount rates [14]–[20].

In our SDD the drift field in the pixel is provided by the elec-trode structures on the pixelated side of the detector, oppositeto the entrance side. The largest area of the pixel is covered bya spiral of implanted rectified junction. The current flowing inthe rectifying implant of the spiral generates a field very closeto the optimal drift field described in [21]. Spirals with severaldifferent pitches were tested in the previous version of the spiralSDDs. The current design is based on the maximal number ofturns of the spiral [22]. This design leads the spiral with thehighest electric resistance and the lowest power dissipation. Anoptimized entrance window covers the energy range down to282 eV, corresponding to the Carbon spectral line [23], [24].The area of each pixel is 20 , and the power dissipated bythe rectifying spiral is about 1 mW. The 100 anode, char-acterized by a capacitance of few tens of fF, is located at thecenter of the pixel, and is directly wire-bonded to the input ofa low-noise Application Specific Integrated Circuit (ASIC) fab-ricated in a commercial 0.25 CMOS technology. The SDDsensors tested here were fabricated at KETEK, GmbH.

We recently reported our first prototype XRS based on a14-pixel array and a 14-channel ASIC [7]. That prototypeachieved a resolution of 172 eV FWHM at the 6 keVline, covering an area of 2.24 with a dissipation of 23

. We present here a new XRS prototype comprising64 pixels connected to four 16-channel ASICs. In Section II wepresent our 64-pixel XRS prototype. In Section III we introducea more recent version designed for high rate operation, whichimplements our novel pile-up rejector.

0018-9499/$26.00 © 2010 IEEE

DE GERONIMO et al.: ASIC FOR SDD-BASED X-RAY SPECTROMETERS 1655

Fig. 1. (a) Layout of a unit of 64 20�� SDD pixels, covering an area of 12.8�� ; and, (b) photo of the interposer with one of the four ASICs mounted. EachASICs, sited at a 30 degree angle, reads out an array of 4� 4 pixels (red line).The holes for wire-bonding the ASIC inputs to the SDD anodes are shown.

Fig. 2. (a) Molybdenum masks for the 16- and 64-pixel versions, and, (b) maskmounted on a 16-pixel version used in some measurements reported here.

II. 64-PIXEL XRS PROTOTYPE

In this section, we introduce our 64-pixel XRS prototype, dis-cuss the ASIC and interconnect architectures, and present someexperimental results.

A. Architecture

Fig. 1(a) shows the layout of a SDD unit, composed of 64hexagonal pixels, each 20 in area. The central anodes ofeach of the four groups of 16 pixels are wire-bonded to the 16inputs of one of four ASICs though holes in an interposer (seeFigs. 1(b) and 13). The interposer also provides wire bond padsfor the remaining interconnections for biasing, configuring, andreading out the ASIC, and for biasing the sensor. The SDD unit,covering an area of 12.8 , dissipates less than 15(10 from the electronics, the rest from the sensor),and is designed to be tiled over a large area.

Fig. 2 depicts the molybdenum mask we sited at the entranceside of the sensor, opposite to the pixelated side. Its purposeis to prevent ionizing radiation from reaching the sensor alongthe edges of the pixels, thus reducing charge sharing betweenpixels, and consequently, increasing the peak-to-backgroundratio. The thickness and the width between pixels of the molyb-denum mask are 125 and 240 respectively.

Fig. 3 is a block diagram of the ASIC. It has 16 front-endchannels, multiplexers, common bias-circuitry, registers,DACs, control and readout logic, and a temperature sensor.Each channel has a MOS-only [7] dual-stage charge amplifier

Fig. 3. Block diagram of the 16-channel ASIC.

with adaptive reset [25] providing a charge gain 1551 or 775.5.The amplifier input MOSFET operates with a drain current of200 and it is optimized for an input capacitance of 200 fF[26]. The charge amplifier is followed by a 5th order shaper(SA) [27] with adjustable peaking time (0.5-, 1-, 2-, 4- ), andthe output baseline is stabilized with a band-gap-referencedBaseline Holder (BLH) circuit [28]. The overall voltage/chargegain is adjustable to 2.6 and 5.2 V/fC.

A low-hysteresis comparator with multiple-firing suppression[29] discriminates events, with a threshold controlled by a 10-bitDAC common to all channels, and a 3-bit DAC in each channelfor equalization. The above-threshold events are processed bya multi-phase peak detector (PD) with an analog memory [29],[30]. A flag (FLG), released after a first peak is found, indicatesthat one (or more) successful acquisition is ready to be read out.At each clock (CLK) the peak amplitude (PDO) and the address(ADR) of all the events above threshold are made sequentiallyavailable at the dedicated outputs, thus providing sparsification.The ASICs can be read out per column with an automatic token-passing scheme, similar to the one we described in [31], andwith a edge-based digital signal for chip selection.

Each channel also implements a pixel leakage current mea-surement circuit. The leakage current, multiplied by the gain ofthe charge amplifier, is absorbed by the BLH to maintain theoutput baseline at a constant voltage. A current source, con-trolled by the BLH and proportional to the leakage current, isconverted into a voltage and it is made available by multiplexingthrough the analog monitor. The gain of this leakage currentmeasurement circuit is about 1 mV/pA. A temperature sensor isalso integrated with a gain of about 5.5 .

For the digital interface, we developed a custom, low-power,tristatable low-voltage differential signaling (LPT-LVDS)wherein the output requires a 2 termination and a drivingcurrent of 150 , and which dissipates 700 and 200

, respectively, in the transmitter and receiver. The settlingtime is 10 ns with a 10 pF capacitive load. Fig. 4(a) shows thenon-tristatable case, while Fig. 4(b) shows the tristatable one,used for the flag (FLG) signal, which several chips can share.With an area of 2.2 4.7 the ASIC dissipates 32 mW(1.7 mW/channel plus 5 mW for shared circuits).

B. Experimental Results

Whilst our original XRS prototype gave encouraging results[7], we identified two issues. First, the gain was about 20% lower


Fig. 4. Low-power differential transmitters: (a) driven, and, (b) tristatable withpull-down resistors. Each transmitter, when active, dissipates 700 �� to drivethe 2 �� off-chip resistor.

Fig. 5. Equivalent Noise Charge (ENC) versus peaking time measured for dif-ferent channels with input floating and connected to the SDD pixel anodes. Thesimulated ENC and its contributions, assuming no sensor and a leakage currentof 1 pA, are also shown.

than the design value, due to parasitic capacitance between theinput node and the internal gain node of the front-end amplifier,so affecting pole-zero cancellation, and eventually, the resolu-tion of the front-end at high rate. Second, the stability of the peakdetection [32] and its noise contribution were of concern; bothaffected the resolution of the system and its ability to discrimi-nate low amplitudes. These issues were resolved in the presentXRS prototype. A third minor issue was more recently found,consisting of a small decrease in gain at low temperature. Thedecrease is due to the compression of the gate-source voltageof the MOSFETs used as feedback capacitors (see [7, Fig. 7]),which reduces the charge amplifier loop gain. This issue hasbeen addressed in a further ASIC revision, now being fabricated.

Fig. 5 shows the Equivalent Noise Charge (ENC) measuredat on some channels with the input floating andconnected to the anode of the biased SDD pixel. Fig. 6(a) ex-plains the difference between the two floating channels 14 and8, due to the on-chip parasitic capacitance from the intercon-nection line between the input of the channel and its bondingpad. A difference of about 100 fF was extracted, correspondingto about 10 fF/100 . Fig. 6(b) explains the difference be-tween channels 14 and 4 when connected to the SDD anodes,due to the parasitic capacitance of the wire bond. An increaseof about 80fF was extracted, corresponding to about 10 fF/mm.

Fig. 6. Details of the layout illustrating (a) the on-chip interconnection betweenthe input of the channel and its bonding pad (lines in red for two extreme cases),and, (b) the wire bond interconnection between the ASIC bonding pads and theSDD anodes for different pixels (lines in red).

The side channels (channel 6 plotted in Fig. 5, plus channels 7,16, 15, and 2, 1, 10, 11, as in Fig. 6(b)) exhibited considerablepick-up from the noise on the LVDS lines connected directly toour DAQ integrated in the computer; pick-up was present alsowhen the LVDS signals were inactive. The coupling was be-tween the input wire bonds and portions of the digital tracesflowing either below them or close to the holes (see Figs. 1(b)and 13). In the latter case, the coupling also was through linesrouted in an inner layer of the interposer.

Fig. 7 plots the ENC against the injected charge measuredusing the internal pulse generator and test capacitorwith the input connected to the SDD anode. The inset depictsthe corresponding spectral lines. The progressive increase withinput charge of up to 8 at 2,700 is caused bythe discharge process in the feedback MOSFET of the chargeamplifier [25]. The test capacitor contributes to the ENC withabout 2.5 , and the pulse generator with about 3.5 .This gives an electronic resolution of about 10 at 1peaking time, in line with the results shown in Fig. 5.

Fig. 8 plots the spectrum measured at a peaking time of 1and a rate of about 1 kcps, and compares it to one acquired by

routing the analog monitor to a commercial Multichannel Ana-lyzer (MCA). A FWHM of about 153 eV was measured at the5.9 keV spectral line, which corresponds to an electronicresolution (once subtracted statistics with Fano) of about 11.5

at the 0.26 fC ( , 630 ) input charge. Assuminga contribution from the discharge of the feedback MOSFETof about 5 ,we can expect a resolution of about 85 eVFWHM (10 ) at low energies. A peak-background ratio


Fig. 7. Measured ENC versus injected charge and corresponding spectral mea-surements for 1 �� peaking time.

Fig. 8. Spectrum from a �� source (red) compared with one measured byfeeding the shaper output through an analog monitor to a commercial Multi-channel Analyzer MCA (blue).

of about 5000 also is apparent. This considerable improvementover that of our original version (about 300 [7]) is mainly due toreducing charge-shared events with the molybdenum mask (seeFig. 2).

Comparing the two spectra highlights their differences atthe right side of the two main spectral lines and :some pile-up rejection occurs when employing the internalmulti-phase peak detector [30]. This phenomenon is explainedby examining the two cases of pile-up in Fig. 9. In the firstcase (a) the peak detector (PD) that is sensitive only to thefirst change in slope, detects and stores the first peak, whilethe MCA detects the highest peak in a fixed time-window. Itresults that the PD properly processes the first peak and rejectsthe second, highest peak while the MCA doesn’t. As the delaybetween the two pulses declines, we enter the second case (b)where lacking the first peak, both the PD and the MCA perform

Fig. 9. Comparison (a) between the responses of a multi-phase peak detector(PD), sensitive to the first change in slope, and (b) a multi-channel analyzer(MCA), sensitive to the highest peak in a given time window, for two differentcases of pile up. The red and blue are the two single pulses, with peak voltagesrepresented with dashed lines. The black line is the resulting piled-up pulse: thepeak voltages processed by the PD and MCA are marked.

Fig. 10. Spectra from a �� source with rate variable from 1 to 200 kcps. Theshift �� of the �� line and the resolution are in eV.

identically. The sharper spectral lines and the deep region attheir right side correspond to those events from case (a) ofFig. 9, while the further right region where the spectra adopt asimilar behavior corresponds to events from case (b).

Fig. 10 shows some spectral measurements at a peakingtime of 0.5 for input rates ranging from 1 to 200 kcps. Thetwo main spectral lines and exhibit a shift andbroadening at high count rates [33], along with a relative de-crease of background events at low energies. This behavior isexplained as illustrated in Fig. 11 showing two cases of pileup between a low-amplitude and a high-amplitude event; inde-pendent of the sequence, the low-amplitude event is lost andcontributes a small amount to the high-amplitude one. Consid-ering the stable baseline afforded by the Baseline Holder [28],the pile-up entails a loss of low-amplitude events and a broad-ening and shift of high-amplitude events.

III. XRS PROTOTYPE WITH PILE-UP REJECTION

In this section, we describe a more recent version of the XRSprototype, which includes our new concept for an analog pile-uprejector, and we discuss some preliminary experimental results.


Fig. 11. Examples of pile-up between a low-amplitude and an high-amplitudeevent. Independent of the sequence, the low-amplitude event is lost and con-tributes a small amount to the high-amplitude one.

Fig. 12. Block diagram of the new version of the ASIC.

A. Architecture

Most improvements made in this new prototype aimed at re-ducing the parasitic capacitance and pick-up at the charge sen-sitive input nodes (see Figs. 5 and 6), and at improving thesystem’s rate capability. The ASIC block diagram is shownin Fig. 12. The high-order shaper has now a peaking time ad-justable to 0.25-, 0.5-, 1-, and 2- , a factor of 2 smaller the pre-vious version. The area, 2.1 4.6 , is slightly smaller andthe power dissipation is the same (about 2 mW per channel). An-other major improvement consists of the pile-up rejector (PUR),discussed in the Section III-B.

To reduce the parasitic capacitance at the inputs, we opti-mized the placement of the input bonding pads and the routingof the interconnections between the input of the channel and itsbonding pad (Fig. 13(a) and (b)). Other improvements, shown inFig. 13(c), consisted of shielding the input nodes from the digitallines flowing in the interposer. We implemented two solutions:(i) Gold-plating the holes for input interconnections, and, (ii)hiding the digital lines in an inner layer and exposing those forwire bonding only when they were close to the ASIC. These de-tails are visible when comparing the bottom (gold-plated holes)and right (inner hidden lines) of Fig. 13(c) and (d). The inter-poser was also equipped with buffers for all LVDS signals, andwith on-board Analog-to-Digital Converters (ADCs) to improvethroughput by reducing the settling time of the analog signalsand to improve the analog signal by reducing the signal path.

With these optimizations, we observed improvements inthe ENC. Fig. 14 plots the ENC measured for some channelswithout and with the sensor. Channels 14 and 8, respectively,are characterized by the shortest and longest on-chip intercon-nections between the input of the channel and its bonding pad.

Fig. 13. Some recent improvements: details of placing the pads and routing theinputs of eight channels for (a) previous version, and, (b) new version; detailsof the holes and shielding the digital lines for (c) previous version, and, (d) newversion.

Fig. 14. ENC versus peaking time measured with the new version for differentchannels with input floating and connected to the SDD pixel anodes. The simu-lated ENC and its contributions, assuming no sensor and a leakage current of 1pA, are also shown.

We note that the increase in ENC is smaller than in the pre-vious version (see Fig. 5) demonstrating the effectiveness of ouron-chip optimization. Channels 14 and 11, respectively, have theshortest and longest wire-bond connection from the ASIC inputpad to the SDD anode (see Fig. 6(b)). Furthermore, channel 11that, with channel 6, constitutes the worst case in terms of capac-itance and exposure to pick-up, can achieve at 1 peaking timea sub-10 electrons ENC, corresponding to a FWHM of about 85eV for low-energy spectral lines.


Fig. 15. Spectra from a �� source measured with the new prototype without,and (b) with a test pulse.

In Fig. 15 we show spectral measurements at a low rate (about1kcps) from channel 14 with a source. We measured a res-olution of 145 eV FWHM at the line (Fig. 15(a)) corre-sponding to an electronic resolution of about 10 . Takinginto account the contribution from the discharge of the feedbackMOSFET, a resolution of about 70 eV FWHM (8 ) can beexpected at low energies. This result was confirmed by adding atest pulse with amplitude equivalent to an energy of 200 eV, asillustrated in Fig. 15(b). A resolution of 84 eV FWHM was mea-sured which, after subtracting the contributions from the 30 fFtest capacitor (about 3.5 ) and the pulse generator (about2.5 ), corresponds to 70 eV FWHM on a 200eV spectralline.

Fig. 16 is an overview of the spectral measurements forall 16 channels. A resolution of 152 eV wasmeasured on the line. Considering the noise from thedischarge in the feedback MOSFET of the charge amplifier, thiscorresponds to an electronic noise of about 84 eV

at low energies. We noted an increase in background atlow energy for all pixels along the edge, possibly signifyingan increase in the charge-sharing region. This clearly warrantsfurther investigation.

Fig. 16. Overview of �� spectral measurements on all 16 channels. A reso-lution of 152 eV �� was measured on the�� line. Consideringthe noise from the discharge in the feedback MOSFET of the charge amplifier,this corresponds to about 84 eV �� at low energies.

Fig. 17. (a) Block diagram, and (b) graph illustrating the operation of thepile-up rejector (PUR) implemented in the ASIC. A single- and a piled-up-pulseare shown, along with the timing of the discriminator (threshold crossing, � )and peak detector (peak time, � ).

B. Pile-Up Rejection

When comparing the spectrum in Fig. 15 with the one in Fig.8 (previous version), along with the improvement in resolution,we see a substantial suppression of the piled-up events in theformer, characterized by amplitudes higher than the two main

peaks and . The spectrum was measured withthe pile-up rejector enabled (PUR in Fig. 12). Fig. 17(a) and(b) are a scheme and a graph illustrating the operation of thePUR. The only circuits added to the previous electronics are theTime-to-Amplitude converter (TAC), the logic, and the trimmerto adjust the TAC duration.

The PUR employs timing signals from the discriminatorat threshold crossing, , and from the peak detector at thepeaking time . A timing window is defined, based on atime-to-amplitude converter (TAC) that starts at and,


making use of a Schmitt trigger, stops at . The timingwindow is adjusted so that the peaking time of single pulsesoccurs before , i.e., in Fig. 17(b).

When a peak is detected, the logic compares the timing sig-nals and . If (single case in Fig. 17) the pulseis accepted and the channel-event indicator (Flag) is released tostart the readout process; however, if (pile-up casein Fig. 17) the pulse is rejected and the logic resets the channelfor a new acquisition. The choice of is critical for ensuringthe proper operation and efficiency of the PUR; it must accountfor the time jitter and the time walk associated with the timingsignals and . The time jitter of is approximatedas

(1)

where is the rms voltage noise, and dV/dt is the slope of thesignal calculated at the crossing of the threshold voltage .Depending on the type and order of the shaper, simple equationsor moderately simple numeric calculations can generate .The time jitter of can be estimated as

(2)

where is the peaking time (1% to peak), and the two coef-ficients and depend, respectively, on the type and orderof the shaper [29], [34]. In our case of a 5th order shaper withcomplex conjugate poles, the corresponding values of the twocoefficients are 1.58 and 3.65 [29].

Concerning the time walk, for the peaking time it can beassumed to be a first order independent of the peak’s amplitude[35], while for threshold crossing, it depends again on the typeand order of the shaper, and it can be obtained from simple equa-tions or moderately simple numeric calculations.

Fig. 18 displays typical curves for and , normalizedto the peaking time , as functions of the peak amplitude nor-malized to the full scale ; and are assumed to be 1%and 0.3% of , respectively. In the same Fig. 3, is plottedwhere is the quadratic sum of and , assuming nocorrelation as the worst case. It readily is observed that to ensurenegligible rejection of valid single pulses, should exceed 3

, which rises as the peak amplitude declines. This figurealso illustrates the time walk associated with the thresholdcrossing, that also increases as the peak amplitude drops. Onthe one hand, the trend of the time walk lowers the efficiency ofthe pile-up rejector at low amplitudes. On the other hand, sincethe time walk exceeds the 3 , it prevents the loss of validevents over a wide range of amplitudes when small values ofare chosen (e. g., ).

In the case shown in Fig. 18, we chose a value of(5% of the peaking time). Due to the time walk, the efficiency ofthe PUR decreases with the peak amplitude, but no single eventsare lost due to time jitter. This outcome is quantified by simu-lating the single-energy spectral lines for different amplitudes.

Fig. 18. Typical curves of �� and �� , 3 �� , and�� , normalized to thepeaking time � , as function of the relative peak amplitude.

Fig. 19. (a) Simulated spectral lines for different peak amplitudes at low- andhigh-rate without and with PUR, and (b) PUR efficiency � versus relativepeak amplitude.

Thus, in Fig. 19(a) the spectrum for three different relative am-plitudes 0.05, 0.1, and 0.5 is shown for the low rate and the highrate with and without PUR. The values of

and , respectively, are assumed as 1% and 0.3% of ,


Fig. 20. Layout of the PUR circuit integrated in the ASIC channel, size90� 100 �� .

and a value of is chosen for the PUR. The plotsshow the effectiveness of the PUR in rejecting events in the re-gion between the main line and the double-amplitude line.

As a measure of the efficiency of the PUR, we can adoptthe ratio of the FWHM of the main spectral line with respectto the of the corresponding double-amplitude line asfollows:

(3)

It is noted that any PUR, including the ideal case, fails to dis-criminate and reject events that are fully superposed. In thatcase the pulse results from the superposition of two individualnon-correlated x-ray events. The corresponding is afactor larger than the FWHM of the main line. Hence the co-efficient in (3); in the ideal noiseless case approachesthe unity.

Fig. 19(b) shows the PUR efficiency vs the relativeamplitude and it reveals that the efficiency decreasesas the peak amplitude decreases, followed by an increase thatarises from the decline in the contribution of the piled-up eventsto broadening compared with the actual noise. In fact, in contrastto the noise, the contribution of the pile-up to the line broadeningdrops as the peak amplitude falls.

Finally, from Fig. 19(a) we note that, as expected, the peak-to-valley ratio of the spectrum with pile-up decreases with ampli-tude, because, at low amplitudes, the same number of pile-upevents spreads over a smaller range of amplitudes. So far, weassumed negligible dispersion in the diffusion of the charge col-lected at the anode of the SDD pixel. In actuality, dispersion in-creases with the distance of the anode from the interaction point,and was estimated at about 15 ns rms. The corresponding impacton the amplitude and peaking time is about 0.02% and 7.5 ns. Toavoid loss of valid single events, the latter value must be addedto .

The PUR circuit integrated in the ASIC channel implementsa 3-bit trimmer to adjust and optimize the value of . Fig. 20shows the layout of the PUR, which dissipates less than 1at 200 kcps in an area of 90 100 .

Fig. 21 compares two spectra measured at 200 kcpswithout and with the PUR. The gain was set at 2.6 V/fC,thus extending the energy range to more than 18 keV. The

Fig. 21. Spectra from a �� source measured without and with PUR at a rateof 200 kcps, a peaking time of 1 ��, and a gain of 2.6 V/fC.

main-, double-, and triple-lines of and andtheir combinations can be observed. Our measured ratio,

, corresponds to a PUR efficiencyand is slightly lower than we anticipated from

the simulations of Fig. 19. Due to a design error, the trimmingrange was shifted, and the lowest available value of used inthese measurements was higher than the optimum. We resolvedthis issue in an ASIC revision now being fabricated.

Several pile-up rejection techniques were proposed. Someuse digital signal processing, and require fast analog-to-digitalconversion (ADC) of the analog signal [33], [36], [37]. Thesesolutions, mostly based on shape discrimination, in principlemay offer better rejection performance than ours, and otheradvantages, like recovering some piled-up pulses by amplitudecorrection [38]–[40]. However, the power and processing timeneeded to perform ADC per channel and digital processingcurrently is prohibitive for all applications requiring either ahigh density of channels or a limited power budget. Amongthe analog techniques adopted, the most common uses anadditional fast shaper and veto logic to detect and reject pile-upin the main slow shaper [20], [41], [42]. Due to the higher noiseand the width of the fast-shaped pulse, efficiency is lower atlow amplitudes and for closely spaced pulses, as in our case.The drawback is in the need for additional shaping and dis-crimination circuits. We note that rejecting pile-up events withan internal reset, transparent to the external readout electronics,also minimizes dead time compared to off-line rejection.Additionally, the proposed technique best uses the alreadyavailable circuits (the discriminator and the peak detector withthe peak-found signal). These are further advantages of ourapproach compared to other analog techniques [43]–[45] thatare characterized by higher complexity or need for additionalconversion and off-line processing.

IV. CONCLUSIONS AND FUTURE WORK

We discussed our progress in developing a high-resolutionand low-power x-ray spectrometer (XRS) for extra-terrestrial


applications. Our XRS is based on pixelated Silicon Drift Detec-tors with anodes directly wire-bonded to the inputs of an Appli-cation Specific Integrated Circuit (ASIC). The results achievedwith our most recent version are within the requirements forsome low-rate space missions. Our next version will focus onoptimizing performance for high-rate environments, and mightbe characterized by a more relaxed power budget. We describedour novel pile-up rejector that gave encouraging results, whileleaving margins for its optimization.

ACKNOWLEDGMENT

The authors are grateful to the reviewers, editor, andsenior editor for their valuable suggestions and com-ments; V. Radeka and G. C. Smith for helpful discussions;R. Beuttenmuller and J. Triolo for technical assistance; andA. D. Woodhead for assistance with editing. The authors arealso indebted to KETEK GmbH, A. Fazzi from Milan Poly-technic, and S. Babu from NASA/GSFC.

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