16 Clocking
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Transcript of 16 Clocking
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Clocking
Bharadwaj Amrutur
ECE Dept, IISc Bangalore 12
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Sequencing Elements
Latch: Level sensitive
a.k.a. transparent latch, D latch
Flip-flop: edge triggered
a.k.a. master-slave flip-flop, D flip-flop, D
register
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Latch Design
Q
DX
Q
DX
D
X
Q
D Q
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Latch: Opaque state
Q
DX
D
X
Q
D Q
Q
DX
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Latch:Transparent
D
X
Q
D Q
Q
DX
Q
DX
tdq = ?
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Latch setup:Transparent to Opaque
D
X
Q
D Q
Q
DX
Q
DX
tsetup = ?thold = ?
D
Q
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Latch hold:Transparent to Opaque
D
X
Q
D Q
Q
DX
Q
DX
tsetup = ?thold = ?
D
Q
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Flop/Latch characterization
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Latch based design
T T
Combinational
Logic
Both latches are positive transparent
Why will this not work in general?
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Latch based design
T T
Combinational
Logic
Cannot drive latch from another latch driven off
the same phase in general
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Flip-Flop Design
Flip-flop is built as pair of back-to-back latches
D Q
X
D
X
Q
Q
T T
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Sequencing Methods
Flip-Flo
ps
Flop
Latch
Flop
clk
1
2
p
clk clk
Latch
Latch
p
p
1
1
2
2-Ph
ase
TransparentLatchesPulsed
Latches
Combinational Logic
CombinationalLogic
CombinationalLogic
Combinational LogicLatch
Latch
Tc
Tc/2
tnonoverlap tnonoverlap
tpw
Half-Cycle 1 Half-Cycle 1
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Max-Delay: Flip-Flops
F1
F2
clk
clk clk
Combinational Logic
Tc
Q1 D2
Q1
D2
tpd
tsetuptpcq
tcq
tpd
thold
Tc
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Min-Delay: Flip-Flops
CL
clk
Q1
D2
F
1
clk
Q1
F2
clk
D2
tcd
thold
tccq
tccq
tcd
thold
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Understanding clock skew
Delay mismatchcauses clock skew
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Understanding clock skew
Delay mismatch
causes clock skew
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Clock Skew: Flip flops
F1
F2
clk
clk clk
Combinational Logic
Tc
Q1 D2
Q1
D2
tskew
CL
Q1
D2
F1
clk
Q1
F2
clk
D2
clk
tskew
tsetup
tpcq
tpdq
tcd
thold
tccq
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Why would there be mismatch?
Delay mismatch
causes clock skew
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Why would there be mismatch?
Delay mismatch
causes clock skew
Asymmetry
Delay ~ f (CV/I,edgerate)C mismatch:
V mismatch:
I mismatch:
Edge rate mismatch:
Non-random:
Random:
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Why would there be mismatch?
Delay mismatch
causes clock skew
Asymmetry
Delay ~ f (CV/I,edgerate)C mismatch: size, state, wires
V mismatch: supply gradient
I mismatch: driver size, layout topology, random variations
Edge rate mismatch: I mismatch, wire RC
Mismatch types:
Non-randomRandom
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Random Mismatch
Variations in length and width (due to etching)Fluctuations in number of dopant atomsLeads to variations in current (I)
Cl k i
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Clock Jitter
Variations in clock arrival time at inputs of a sequencingelement
Random and Deterministic components Varies cycle to cycle
Contrast with Clock skew: measures the averagedifference in arrival times of the clock at twodifferent sequencing elements.
ideal
lateearly
Period jitter:Variations in periodWhen referenced toIdeal clock.
Cycle to cycle jitter:Variations in nextEdge when referencedTo previous edge
Cl k Ji Fli fl
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Clock Jitter: Flip flops
F1
F2
clk
clk clk
Combinational Logic
Tc
Q1 D2
Q1
D2
tskew
CL
Q1
D2
F1
clk
Q1
F
2
clk
D2
clk
tskew
tsetup
tpcq
tpdq
tcd
thold
tccq
Wh t l k jitt ?
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What causes clock jitter?
Noise
Delay ~ f (CV/I,edgerate)C: state changes per cycle
V mismatch: supply gradient per cycle, coupling noise
I mismatch: Supply noise, substrate noise
Edge rate mismatch: coupling noise
Jitter types:
Non-random
Random