15 Counters

DIGITAL ELECTRONICS (331102)

61 | P a g e SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))

PRACTICAL: 15

TO STUDY COUNTERS

1.0 AIM :

To study and design Counters.

2.0 PRIOR CONCEPTS :

Knowledge of working of AND, OR, NOT gate.

Knowledge of working of NAND and Ex - OR gates.

Difference between sequential circuit and combinational circuit.

Working of flip flops.

3.0 INTRODUCTION :

A counter, by function is a sequential circuit consisting a set of flip flops

connected in a suitable manner to count the sequence of the input pulses

presented to it in digital form.

Counters can be broadly classified under 3 heads as follows :

o Asynchronous and Synchronous counter.

o Single and Multimode counters

o Modulus counters.

In electronics, counters can be implemented quite easily using register-type

circuits such as the flip-flop, and a wide variety of designs exist, e.g:

o Asynchronous (ripple) counter – changing state bits are used as clocks to

subsequent state flip-flops

o Synchronous counter – all state bits change under control of a single clock

o Decade counter – counts through ten states per stage

o Up–down counter – counts both up and down, under command of a control

input

o Ring counter – formed by a shift register with feedback connection in a

ring

o Johnson counter – a twisted ring counter

o Cascaded counter

http://en.wikipedia.org/wiki/Electronics

http://en.wikipedia.org/wiki/Flip-flop_(electronics)



4.0 ASYNCHRONOUS (RIPPLE) COUNTER :

An asynchronous (ripple) counter is a single D-type flip-flop, with its D (data)

input fed from its own inverted output.

This circuit can store one bit, and hence can count from zero to one before it

overflows (starts over from 0).

This counter will increment once for every clock cycle and takes two clock cycles

to overflow, so every cycle it will alternate between a transition from 0 to 1 and a

transition from 1 to 0.

This creates a new clock with a 50% duty cycle at exactly half the frequency of

the input clock.

If this output is then used as the clock signal for a similarly arranged D flip-flop

(remembering to invert the output to the input), you will get another 1 bit

counter that counts half as fast. Putting them together yields a two bit counter:

You can continue to add additional flip-flops, always inverting the output to its

own input, and using the output from the previous flip-flop as the clock signal.

The result is called a ripple counter, which can count to 2n -1 where n is the

number of bits (flip-flop stages) in the counter.

Ripple counters suffer from unstable outputs as the overflows "ripple" from stage

to stage, but they do find frequent application as dividers for clock signals, where

the instantaneous count is unimportant, but the division ratio overall is.

The use of flip-flop outputs as clocks leads to timing skew between the count data

bits, making this ripple technique incompatible with normal synchronous

circuit design styles.

http://en.wikipedia.org/wiki/Flip-flop_(electronics)#D_flip-flop

http://en.wikipedia.org/wiki/Duty_cycle

http://en.wikipedia.org/wiki/Ratio

http://en.wikipedia.org/wiki/Synchronous_circuit

http://en.wikipedia.org/wiki/Synchronous_circuit



This circuit would yield the following output waveforms, when "clocked" by

a repetitive source of pulses from an oscillator:

We can design a counter as Simultaneous “Up – Down” counter as follows



5.0 SYNCHRONOUS COUNTER :

A simple way of implementing the logic for each bit of an ascending counter

(which is what is depicted in the image to the right) is for each bit to toggle when

all of the less significant bits are at a logic high state.

For example, bit 1 toggles when bit 0 is logic high; bit 2 toggles when both bit 1

and bit 0 are logic high; bit 3 toggles when bit 2, bit 1 and bit 0 are all high; and

so on.

Synchronous counters can also be implemented with hardware finite state

machines, which are more complex but allow for smoother, more stable

transitions.

A synchronous counter, in contrast to an asynchronous counter, is one whose

output bits change state simultaneously, with no ripple.

The only way we can build such a counter circuit from J-K flip-flops is to connect

all the clock inputs together, so that each and every flip-flop receives the exact

same clock pulse at the exact same time:

http://en.wikipedia.org/wiki/Finite_state_machine

http://en.wikipedia.org/wiki/Finite_state_machine



Each of the higher-order flip-flops are made ready to toggle (both J and K

inputs "high") if the Q outputs of all previous flip-flops are "high."

Otherwise, the J and K inputs for that flip-flop will both be "low," placing it

into the "latch" mode where it will maintain its present output state at the

next clock pulse.

Since the first (LSB) flip-flop needs to toggle at every clock pulse, its J

and K inputs are connected to Vcc or Vdd, where they will be "high" all the

time.

The next flip-flop need only "recognize" that the first flip-flop's Q output is

high to be made ready to toggle, so no AND gate is needed.



However, the remaining flip-flops should be made ready to toggle only

when all lower-order output bits are "high," thus the need for AND gates.

To make a synchronous "down" counter, we need to build the circuit to

recognize the appropriate bit patterns predicting each toggle state while

counting down.

Not surprisingly, when we examine the four-bit binary count sequence, we

see that all preceding bits are "low" prior to a toggle.

Since each J-K flip-flop comes equipped with a Q' output as well as a Q

output, we can use the Q' outputs to enable the toggle mode on each

succeeding flip-flop, being that each Q' will be "high" every time that the

respective Q is "low:".

Taking this idea one step further, we can build a counter circuit with

selectable between "up" and "down" count modes by having dual lines of

AND gates detecting the appropriate bit conditions for an "up" and a

"down" counting sequence, respectively, then use OR gates to combine

the AND gate outputs to the J and K inputs of each succeeding flip-flop:



This circuit isn't as complex as it might first appear.

The Up/Down control input line simply enables either the upper string or

lower string of AND gates to pass the Q/Q' outputs to the succeeding

stages of flip-flops.

If the Up/Down control line is "high," the top AND gates become enabled,

and the circuit functions exactly the same as the first ("up") synchronous

counter circuit shown in this section.

If the Up/Down control line is made "low," the bottom AND gates become

enabled, and the circuit functions identically to the second ("down"

counter) circuit shown in this section.



6.0 RING COUNTER :

Ring counters are implemented using shift registers.

It is essentially a circulating shift register connected so that the last flip-

flop shifts its value into the first flip-flop.

There is usually only a single 1 circulating in the register, as long as clock

pulses are applied.

In the diagram above, assuming a starting state of Q3 = 1 and Q2 = Q1 =

Q0 = 0.

At the first pulse, the 1 shifts from Q3 to Q2 and the counter is in the

0100 state. The next pulse produces the 0010 state and the third, 0001.

At the fourth pulse, the 1 at Q0 is transferred back to Q3, resulting in the



1000 state, which is the initial state. Subsequent pulses will cause the

sequence to repeat, hence the name ring counter.

The ring counter above functions as a MOD-4 counter since it has four

distinct states and each flip-flop output waveform has a frequency equal

to one-fourth of the clock frequency.

A ring counter can be constructed for any MOD number. A MOD-N ring

counter will require N flip-flops connected in the arrangement as the

diagram above.

A ring counter requires more flip-flops than a binary counter for the same

MOD number. For example, a MOD-8 ring counter requires 8 flip-flops

while a MOD-8 binary counter only requires 3 (23 = 8).

So if a ring counter is less efficient in the use of flip-flops than a binary

counter, why do we still need ring counters? One main reason is because

ring counters are much easier to decode.

In fact, ring counters can be decoded without the use of logic gates. The

decoding signal is obtained at the output of its corresponding flip-flop.

For the ring counter to operate properly, it must start with only one flip-

flop in the 1 state and all the others at 0.

Since it is not possible to expect the counter to come up to this state

when power is first applied to the circuit, it is necessary to preset the

counter to the required starting state before the clock pulses are applied.

One way to do this is to apply a pulse to the PRESET input of one of the

flip-flops and the CLEAR inputs of all the others. This will place a single 1

in the ring counter.

7.0 EXERCISE :

7.1 What is meant by DUTY CYCLE?

Ans:



7.2 Why J- K Flip Flops are used to design a counter?

Ans:

7.3 What is the difference between Up counter and Down Counter?

Ans:

7.4 State the reason, why Asynchronous Counter are called Ripple counter?

Ans :

7.5 What is the basic design difference between Asynchronous counter and

Synchronous counter?

Ans :

7.6 State the Application of clock in Counter.

Ans:



8.0 ASSIGNMENT :

8.1 State the function of Asynchronous Counter.

8.2 State the function of Synchronous Counter.

8.3 Why clock signal is used in synchronous Counter?

8.4 State the application of Counters.

8.5 Describe the functioning of Up counter in Up-Down Counter.

8.6 Describe the functioning of Down counter in Up-Down Counter.

8.7 Explain the functioning of Ring Counter.

Grades for Exercise: .................................................

Grades for Assignment: .................................................

Signature of Lab Co-ordinators: .................................................

15 Counters

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