15 A Synchronous Machine

8/3/2019 15 A Synchronous Machine

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Asynchronous Machine


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Types of Asynchronous Sequential Machines

Pulse-Mode Pulse will not occur simultaneously on two or more inputs

Memory Element transitions are initiated by input pulses

Input variables are used only in the uncomplemented or

complemented forms, but not both

y1 Yryr Y1

Flip-Flop

memory

Combinational

logic

Pulse Mode circuit model

x1 z1

xn zm


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Fundamental Mode Level inputs and unclocked memory element

Assume delay is lumped and equal (t)

In reality often not necessary

Only one input is allowed to change at any instant of time

y1 Yryr Y1

Delay, t

Combinational

logic

Fundamental Mode circuit model

x1 z1

xn zm


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In all types: State must be stable before input can bechange

Behavior is unpredictable (nondeterministic) if circuit not

allowed to settle


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Stable State

PS = present state NS = next state

PS = NS = Stability

Machine may pass through none or more intermediate

states on the way to a stable state Desired behavior since only time delay separates PS from NS

Oscillation

Machine never stabilizes in a single state


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Races

A Race Occurs in a Transition From One State to the NextWhen More Than One Next State Variables Changes in

Response to a Change in an Input

Slight Environment Differences Can Cause Different State

Transitions to Occur Supply voltage

Temperature, etc.


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Races

Desired Next State: NS

if Y1 changesfirst

if Y2 changesfirst

01

Present State : PS (Y1Y2)

11 00

10


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Types of Races

Non-Critical Machine stabilizes in desired state, but may transition through

other states on the way

Critical

Machine does not stabilize in the desired state


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Races

Desired Next State: NS

if Y1 changesfirst

if Y2 changesfirst

01

Present State : PS (Y1Y2)

11 00

1000

Non-Critical Race

Critical Race


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Asynchronous FSM Benefits

Fastest FSM Economical

No need for clock generator

Output Changes When Signals Change, Not When Clock

Occurs Data Can Be Passed Between Two Circuits Which Are Not

Synchronized

In some technologies, like quantum, clock is just not

possible to exist, no clocks in live organisms.


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Asynchronous FSM Example

nextstatepresent

state y1

y2

input


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Next State Variables

( ) ( ) ( )

( )

12

2212

2211

2211211

,,

,,

yxy

yxyyyxY

yxyyxyx

yxyyxyxyyxY

+=

=

++=

++=


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Asynchronous State Tables

States are either Stable or Unstable. Stable states encircled with symbol.

Presentstate

Next state, output

x=0 x=1

Q0 Q0,0 Q1,0

Q1 Q2,0 Q1,0

Q2 Q2,0 Q3,1

Q3

Q0, 0

Q3,1

Oscillations occur if all states are unstable for an input value.

Total State is a pair (x, Qi)


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Constraints on Asynchronous Networks

If the next input change occurs before the previousones effects are fed back to the input, the machinemay not function correctly.

Thus, constraints are needed to insure proper

operation.

Fundamental Mode Input changes only when themachine is in a stable state.

Normal Fundamental Mode A single input changeoccurring when the machine is in a stable stateproduces a single output change


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Analysis Pulse-Mode Asynch. Circuit

Assumptions Pulse do not occur simultaneously on two or more input lines

State transition only occurs only if an input pulse occurs

All devices trigger on the same edge of each pulse


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Q

QSET

CLR

S

R

x1

x2

z

y

y

States:y = 0 = Ay = 1 = B

Inputs:

[x1,x2] = 00 = I0[x1,x2] = 10 = I1[x1,x2] = 01 = I2

yxR

yxS

yxz

2

1

1

=

=

=


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Inputs:[x1,x2] = 00 = I0[x1,x2] = 10 = I1[x1,x2] = 01 = I2 yxR

yxSyxz

2

1

1

=

=

=

x1

x2

y

S

R

z


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Inputs:[x1,x2] = 00 = I0[x1,x2] = 10 = I1[x1,x2] = 01 = I2 yxR

yxSyxz

2

1

1

=

=

=

y\x1x2 00 01 11 10

0 0 0 - 1

1 0 0 - 0

S

y\x1x2 00 01 11 10

0 0 0 - 0

1 0 1 - 0

R

y\x1x2 00 01 11 10

0 0 0 - 0

1 0 0 - 1

z


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y\x1x2 00 01 11 10

0 00 00 - 10

1 00 01 - 00

SR

y\x1x2 00 01 11 10

0 0 0 - 1

1 1 0 - 1

Y

y\x1x2 00 01 11 10

0 0/0 0/0 - 1/0

1 1/0 0/0 - 1/1

Y/z

y\x1x2 00 01 11 10

0 0 0 - 1

1 0 0 - 0

S

y\x1x2 00 01 11 10

0 0 0 - 0

1 0 1 - 0

R

y\x1x2 00 01 11 10

0 0 0 - 0

1 0 0 - 1

z


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Q

QSET

CLR

S

R

x1

x2

z

y

y


Inputs:[x1,x2] = 00 = I0[x1,x2] = 10 = I1[x1,x2] = 01 = I2

yxR

yxS

yxz

2

1

1

=

=

=

y\x1x2 00 01 10

0 0/0 0/0 1/0

1 1/0 0/0 1/1

Y/z PresentState

I0 I2 I1

A A/0 A/0 B/0

B B/0 A/0 B/1

Present

State

x1 x2

A B/0 A/0

B B/1 A/0


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Exercise

Q

QSET

CLR

D

x z

y1

Q

QSET

CLR

Dy2

21

212

2111

,,

yxyz

xCyDxyCyD

=

==

==

Inputs:I0 = no pulse on xI1 = pulse on x

States (y1, y2)A = 00B = 01C = 10D = 11


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Exercise

21

212

2111

,,

yxyz

xCyDxyCyD

=

==

==Inputs:I0 = no pulse on xI1 = pulse on x

States (y1

, y2

)A = 00B = 01C = 10D = 11

x

y1

y2

D1=D2

C1

C2

z

0

0

0 0

0

0

1

1

1 1


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Exercise

We need to construct the K-mapfor the State Table.

DFF clock input will see a transition1 to 0 if the input pulse occurs

From the DFF Characteristics

equation and this observation, thenext state equations are:

Q

QSET

CLR

D

x z

y1

Q

QSET

CLR

Dy2

21

212

2111

,

,

yxyz

xCyD

xyCyD

=

==

==

21

22222

212121

2121

11111

)(

yxyx

CyCDY

yyyyxyyx

yxyxyy

CyCDY

+=

+=

++=

++=

+=


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Exercise

y1y2\x 0 1

00 1 1

01 1 1

11 0 0

10 0 0

D1 y1y2\x 0 1

00 0 0

01 0 1

11 0 1

10 0 0

C1 y1y2\x 0 1

00 10 10

01 10 11

11 00 01

10 00 00

D1

C1

y1y2\x 0 1

00 1 1

01 1 111 0 0

10 0 0

D2y1y2\x 0 1

00 0 1

01 0 111 0 1

10 0 1

C2y1y2\x 0 1

00 10 11

01 10 1111 00 01

10 00 01

D2C2

22222

11111

CyCDY

CyCDY

+=

+=

y1y2\x 0 1

00 0 0

01 0 1

11 1 0

10 1 1

Y1

y1y2\x 0 1

00 0 1

01 1 111 1 0

10 0 0

Y2


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Exercise

y1y2\x 0 1

00 00 01

01 01 11

11 11 00

10 10 10

Y1

Y2

21

22222

11111

yxyz

CyCDY

CyCDY

=

+=

+=

y1y2\x 0 1

00 0 0

01 0 1

11 1 0

10 1 1

Y1

y1y2\x 0 1

00 0 1

01 1 111 1 0

10 0 0

Y2y1y2\x 0 1

00 00/0 01/0

01 01/0 11/011 11/0 00/1

10 10/0 10/0

Y1Y2/z

y1y2\x I0 I1

00 00/0 01/0

01 01/0 11/0

11 11/0 00/1

10 10/0 10/0

Y1Y2/z

y1y2\x x

00 01/0

01 11/0

11 00/1

10 10/0

Y1Y2/z


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Exercise

Q

QSET

CLR

D

x z

y1

Q

QSET

CLR

Dy2

y1y2\x I0 I1

A A/0 B/0

B B/0 D/0

C C/0 C/0

D D/0 A/1

Y1Y2/z

A B

D C

I0/0

I1/0

I0/0

I0/0

I0/0I1/0I1/1

I1/0


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Design of Pulse-Mode Circuit

Step 1. Derive state diagram or state table

Step 2. Minimize the state table

Step 3. Choose state assignment and generate the

transition output table

Step 4. Select type of latch or flip-flop to be used anddetermine excitation equation

Step 5. Determine the output equation

Step 6. Draw the circuit


28/99

Do it yourself

Design a pulse-mode circuit having two input lines x1

and

x2, and one output line z. The circuit should produce an

output pulse coincide with the last input pulse in the

sequence x1-x2-x2. No other input sequence should

produce an output pulse. (Sequence detector x1

-x2

-x2

)

Use T-FF: T = 1, C acts as input


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Step 1

States

A : indicates that the last input was x1

B : indicates that the sequence x1-x2 occurs

C : indicates that the sequence x1-x2-x2 occurs

Present

Statex1 x2

A A/0 B/0

B A/0 C/1

C A/0 C/0

A B

C

x1/0

x2/0

x1/0

x2/0

x2/1x1/0


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Step 2 and 3

Step 2. State table is minimize as given

Step 3. State assignment A=00, B=01, and C=10

y1y2 x1 x2

00 00/0 01/0

01 00/0 10/1

10 00/0 10/0

Y1Y2/z


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Step 4 and 5

Use T-FF: T = 1

y1y2 x1 x2

00 00/0 01/0

01 00/0 10/1

10 00/0 10/0

Y1Y2/z

y1y2 x1 x2

00 0 0

01 0 1

11 d d

10 0 1

Y1

y1y2 x1 x2

00 0 0

01 0 1

11 d d

10 1 0

C1

y1y2 x1 x2

00 0 1

01 0 0

11 d d

10 0 0

Y2

y1y2 x1 x2

00 0 1

01 1 1

11 d d

10 0 0

C2

y1y2 x1 x2

00 0 0

01 0 1

11 d d

10 0 0

z

22

12212

22111

yxz

yxyxC

yxyxC

=

+=

+=


32/99

Step 6

22

12212

22111

yxz

yxyxC

yxyxC

=

+=

+=

z

y1

y2

TQ

Q

T Q

Q

x1

x2

1

1


33/99

Do it yourself

Design a pulse-mode circuit with inputs x1

,x2

, x3

and

output z. The output must change from 0 to 1 iff the input

sequence x1-x2-x3 occurs while z = 0. The output must

change from 1 to 0 only after an x2 input occur.

Use SR Latch


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Step 1

Moore machine because output must remain high

between pulses

Present

Statex1 x2 x3 z

A B A A 0

B B C A 0

C B A D 0

D D A D 1

A/0 B/0

D/1 C/0

x2,x3x1

x1

x1

x3

x2

x3

x2

x2

x1,x3


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Step 2 and 3

Step 2. State table is minimize as given

Step 3. State assignment A=00, B=01, C=11, and D =10

y1y2 x1 x2 x3 z

00 01 00 00 0

01 01 11 00 0

11 01 00 10 0

10 10 00 10 1

Y1Y2

Y1Y2


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Step 4

Use SR Latch

y1y2 x1 x2 x3

00 0 0 0

01 0 1 0

11 0 0 1

10 1 0 1

Y1

y1y2 x1 x2 x3 z

00 01 00 00 0

01 01 11 00 0

11 01 00 10 0

10 10 00 10 1

1 2

y1y2 x1 x2 x3

00 1 0 0

01 1 1 0

11 1 0 0

10 0 0 0

Y2

y1y2 x1 x2 x3

00 0 0 0

01 0 1 0

11 0 0 d

10 d 0 d

S1

y1y2 x1 x2 x3

00 d d d

01 d 0 d

11 1 1 0

10 0 1 0

R1

y1y2 x1 x2 x3

00 1 0 0

01 d d 0

11 d 0 0

10 0 0 0

S2

y1y2 x1 x2 x3

00 0 d d

01 0 0 1

11 0 1 1

10 d d d

R2

12211

2121

yxyxR

yyxS

+=

=

3121

112

xyxR

yxS

+=

=


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Step 5

y1y2 x1 x2 x3 z

00 01 00 00 0

01 01 11 00 011 01 00 10 0

10 10 00 10 1

Y1Y2

21

yyz =


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Step 6

12211

2121

yxyxR

yyxS

+=

=

3121

112

xyxR

yxS

+=

=21yyz =

Q

QSET

CLR

S

R

Q

QSET

CLR

S

R

x1

x2

x3

z


39/99

Analysis Fundamental-Mode Asynch. Circuit

Assumptions

Fundamental Mode Input changes only when the machine is

in a stable state.

Normal Fundamental Mode A single input change occurring

when the machine is in a stable state produces a single output

change

This type of circuit is most difficult to analyze


40/99

Introduction to Fundamental mode

x=(x1, , xn) : input state

y =(y1, , yr) : secondary state z=(z1, , zm) : output state

Y=(Y1, , Yr) : excitation state

(x,y) : total state

y1 Yryr Y1

Delay, t

Combinational

logic

Fundamental Mode circuit model

x1 z1

xn zm

ttt

ttt

ttt

Yy

yxhY

yxgz

=

=

=

+

),(

),(


41/99

Example

Set of equations

Delay

dt

x1

x2 z

ttt

tt

tttttttt

Yy

zY

yxxxyxxgz

=

=

+==

+

22121),,(

x1

x2

y

z=Y

t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15

Unstable at t3 (y Y)


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Tabular Representation

Excitation Table

Excitation state and output

It is a function of total space (x1, ,xn, y1, , yr)

K-map of

Row of secondary state

Column of unique input state

ttt

tt

tttttttt

Yy

zY

yxxxyxxgz

=

=

+==

+

22121 ),,(y\x1x2 00 01 11 10

0 0/0 0/0 1/1 0/0

1 1/1 0/0 1/1 1/1


43/99


Flow Table

Replace the secondary state and excitation state by letters or

nonbinary characters

It represents the behavior of the circuit but does not specify

the realization of the circuit

y\x1x2 00 01 11 10

0 0/0 0/0 1/1 0/0

1 1/1 0/0 1/1 1/1

y\x1x2 00 01 11 10

a a/0 a/0 b/1 a/0

b b/1 a/0 b/1 b/1


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Flow Table

Can be used to determinethe output behavior givenan input sequence

Input change produce

horizontal movement State changes produce

vertical movement

y\x1x2 00 01 11 10

a a/0 a/0 b/1 a/0

b b/1 a/0 b/1 b/1

x1

x2

y

z=Y

t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15

t1 t2t3

t4t5

t6t7


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Analysis of Fundamental-Mode Asynch. Circuit

Determine the excitation and output equations from the

circuit diagram

Plot the excitation and output K-map for Y and z and from

these K-map construct the excitation table

Locate and circle all stable state in the excitation table Assign a unique nonbinary symbol for each row of the

excitation table.

Construct the flow table


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Example

Step 1

1

12

21

yxz

yxY

yxY

=

=

=

Delay

dt

x z

Delay

dt

Y2

Y1

y2

y1


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Example

Step 2

y1y2\x 0 1

00 1 0

01 0 0

11 0 010 1 0

Y1y1y2\x 0 1

00 0 1

01 0 1

11 0 010 0 0

Y2y1y2\x 0 1

00 0 0

01 0 0

11 1 010 1 0

z

y1y2\x 0 1

00 10/0 01/0

01 00/0 01/0

11 00/1 00/0

10 10/1 00/0

Y1 Y2/z

y1y2\x 0 1

1 3/0 2/0

2 1/0 2/0

4 1/1 1/0

3 3/1 1/0

Y1 Y2/z

y1y2\x 0 1

1 3/0 2/0

2 1/0 2/0

3 3/1 1/0

4 1/1 1/0

Y1 Y2/z

1

12

21

yxz

yxY

yxY

=

=

=


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y1y2\x 0 1

00 10/0 01/0

01 00/0 01/0

11 00/1 00/0

10 10/1 00/0

Example

Timing Diagram

y1y2\x 0 1

00 10/0 01/0

01 00/0 01/0

11 00/1 00/0

10 10/1 00/0

Y1 Y2/z

Y1 Y2/z

x

y1

y2

Y1

Y2

z

dt dt

Start from (2) and input changes from 1 to 0State (2) 1 (3)


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Example

Step 1

Let Q0 be state when y1 = 0 and Q1 be state when y1 = 1.

12

111

1221112

1121121

)(

)())((

yz

yxz

yxxxyxx

yxxyxxY

=

=

+=+=

+=++=x1 z1

Delaydt

z2

Y1y1

x2


50/99

Example

Step 2 through 5

Let Q0 be state when y1 = 0 and Q1 be state when y1 = 1.

y1\x1 x2 00 01 11 10

0 0 0 0 1

1 1 0 0 1

Y1

y1\x1 x2 00 01 11 10

0 0 0 0 0

1 1 1 1 1

z1

y1\x1 x2 00 01 11 10

0 1 1 0 0

1 0 0 0 0

z2

PresentState

Input x1,x2

00 01 11 10

Q0 Q0,10 Q0,10 Q0,00 Q1,00

Q1 Q1,01 Q0,01 Q0,01 Q1,01

z1z2

x1 z1

Delaydt

z2

Y1y1

x2


51/99

Do it Yourself

Analyze this circuit!

Q

QSET

CLR

S

R

Q

QSET

CLR

S

R

x1

x1

x1

x1x2

x1x2

x1

z

Q1

Q2


52/99

Example (Excitation Table)

1 1 2

1 1 2

2 1 2 1

1 1 2 1 1

S x Q R x Q

S x x Q

R x x x Q

=

=

=

= +

1 2 1 2 z Q Q x Q= +

Present State

(Q1Q2)

Excitation

(S1R1,S2R2)

Output

(z)

Inputs State (x1x2) Inputs State (x1x2)

00 01 10 11 00 01 10 11

00 00,01 00,01 10,00 10,00 0 0 1 1

01 00,01 00,01 01,00 01,00 0 0 0 0

10 00,01 00,10 10,00 10,00 1 1 1 1

11 00,01 00,10 01,00 01,00 0 0 0 0


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Example (Transition Table)

Present State(Q1Q2)

Next State(Q+1Q

+2)

Output(z)


00 01 10 11 00 01 10 11

00 00 00 10 10 0 0 1 1

01 00 00 01 01 0 0 0 0

10 10 11 10 10 1 1 1 1

11 10 11 01 01 0 0 0 0


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Example (State Table)

Present State(Q1Q2)

Next State(Q+1Q

+2)

Output(z)


00 01 10 11 00 01 10 11

00 A A A C C 0 0 1 1

01 B A A B B 0 0 0 0

10 C C D C C 1 1 1 1

11 D C D B B 0 0 0 0


55/99

Example (Flow Table)

Present State(Q1Q2)

Next State(Q+1Q

+2)

Output(z)


00 01 10 11 00 01 10 11

A A A C C 0 0 - -

B A A B B - - 0 0

C C D C C 1 - 1 1

D C D - B - 0 - -


56/99

Tables, tables and tables.

Excitation table

Transition Table

State Table

Flow Table

Careful with unreachable state because input is restricted Output only at stable state


57/99

Design of Fundamental-Mode Circuit

Step 1. Construct a primitive flow table from word

description of the problem

Step 2. Derive a reduced primitive flow table

Step 3. Make secondary state assignment

Step 4. Construct excitation table and output table Step 5. Determine the logic equations for each state

variable and output state variable

Step 6. Realize the logic equation with the appropriate

logic devices

A primitive flow table is a flow table that contains only

one stable state per row


58/99

Example

A two input (x1,x2) and one output (z) asynchronous sequential

circuit is to be designed to meet the following specifications.1. Whenever x1 = 0, z = 0.

2. The first change to input x2 that occurs while x1 = 1 must cause theoutput to become z = 1.

3. A z = 1 output must not change to z = 0 until x1 = 0.

A typical input-output response of the desired circuit isshown below.

x1

x2

z


59/99

Example

Step 1. Create a primitive table that satisfy the

requirement of the circuit.

Note:

Given only one stable state then we can only have 2 other

unstable state and one unspecified state.

x1

x2

z


60/99

Example

Possible input x1x

2= 00

Since the circuit is operating

on fundamental mode, then

there must be a stable state

at x1x2 = 00

Create a state a in the next

state at 00 column.

Circle it because it must be

stable.

Since z = 0 when x1 = 0, thenthe output is set to 0

Present

State

Next State, Output

00 01 10 11

a a,0


61/99

Example At state (a),

Since there can be only onestable state in each row, thisimplies that x1x2 = 11 can notfollow x1x2 = 00.

Place -,- at column x1x2 = 11

When x1x2 = 01, the next state must be an

unstable state, named b with output.

We must add a new row forstate b, where b is stable forx1x2 = 01

Since z = 0 for x1 = 0 then theoutput is zero

Present

State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b b,0

c c,0

When x1x2 = 10, the next state must be an

unstable state, named c with output.

We must add a new row forstate b, where c is stable forx1x2 = 10

For x1 = 1, x2 must changethus the output is 0


62/99

Example At state (b),

x1x2 = 10 can not follow x1x2= 01.


When x1x2 = 00,

the next state must be anunstable state

For x1x2 = 00, we already

have a stable state (a). We

must consider this. From specification, z=0

when x1 = 0, thus go to a

with - output

Present

State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b a,- b,0 -,- d,-

c c,0

d d,0

When x1x2 = 11,

the next state must be anunstable state, named d with

output.

We must add a new row forstate d, where d is stable forx1x2 = 11

For x1 = 1, x2 must change

thus the output is 0


63/99

Example At state (c),

x1x2 = 01 can not follow x1x2 = 10.


When x1x2 = 00, From specification, z=0 when x1

= 0, thus go to a with - output

When x1x2 = 11,

Already have a stable state (d),we must consider this.

For x1 = 1, x2 changes from 0 to 1thus the output must be 1. Thuswe can not go to state (d)

the next state must be a new

unstable state, named e with output.

We must add a new row for statee, where e is stable for x1x2 = 11and the output is 1

Present

State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b a,- b,0 -,- d,-

c a,- -,- c,0 e,-

d d,0

e e,1


64/99

Example At state (d),

x1x2 = 00 can not follow x1x2 = 11.


When x1x2 = 01, From specification, z=0 when x1

= 0, thus go to b with - output

When x1x2 = 10,

Already have a stable state (c),we must consider this.

For x1 = 1, x2 changes from 1 to 0thus the output must be 1. Thuswe can not go to state (c)

the next state must be a new

unstable state, named fwith output.

We must add a new row for statef, where fis stable for x1x2 = 10and the output is 1

Present

State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b a,- b,0 -,- d,-

c a,- -,- c,0 e,-

d -,- b,- f,- d,0

e e,1

f f,1


65/99

Example At state (e),

x1x2 = 00 can not follow x1x2 =11.


When x1x2 = 01,

From specification, z=0 when

x1 = 0, thus go to b with -output

When x1x2 = 10,

Already have a stable state (c)and (f), we must consider this.

For x1 = 1, x2 changes from 1 to0 thus the output must be 1.Thus we can not go to state (c)

the next state must be unstablestate fwith output.

Present

State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b a,- b,0 -,- d,-

c a,- -,- c,0 e,-

d -,- b,- f,- d,0

e -,- b,- f,- e,1

f f,1


66/99

Example At state (f),

x1x2 = 01 can not follow x1x2 =10.


When x1x2 = 00,

From specification, z=0 when

x1 = 0, thus go to a with -output

When x1x2 = 11,

Already have a stable state (d)and (e), we must consider this.

For x1 = 1, x2 changes from 0 to1 thus the output must be 1.Thus we can not go to state (d)

the next state must be unstablestate e with output.

Present

State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b a,- b,0 -,- d,-

c a,- -,- c,0 e,-

d -,- b,- f,- d,0

e -,- b,- f,- e,1

f a,- -,- f,1 e,-


67/99


68/99

Implication chart

Find compatible pairs

Present

State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b a,- b,0 -,- d,-

c a,- -,- c,0 e,-

d -,- b,- f,- d,0

e -,- b,- f,- e,1

f a,- -,- f,1 e,-

cf

cf

cf

b

c

d

e

f

de

de

de

cfde

cf

de

a b c d e


69/99

Implication chart

Determine Maximal Compatible

cf

cf

cf

b

c

d

e

f

de

de

de

cfde

cf

de

a b c d e

Column List of Compatible Classes

e {e,f}

d {e,f}

c {e,f}

b {e,f}, {b,d}

a {e,f}, {b,d},{a,b},{a,c}

No single state is added sinceevery state already appear at leastonce.


70/99

Implication chart

Determine minimal collection of maximal compatible

Apply the concept of prime-implicant to reduce flow table

Column List of Compatible Classes

e {e,f}

d {e,f}

c {e,f}

b {e,f}, {b,d}

a {e,f}, {b,d},{a,b},{a,c}

a b c d e f

{a,b} x x

{a,c} x x *

{b,d} x x *

{e,f} x x *

Minimal collection of MC is {a,c} {b,d} {e,f}


71/99

Constructing Minimal Row Flow Table

Present

State

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Present

State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b a,- b,0 -,- d,-

c a,- -,- c,0 e,-

d -,- b,- f,- d,0

e -,- b,- f,- e,1

f a,- -,- f,1 e,-


72/99

Secondary State Assignment

Step 3. State Assignment

The goal is to avoid race

Present

State

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

State Assignment Possibility

(,) (,) (,)

Choose!

(,) (,)

y1\y2 0 1

0

1

Assignment: 00: 11

: 10


73/99

Constructing State Transition Table (Step 4)

Replace all stable state with its assignment

PresentState

Next State00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment: 00: 11

: 10

Present

State

Next State

00 01 10 11

: 00 00,0 00,0

: 11 11,0 11,0

: 10 10,1 10,1


74/99

Constructing State Transition Table

Now we need to replace the unstable states

PresentState

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment: 00: 11

: 10

Present

State

Next State

00 01 10 11

: 00 00,0 00,0

: 11 10,- 11,0 11,0

: 10 00,- 10,1 10,1

Remember if a state changes

more than 1 bit at a time we have a race

Input 00:Total State (00,11) (00,00)

Create a cycle(00,11) (00,10) (00,00)


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PresentState

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment: 00: 11

: 10

Present

State

Next State

00 01 10 11

: 00 00,0 10,- 00,0

: 11 10,- 11,0 11,0

: 10 00,- 11,- 10,1 10,1




Create a cycle(01,00) (01,10) (01,11)


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PresentState

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment: 00: 11

: 10

Present

State

Next State

00 01 10 11

: 00 00,0 10,- 00,0

: 11 10,- 11,0 10,- 11,0

: 10 00,- 11,- 10,1 10,1




No problem here!Only 1 bit need to change


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PresentState

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment: 00: 11

: 10

Present

State

Next State

00 01 10 11

: 00 00,0 10,- 00,0 10,-

: 11 10,- 11,0 10,- 11,0

: 10 00,- 11,- 10,1 10,1




No problem here!Only 1 bit need to change


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Constructing State Transition Table (variant 1)

Used the unused state 01

PresentState

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment: 00: 11

: 10

Present

State

Next State

00 01 10 11

: 00 00,0 00,0

: 11 01,- 11,0 11,0

: 10 00,- 10,1 10,1

01 00,-

Input 00:

Total State (00,11) (00,00)Create a cycle(00,11) (00,01) (00,00)


79/99


Used the unused state 01

PresentState

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment: 00: 11

: 10

Present

State

Next State

00 01 10 11

: 00 00,0 01,- 00,0 10,-

: 11 01,- 11,0 10,- 11,0

: 10 00,- 11,- 10,1 10,1

01 00,- 11,-

Input 01:

Total State (01,00) (01,11)Create a cycle(01,00) (01,01) (01,00)All other inputs are the same asbefore!


80/99


Create non-critical race

PresentState

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment: 00: 11

: 10

Present

State

Next State

00 01 10 11

: 00 00,0 00,0

: 11 00,- 11,0 11,0

: 10 00,- 10,1 10,1

01 00,-

Input 00:

Total State (00,11) (00,00)Non critical race(00,11) (00,01) (00,00)(00,11) (00,10) (00,00)


81/99


Create non-critical race

PresentState

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment: 00: 11

: 10

Present

State

Next State

00 01 10 11

: 00 00,0 11,- 00,0 10,-

: 11 00,- 11,0 10,- 11,0

: 10 00,- 11,- 10,1 10,1

01 00,- 11,-

Input 01:

Total State (01,00) (01,11)Non critical race(01,00) (01,01) (01,11)(01,00) (01,10) (01,11)All other input are the same!


82/99

Constructing State Transition Table (output)

Now we need to set the output of the unstable states

If for some stable state the output is 0 and after input

changes the resulting stable state the output is 0, then all

unstable state that might be encountered during the time

between the two stable state must have an output of 0.

The same for stable state with output of 1.

Present

State

Next State

00 01 10 11

: 00 00,0 10,0 00,0 10,- : 11 10,0 11,0 10,- 11,0

: 10 00,0 11,0 10,1 10,1

The unstable state (01,00) isreachable from (00,00) having anoutput 0 and eventually reaches

(01,11) which also have an outputof 0 then (01,00) must have anoutput of 0.The same for (00,11), (00,10) and(01,10)


83/99

Constructing State Transition Table (output)

What about the others?

Consider (11,11) (10,11) (10,10) (11,11) have an output of 0

(10,10) have an output of 1

The output of (10,11) can be left unspecified (dont care) as itprovides more flexibility in implementation as it does not violatesthat no more than a single output can change.

Present

State

Next State

00 01 10 11

: 00 00,0 10,0 00,0 10,- : 11 10,0 11,0 10,- 11,0

: 10 00,0 11,0 10,1 10,1

Note: no more than a single outputcan change at a time!

You can do the same for variant 1and 2


84/99

Determine Logic Equations (Step 5)

Present

Statey1y2

Next State

Y1Y2,z00 01 10 11

: 00 00,0 10,0 00,0 10,-

: 11 10,0 11,0 10,- 11,0

: 10 00,0 11,0 10,1 10,1

y1y2\x1x2 00 01 11 10

00 0 1 1 0

01 - - - -

11 1 1 1 1

10 0 1 1 1

Y1

y1y2\x1x2 00 01 11 10

00 0 0 0 0

01 - - - -

11 0 1 1 0

10 0 1 0 0

Y2

y1y2\x1x2 00 01 11 1000 0 0 - 0

01 - - - -

11 0 0 0 -

10 0 0 1 1

z

11221yxyxY ++=

121222yxxyxY +=

211yyxz =

( )


85/99

Realize logic equation (Step 6)

11221 yxyxY ++=

121222yxxyxY +=

211yyxz =

Delay

dt

Delaydt

Y2

Y1

y1

y2

x1

x2

z

l l ( )


86/99


With SR Latch?

11221yxyxY ++=

121222yxxyxY +=

211yyxz =

SR Excitation Property00 SR 0d01 SR 1010 SR 0111 SR d0

Present

Statey1y2

Next State

Y1Y2,z

00 01 10 11

: 00 00,0 10,0 00,0 10,-

: 11 10,0 11,0 10,- 11,0

: 10 00,0 11,0 10,1 10,1

Present

State

y1y2

Next State

(S1R1,S2R2),z

00 01 10 11

: 00 (0d,0d),0 (10,0d),0 (0d,0d),0 (10,0d),d

: 11 (d0,01),0 (d0,d0),0 (d0,01),d (d0,d0),0

: 10 (01,0d),0 (d0,10),0 (d0,0d),1 (d0,0d),1

li l i i (S 6)


87/99


Present

Statey1y2

Next State

(S1R1,S2R2),z

00 01 10 11

: 00 (0d,0d),0 (10,0d),0 (0d,0d),0 (10,0d),d

: 11 (d0,01),0 (d0,d0),0 (d0,01),d (d0,d0),0

: 10 (01,0d),0 (d0,10),0 (d0,0d),1 (d0,0d),1

y1y2\x1x2 00 01 11 10

00 0 1 1 0

01 d d d d

11 d d d d

10 0 d d d

S1

21xS =

y1y2\x1x2 00 01 11 10

00 d 0 0 d

01 d d d d

11 0 0 0 0

10 1 0 0 0

R1

2211yxxR =

R li l i i (S 6)


88/99


Present

Statey1y2

Next State

(S1R1,S2R2),z00 01 10 11

: 00 (0d,0d),0 (10,0d),0 (0d,0d),0 (10,0d),d

: 11 (d0,01),0 (d0,d0),0 (d0,01),d (d0,d0),0

: 10 (01,0d),0 (d0,10),0 (d0,0d),1 (d0,0d),1

y1y2\x1x2 00 01 11 10

00 0 0 0 0

01 d d d d

11 0 d d 0

10 0 1 0 0

S2

1212yxxS =

y1y2\x1x2 00 01 11 10

00 d d d d

01 d d d d

11 1 0 0 1

10 d 0 d d

R2

22xR =

R li l i i (S 6)


89/99


21xS =

2211yxxR =

1212yxxS =

22xR =

211 yyxz =

Q

QSET

CLR

S

R

Q

QSET

CLR

S

R

zx1

x2

D it lf


90/99

Do it yourself

Design a two input (x1, x2) and two output (z1,z2) circuit

where,

z1z2 =00 when x1x2=00

Output 10 will be produced following the occurrence of 00-01-

11 input sequence, and the output goes back to 00 after a 00

input. Output 01 will be produced following the occurrence of 00-10-

11 input sequence, and the output goes back to 00 after a 00

input.

St 1 C t t P i iti Fl T bl


91/99

Step 1: Construct Primitive Flow Table

Present

State

Input State (x1 x2)

00 01 11 10

a a/00 b/-- -/-- c/--

b a/-- b/00 d/-- -/--

c a/-- -/-- e/-- c/00

d -/-- f/-- d/10 g/--

e -/-- h/-- e/01 i/--

f a/-- f/10 d/-- -/--

g a/-- -/-- d/-- g/10

h a/-- h/01 e/-- -/--i a/-- -/-- e/-- i/01

Present

State

Input State (x1 x2)

00 01 11 10

a a/00 b/00 -/-- c/00

b a/00 b/00 d/-0 -/--

c a/00 -/-- e/0- c/00

d -/-- f/10 d/10 g/10

e -/-- h/01 e/01 i/01

f a/-0 f/10 d/10 -/--

g a/-0 -/-- d/10 g/10

h a/0- h/01 e/01 -/--i a/0- -/-- e/01 i/01

It might be easier if we assigned the output of the unstable states.So that we correctly reduced the flow table.

St 2 C t t I li ti h t


92/99

Step 2: Construct Implication chart

Present

State

Input State (x1 x2)

00 01 11 10

a a/00 b/00 -/-- c/00

b a/00 b/00 d/-0 -/--

c a/00 -/-- e/0- c/00

d -/-- f/10 d/10 g/10

e -/-- h/01 e/01 i/01

f a/-0 f/10 d/10 -/--

g a/-0 -/-- d/10 g/10

h a/0- h/01 e/01 -/--i a/0- -/-- e/01 i/01

e

f

g

h

i

a b c d e f g h

d

c

b

de

St 2 Fi d M i l C tibl


93/99

Step 2: Find Maximal Compatibles

e

f

g

h

i

a b c d e f g h

d

c

b

de

column List of Maximal Compatible

h {h,i}

g {h,i}

f {h,i}{f,g}

e {e,h,i}{f,g}

d {e,h,i}{d,f,g}

c {e,h,i}{d,f,g}{c,h}

b {e,h,i}{d,f,g}{c,h}{b,g}

a {e,h,i}{d,f,g}{c,h}{b,g}{a,b}{a,c}


94/99

Step 2 Red ced Flo Table


95/99

Step 2: Reduced Flow Table

Reassignment: {a,b} {d,f,g} {a,c} {e,h,i}

PresentState Input State (x1 x2)

00 01 11 10

/00 /00 /-0 /00

/-0 /10 /10 /10

/00 /00 /0- /00

/0- /01 /01 /01

Row 1 includes two states and .Any unstable state could go to either one of them.

Present

State

Input State (x1 x2)

00 01 11 10

a a/00 b/00 -/-- c/00

b a/00 b/00 d/-0 -/--

c a/00 -/-- e/0- c/00

d -/-- f/10 d/10 g/10

e -/-- h/01 e/01 i/01

f a/-0 f/10 d/10 -/--

g a/-0 -/-- d/10 g/10

h a/0- h/01 e/01 -/--i a/0- -/-- e/01 i/01

Step 3: Secondary State Assignment


96/99

Step 3: Secondary State Assignment

Assignment: 00 01 10

11PresentState

Input State (x1 x2)

00 01 11 10

/00 /00 /-0 /00

/-0 /10 /10 /10

/00 /00 /0- /00

/0- /01 /01 /01

Look at row 4 column 1,transition from (11 00)

Need to change (11 10)

0 1

0

1

Present

State

Input State (x1 x2)

00 01 11 10

/00 /00 /-0 /00

/-0 /10 /10 /10

/00 /00 /0- /00

/0- /01 /01 /01

Step 4: Constructing Transition Table


97/99

Step 4: Constructing Transition Table

Assignment: 00 01 10

11PS(y1 y2)

Input State (x1 x2)

00 01 11 10

00 00/00 00/00 01/-0 10/00

01 00/-0 01/10 01/10 01/10

10 10/00 00/00 11/0- 10/00

11 10/0- 11/01 11/01 11/01

0 1

0

1

Present

State

Input State (x1 x2)

00 01 11 10

/00 /00 /-0 /00

/-0 /10 /10 /10

/00 /00 /0- /00

/0- /01 /01 /01

Step 4: Constructing Excitation and Output Table


98/99

Step 4: Constructing Excitation and Output Table

PS

(y1 y2)

Next State (Y1 Y2)

00 01 11 10

00 00 00 01 10

01 00 01 01 01

10 10 00 11 10

11 10 11 11 11

Output (z1 z2)

00 01 11 10

00 00 -0 00

-0 10 10 10

00 00 0- 00

0- 01 01 01

Step 5: Next State and Output Equations


99/99

Step 5: Next State and Output Equations

y2

y1

00 01 11 10

00

01

11

10

0 0 0 1

0 0 0 0

1 1 1 1

1 0 1 1

x1x2y2

y1

00 01 11 10

00

01

11

10

0 0 1 0

0 1 1 1

0 1 1 1

0 0 1 0

x1x2

Y1 Y2

y2

y1

00 01 11 10

00

01

11

10

0 0 d 0

d 1 1 1

0 0 0 0

0 0 0 0

x1x2y2

y1

00 01 11 10

00

01

11

10

0 0 0 0

0 0 0 0

d 1 1 1

0 0 d 0

x1x2

= + + +

= + +

1 1 2 1 1 2 1 1 2 2

2 1 2 1 2 2 2

Y y y x y x y x x y

Y x x x y x y

=

=

1 1 2

2 1 2

z y yz y y

15 A Synchronous Machine

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Transcript of 15 A Synchronous Machine