15-410, S’04 - 1 - Virtual Memory #1 Feb. 23, 2004 Dave Eckhardt Bruce Maggs L17_VM1 15-410...
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Transcript of 15-410, S’04 - 1 - Virtual Memory #1 Feb. 23, 2004 Dave Eckhardt Bruce Maggs L17_VM1 15-410...
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15-410, S’04- 1 -
Virtual Memory #1Feb. 23, 2004
Dave EckhardtDave Eckhardt
Bruce MaggsBruce Maggs
L17_VM1
15-410“...The only way to win is not to play...”
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15-410, S’04- 1 -
Synchronization
Mid-termMid-term Wednesday, 19:00, 7500 Wean Does not cover today's lecture
Final Exam list postedFinal Exam list posted You must notify us of conflicts in a timely fashion
Summer internship with SCS Facilities?Summer internship with SCS Facilities?
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15-410, S’04- 1 -
Outline
The Problem: logical vs. physicalThe Problem: logical vs. physical
Contiguous memory mappingContiguous memory mapping
FragmentationFragmentation
PagingPaging Type theory Several mapping functions
TLBTLB
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15-410, S’04- 1 -
Logical vs. Physical
It's all about address spacesIt's all about address spaces Generally a complex issue
IPv4 IPv6 is mainly about address space exhaustion
ReviewReview Combining .o's changes addresses
But what about But what about twotwo programs? programs?
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15-410, S’04- 1 -
Every .o uses same address space
code
data
bss
code
data
bss
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15-410, S’04- 1 -
Combining .o's Changes Addresses
code
data
bss
code
data
bss
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15-410, S’04- 1 -
What about two programs?
code
data
bss
00010000
00010200
00010300
stack FFFFF000
code
data
bss
00010000
00010100
00010300
stack FFFFE000
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15-410, S’04- 1 -
Logical vs. Physical Addresses
Logical addressLogical address Each program has its own address space
fetch: address data store: address, data .
As envisioned by programmer, compiler, linker
Physical addressPhysical address Where your program ends up in memory They can't all be loaded at 0x10000!
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15-410, S’04- 1 -
Reconciling Logical, Physical
Ok, load programs at Ok, load programs at differentdifferent addresses addresses Requires using linker to “relocate one last time” Done by some old mainframe OSs Slow, complex, or both
Programs can Programs can take turnstake turns in memory in memory Requires swapping programs out to disk Very slow
We are computer scientists!We are computer scientists! Insert a level of indirection Well, get the ECE folks to do it for us
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15-410, S’04- 1 -
Type Theory
Physical memory behaviorPhysical memory behavior fetch: address data store: address, data .
Process thinks of memory as...Process thinks of memory as... fetch: address data store: address, data .
Goal: each process has “its own memory”Goal: each process has “its own memory” fetch: process-id (address data) store: process-id (address, data . )
What What reallyreally happens happens process-id (virtual-address physical-address)
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15-410, S’04- 1 -
Simple Mapping Functions
P1P1If V > 8191 ERROR
Else P = 1000 + V
P2P2If V > 16383 ERROR
Else P = 9292 + V
Address space ===Address space === Base address Limit
Process 3
Process 2
Process 1
OS Kernel
0
16383
9292
25675
08191
10009291
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15-410, S’04- 1 -
Contiguous Memory Mapping
Processor contains two Processor contains two control registerscontrol registers Memory base Memory limit
Each memory access checksEach memory access checksIf V < limit P = base + V;Else ERROR /* what do we call this error? */
Context switchContext switch Save/load registers Load process's base, limit registers
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15-410, S’04- 1 -
Problems with Contiguous Allocation
How do we How do we growgrow a process? a process? Must increase “limit” value Cannot expand into another process's memory! Must move entire address spaces around
Very expensive
FragmentationFragmentation New processes may not fit into unused memory “holes”
Partial memory residencePartial memory residence Must entire program be in memory at same time?
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15-410, S’04- 1 -
Can We Run Process 4?
Process exit creates Process exit creates “holes”“holes”
New processes may be New processes may be too largetoo large
May require moving entire May require moving entire address spacesaddress spaces
Process 3
Process 4
OS Kernel
Process 1
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15-410, S’04- 1 -
External Fragmentation
Free memory in small Free memory in small chunkschunks
Doesn't fit large objectsDoesn't fit large objects
Can disable lots of Can disable lots of memorymemory
Can fixCan fix Costly “compaction”
Process 4
Process 1
OS Kernel
Process 2
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15-410, S’04- 1 -
Internal Fragmentation
Allocators often round upAllocators often round up 8K boundary (some
power of 2!)
Some memory is wasted Some memory is wasted insideinside each segment each segment
Can't fix via compactionCan't fix via compaction
Effects often non-fatalEffects often non-fatal
Process 3
Process 4
Process 1
OS Kernel
0
8192
11009292
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15-410, S’04- 1 -
Swapping
Multiple user processesMultiple user processes Sum of memory demands > system memory Goal: Allow each process 100% of system memory
Take turnsTake turns Temporarily evict process(es) to disk
Not runnable Blocked on implicit I/O request (e.g., “swapread”)
“Swap daemon” shuffles process in & out Can take seconds per process
Modern analogue: laptop suspend-to-disk
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15-410, S’04- 1 -
Contiguous Allocation Paging
Solve multiple problemsSolve multiple problems Process growth problem Fragmentation compaction problem Long delay to swap a whole process
Divide memory more finelyDivide memory more finely Page = small region of virtual memory (4K) Frame = small region of physical memory [I will get this wrong, feel free to correct me]
Key idea!!!Key idea!!! Any page can map to (occupy) any frame
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15-410, S’04- 1 -
Per-process Page Mapping
P0 code 0
OS Kernel
P1 code 0P0 data 0P1 data 0P1 stack 0P0 stack 0P1 data 1P0 code 1
P0 code 0P0 code 1P0 data 0P0 stack 0
P1 code 0P1 data 0P1 data 1P1 stack 0
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15-410, S’04- 1 -
Benefits of Paging
Process growth problemProcess growth problem Any process can use any free frame for any purpose
Fragmentation compaction problemFragmentation compaction problem Process doesn't need to be contiguous
Long delay to swap a whole processLong delay to swap a whole process Swap part of the process instead!
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15-410, S’04- 1 -
Partial Residence
P0 code 0
OS Kernel
[free]P0 data 0P1 data 0P1 stack 0P0 stack 0P1 data 1
[free]
P0 code 0P0 code 1P0 data 0P0 stack 0
P1 code 0P1 data 0P1 data 1P1 stack 0
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15-410, S’04- 1 -
New Data Structure
Contiguous allocationContiguous allocation Each process described by (base,limit)
PagingPaging Each page described by (base,limit)?
Pages typically one size for whole system Each page described by base address Arbitrary page frame mapping requires some work
Abstract data structure: “map” Implemented as...
» Linked list?» Array?» Hash table?» Splay tree?????
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15-410, S’04- 1 -
Page Table Options
Linked listLinked list VP time gets longer for large addresses!
ArrayArray Constant time access Requires contiguous memory for table
Hash tableHash table Vaguely-constant-time access Not really bounded though
Splay treeSplay tree Excellent amortized expected time Lots of memory reads & writes possible for one mapping Probably impractical
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15-410, S’04- 1 -
Page Table Array
Page
....f29f34....
Frame
Page table array
Page 3Page 2Page 1Page 0
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15-410, S’04- 1 -
Paging – Address Mapping
Logical Address
Page Offset
4K page size 12 bits
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15-410, S’04- 1 -
Paging – Address Mapping
Logical Address
Page Offset
....f29f34....
Frame
Page table
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15-410, S’04- 1 -
Paging – Address Mapping
Logical Address
Page Offset
....f29f34....
Frame Offset
Copy
Page table
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15-410, S’04- 1 -
Paging – Address Mapping
Logical Address
Page Offset
....f29f34....
Frame Offset
Page tablePhysical Address
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15-410, S’04- 1 -
Paging – Address Mapping
User viewUser view Memory is a linear array
OS viewOS view Each process requires N frames
Fragmentation?Fragmentation? Zero external fragmentation Internal fragmentation: maybe average ½ page
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15-410, S’04- 1 -
Bookkeeping
One page table for each processOne page table for each process
One frame tableOne frame table Manages free frames Remembers who owns a frame
Context switchContext switch Must “activate” process's page table
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15-410, S’04- 1 -
Hardware Techniques
Small number of pages?Small number of pages? “Page table” can be a few registers
Typical caseTypical case Large page tables, live in memory
Where? Processor has “Page Table Base Register”
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Double trouble?
Program requests memory accessProgram requests memory access
Processor makes Processor makes twotwo memory accesses! memory accesses! Split address into page number, intra-page offset Add to page table base register Fetch page table entry (PTE) from memory Add frame address, intra-page offset Fetch data from memory
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15-410, S’04- 1 -
Translation Lookaside Buffer (TLB)ProblemProblem
Cannot afford double memory latency
Observation - “locality of reference”Observation - “locality of reference” Program accesses “nearby” memory
SolutionSolution Cache virtual-to-physical mappings
Small, fast on-chip memory Don't forget context switch!
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Page Table Entry (PTE) mechanicsPTE flagsPTE flags
Protection Read/Write/Execute bits
Valid bit Dirty bit
Page Table Length Register (PTLR)Page Table Length Register (PTLR) Programs don't use entire virtual space On-chip register detects out-of-bounds reference
Allows small PTs for small processes
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Page Table Structure
ProblemProblem Assume 4 KByte pages, 4 Byte PTEs Ratio: 1024:1
4 GByte virtual address (32 bits) 4 MByte page table For each process!
Key observationKey observation Each process page table is a sparse mapping Many pages are not backed by frames
Address space is sparsely used» Enormous “hole” between bottom of stack, top of heap» Often occupies 99% of address space!
Some pages are on disk instead of in memory
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15-410, S’04- 1 -
Page Table Structure
Key observationKey observation Each process page table is a sparse mapping Page tables are not randomly sparse
Occupied by sequential memory regions Text, rodata, data+bss, stack
We are computer scientists!We are computer scientists! Insert a level of indirection Well, get the ECE folks to do it for us
Multi-level page tableMulti-level page table Page directory maps large chunks of address space to... ...Page tables, which map to frames
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15-410, S’04- 1 -
Multi-level page table
P1 Offset
....f29f34f25
PageTables
....f99f87....
P2 ....f08f07....
PageDirectory
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15-410, S’04- 1 -
Multi-level page table
P1 Offset
....f29f34f25
PageTables
....f99f87....
P2 ....f08f07....
PageDirectory
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15-410, S’04- 1 -
Multi-level page table
P1 Offset
....f29f34f25
PageTables
....f99f87....
P2 ....f08
f07....
PageDirectory
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15-410, S’04- 1 -
Multi-level page table
P1 Offset
....f29f34f25
PageTables
....f99f87....
P2 ....f08
f07....
PageDirectory
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15-410, S’04- 1 -
Multi-level page table
P1 Offset
....f29f34f25
PageTables
....f99f87....
P2
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15-410, S’04- 1 -
Multi-level page table
P1 Offset
....f29f34f25
f34
PageTables
....f99f87....
P2
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15-410, S’04- 1 -
Multi-level page table
P1 Offset
....f29f34f25
f34 Offset
PageTables
....f99f87....
P2
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Sparse Mapping?
Assume 4 KByte pages, 4-byte PTEsAssume 4 KByte pages, 4-byte PTEs Ratio: 1024:1
4 GByte virtual address (32 bits) 4 MByte page table
Now assume page directory with 4-byte PDEsNow assume page directory with 4-byte PDEs 4-megabyte page table becomes 1024 4K page tables Single 1024-entry (4Kbyte) page directory can cover them
Sparse address space...Sparse address space... ...means most page tables contribute nothing to mapping... ...all of them are full of “empty” entries
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15-410, S’04- 1 -
Sparse Mapping?
Page directory can be sparsePage directory can be sparse Contains pointers only to non-empty page tables
Common caseCommon case Need 2 or 3 page tables
One or two map code, data One maps stack
Page directory has 1024 slots Three are filled in with valid pointers Remainder are “not present”
ResultResult 3 page tables 1 page directory Map address space with 16Kbyte, not 4Mbyte
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Segmentation
Physical memory is (mostly) linearPhysical memory is (mostly) linear
Is virtual memory linear?Is virtual memory linear? Typically a set of regions
“Module” = code region + data region Region per stack Heap region
Why do regions matter?Why do regions matter? Natural protection boundary Natural sharing boundary
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Segmentation: Mapping
Seg # Offset
<=
Physical AddressLimit Base
+
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Segmentation + Paging
80386 (does it 80386 (does it allall!)!) Processor address directed to one of six segments
CS: Code Segment, DS: Data Segment– CS register holds 16-bit selector
32-bit offset within a segment -- CS:EIP Descriptor table maps selector to segment descriptor Offset fed to segment descriptor, generates linear address If linear address not in TLB... Linear address fed through page directory, page table
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x86 Type Theory
Instruction Instruction segment selector segment selector [PUSHL specifies selector in %SS]
Process Process (selector (selector (base,limit) ) (base,limit) ) [Global,Local Descriptor Tables]
Segment, address Segment, address linear address linear address
TLB: linear address TLB: linear address physical address or... physical address or...
Process Process (linear address high (linear address high page table) page table) [Page Directory Base Register, page directory indexing]
Page Table: linear address middle Page Table: linear address middle frame address frame address
Memory: frame address, offset Memory: frame address, offset ... ...
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Is there another way?
That seems That seems really complicatedreally complicated Is that hardware monster really optimal for every OS and
program mix? “The only way to win is not to play?”
Could we have Could we have nono page tables? page tables?
How would hardware map virtual to physical???How would hardware map virtual to physical???
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Software-loaded TLBs
ReasoningReasoning We need a TLB for performance reasons OS defines each process's memory structure
Which memory ranges, permissions Why impose a semantic middle-man?
ApproachApproach TLB contains small number of mappings OS knows the rest TLB miss generates special trap OS quickly fills in correct vp mapping
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Software TLB features
Mapping entries can be computed many waysMapping entries can be computed many ways Imagine a system with one process memory size
TLB miss becomes a matter of arithmetic
Mapping entries can be locked in TLBMapping entries can be locked in TLB Great for real-time systems
Further readingFurther reading http://yarchive.net/comp/software_tlb.html
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Summary
Processes emit virtual addressesProcesses emit virtual addresses segment-based or linear
A magic process maps virtual to physicalA magic process maps virtual to physical
No, it's No, it's notnot magic magic Address validity verified Permissions checked Mapping may fail temporarily (trap handler) Mapping results cached in TLB
Data structures determined by access patternsData structures determined by access patterns Most address spaces are sparsely allocated