INTRODUCTION

GRAPHENE TRANSISTOR:-

A graphene transistor is a nanoscale device based on

graphene, a component of graphite with electronic properties far superior to those of silicon.

The device is a single-electron transistor, which means that a single electron passes through it

at any one time. A research team led by Professor Andre Geim of the Manchester Centre for

Mesoscience and Nanotechnology built a graphene transistor and described it in the March

2007 issue of Nature magazine. Scientists have predicted that graphene transistors could

scale to transistor channels as small as two nanometers (nm) with terahertz speeds. The base

of the graphene transistor is graphene

Now before going to discuss about grapheme

transistor(carbon nanotubes) lets take a brief introduction about GRAPHENE.

GRAPHENE

Introduction:-

Graphene is a one-atom-thick planar sheet of sp 2 -bonded carbon atoms that are

densely packed in a honeycomb crystal lattice. It can be viewed as an atomic-scale chicken

wire made of carbon atoms and their bonds. The name comes from GRAPHITE + -

ENE; graphite itself consists of many graphene sheets stacked together. Carbon is one of the

most versatile chemical elements. Because it can form single, double and triple bonds, it

forms thousands of chemical compounds, and has numerous elemental structures, or

allotropes. The most common allotropes of carbon are diamond and graphite. Diamond

consists of carbon atoms single-bonded to four other carbon atoms producing a tetrahedral

crystal lattice. Its structure leads to its extreme hardness and thermal conductivity, but

diamond is a very poor electrical conductor. In contrast, graphite consists of stacked layers

of carbon sheets. Within an individual carbon sheet, known as graphene, the carbon atoms

are sp2 hybridized and form a planar hexagonal lattice. The sp2 hybridization means that the

carbons are σ -bonded in the plane, but are also π -bonded above and below the plane.

Graphene thus possesses one of the strongest bonds in nature and has a very high tensile

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strength. Graphene’s perpendicular p-orbitals lead to electron delocalization because there is

no distinction between neighboring π bonds, as indicated in Figure below.

Fig. Aromatic hydrocarbons like benzene shown here, share electrons in the p-orbitals with

many neighboring atoms.

This conjugated π orbital system permits the electrons to travel freely above and

below the plane of carbon atoms with minimal scattering. Because of the minimal scattering

and strong delocalization of the electrons, graphite is a good conductor along the plane.

However, in graphite, electrostatic forces bind the layers together only very weakly, and

graphite is a very soft mineral. In addition, the other layers interfere with the behavior of the

single sheets, even if not strongly. An ideal system would be to study free single-layer

graphene, but until a few years ago, two-dimensional systems like free graphene were

believed to be impossible.

In recent years, the two most familiar allotropes of carbon have been joined by a

number of newly discovered graphene-like materials. The first major graphene-related

substance discovered was C60, also known as buckminsterfullerene, buckyball, and fullerene,

a soccer-ball-like configuration of carbon atoms found in common lamp soot and known to

be very stable. Soon, the scientific community encountered similar fullerene-type carbon

structures called a carbon nanotubes. Carbon nanotubes are needle-like tubes of rolled up

graphene sheets that exhibit many unusual and useful properties such as extreme tensile

strength and high conductivity. .

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Discovery of Graphene

Graphene, though only recently confirmed experimentally, has been discussed in

conjunction with graphite for many years. Many of its properties had long been studied in

conjunction with the properties of graphite, including its band structure. For example,

graphene was predicted to be a semiconductor with no band gap at the corners of the

reciprocal lattice using the tight-binding approximation. But theoretical studies of graphene

were historically limited entirely to approximations for the properties of graphite. Graphene

as a free substance was largely ignored as a purely academic substance because it was

accepted that thermodynamic stresses prevented the existence of any free one- or two-

dimensional crystals. Additionally, there had been previous attempts to achieve two-

dimensional crystals, but in all cases, it was confirmed that reducing the thickness made the

crystals melt at increasingly low temperatures and it was agreed that two dimensional crystals

were too unstable to exist in a free state. A possible explanation for the disparity between

theory predicting the non-existence of two-dimensional crystals and their experimental

confirmation may be that the graphene monolayers are only approximately two-dimensional

and owe some of their stability to rippling perpendicular to the plane.

Fig. A representation of the rippling of 2D graphene into 3D. The red arrows are ~800nm

long.

But in 2004, graphene was produced experimentally, defying decades of predictions

that it could not exist apart from a crystalline substrate. The procedure for acquiring the

monolayer graphene is comically simple: essentially, graphene is removed from a graphite

sample by using clear adhesive tape to remove layers from graphite. The tape is then stuck to

new clean tape several times to remove additional layers. After a few times, the tape is

dissolved and the graphite remains are examined to sort the graphene monolayers from the

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ultrathin graphite films. The difficulty is in sorting the graphene from the graphite.

Fortunately, different thicknesses of graphite are distinguishable under optical microscopy on

a special silicon substrate. The adhesive tape technique produces extremely high quality

crystals of up to 100 micrometers in length, more than sufficient for most laboratory

experiments. And even better, the raw materials are very cheap.

Graphene’s Charge Carriers Are Relativistic

But why is there such interest in graphene? Aside from the obvious interest in the

novelty of a two-dimensional crystal, graphene crystals exhibit unusual electrical properties

that may prove useful both theoretically and practically. In particular, graphene’s charge

carriers are very unusual in that they behave like massless Driac fermions and are most

effectively described by the Dirac equation rather than the non-relativistic Schrödinger

equation:

EN = [2ehc2 B(N+1/2± 1/2)]1/2.

Fig. Formation of 0D, 1D and 3D carbon materials from Graphene.

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Anomalous Quantum Hall Effect in Graphene

In addition, graphene also exhibits an anomalous quantum hall effect. In classical

electromagnetism, the Hall effect arises when a magnetic field is applied perpendicular to the

surface of a solid carrying a current parallel to the surface. The Lorentz force causes positive

and negative charges to build up on opposite sides of the solid, parallel to the current,

producing a potential difference known as the Hall voltage. The direction the voltage points

determines the charge of the charge carriers in the material. The quantum Hall effect (QHE)

is identical to the classical Hall effect except that the Hall voltage (and consequently the Hall

resistivity and the Hall conductivity) occurs only in discrete steps equal to an integer times

e2/h. In addition to the integer quantum Hall effect, there is another effect known as the

fractional quantum Hall effect in which the Hall conductivity is equal to e2/h times a rational

fraction that is less well understood. In the presence of a magnetic field, graphene produces

yet another quantum Hall effect known as an anomalous quantum Hall effect. In the case of

graphene, the Hall conductivity occurs in discrete integer steps like the conventional QHE,

but is shifted by one-half of an integer as shown below in figure .

Figure . A plot of the Hall

conductivity σ xy (red) and

the Hall resistivity ρ xy

(green) as a function of

carrier concentration.

Graphene is an ideal

system for examining the quantum Hall effect for a number of reasons. First, graphene

samples are available in such purity that the charge carrier concentration can be tuned

continuously from high concentrations of electrons to high concentrations of holes simply by

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changing the gate voltage. Second, the purity of the graphene samples is so high that the

QHE can be observed even at room temperature, whereas most materials only exhibit the

QHE at much lower temperatures. Finally, graphene’s anomalous quantum Hall effect, by

being shifted by half compared to most systems, exhibits non-zero conductivity even as the

charge carriers change from electrons to holes (the neutrality point or the Dirac point). For

most materials, as the charge carrier concentration tends towards zero, so does the

conductivity, so that there is a metal to insulator transition at no temperatures. But graphene

has shown no signs of a metal-insulator transition even down to liquid helium temperatures.

The Future Of Graphene

Aside from the anomalous quantum Hall effect, one of the most exciting prospects for

graphene is that it may eventually prove useful in electronic applications. Graphene’s high

conductivity and its unusual electronic properties may lead to unexpected advances in

processor and electronic technologies. After carbon nanotubes have so far failed to

revolutionize the field, scientists are cautious in advertising the possible future applications of

graphene. For graphene, it is too early to tell whether graphene will significantly affect the

field of commercial electronics, but it’s small scale and unusual properties may contribute to

the development of nanoscopic electronic components or quantum computing. Graphene has

been used to produce a functional transistor even though this initial proof of concept

transistor leaks electrons and is highly inefficient.

Scientists acknowledge that graphene will be an important material in future

technologies. It might be used to store hydrogen in fuel cells or in batteries as electrodes. It

may serve a use in the production of ultra-thin fabrics that require great strength. If glues are

used between the graphene layers, it might be possible to assemble very strong materials. Its

chemistry can be controlled to change its electrical properties to be conducting, insulating or

semiconducting. It may even prove useful in the possible development of quantum

computing. Graphene’s immense potential is especially exciting considering how easy and

cheap it is to produce.

Graphene transistor

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Transistors less than one-quarter the size of the tiniest silicon ones - and potentially

more efficient - can be made using sheets of carbon just one-tenth of a nanometre thick,

research shows. Unlike other experimental nanoscopic transistors, the new components

require neither complex manufacturing nor cryogenic cooling. The transistors are made of

graphene, a sheet of carbon atoms in a flat honeycomb arrangement. Graphene makes

graphite when stacked in layers, and carbon nanotubes when rolled into a tube. Graphene

also conducts electricity faster than most materials since electrons can travel through in

straight lines between atoms without being scattered. This could ultimately mean faster, more

efficient electronic components that also require less power.

Fig. Graphene Transistor is built entirely from sheets of graphene

The first graphene transistor was demonstrated in 2004. But this leaked current and

could never switch it off, because electrons hopped too easily between the carbon atoms. We

have now made a graphene transistor that does not leak current that can control the flow of

just a single electron efficiently. The leak-free transistor is made from a "nano-ribbon" of

graphene less than 10 nanometres wide and just a single carbon atom thick (0.1 nm). The

device not only works at room temperature but, unlike other transistors of a similar size, it is

relatively simple to make. The ribbon at the heart of the device, as well as the surrounding

connections, can be cut from a graphene sheet using electron beam lithography - the same

method used to make silicon devices.

Operation of Graphene Transistors at GHz Frequencies

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Top-gated graphene transistors operating at high frequencies (GHz) have been

fabricated. The work represents a significant step towards the realization of graphene-based

electronics for high-frequency applications. Graphene is a two-dimensional (2D) material

with great potential for electronics with essentially the same lattice structure as an unwrapped

carbon nanotube, graphene shares many of the advantages of nanotubes, such as the highest

intrinsic carrier mobility at room temperature of any known materials. This makes these

carbon-based electronic materials particularly promising for high-frequency circuits.

However, due to the high impedance of a single carbon nanotube transistor, high-frequency

properties of nanotubes were investigated indirectly using various mixing techniques and

direct ac measurements of these devices at GHz frequencies were realized only recently

enabled by the larger device current in nanotube arrays. In contrast, one distinct advantage of

graphene lies in its 2D nature, so that the drive current of a graphene device, in principle, can

be easily scaled up by increasing the device channel width. This width scaling capability of

graphene is of great significance for realizing high-frequency graphene devices with

sufficient drive current for large circuits and associated measurements. Furthermore, the

planar graphene allows for the fabrication of graphene devices and even integrated circuits

utilizing well-established planar processes in the semiconductor industry. Recently, it was

shown that graphene devices can exhibit current gain in the microwave frequency range .

Despite intense activities on graphene research, the intrinsic high-frequency transport

properties of graphene transistors have not been systematically studied.

This topic presents the first comprehensive experimental studies on the high-

frequency response of top-gated graphene transistors for different gate voltages and gate

lengths. The intrinsic current gain of the graphene transistors was found to decrease with

increasing frequency and follows the ideal 1/f dependence expected for conventional FETs.

This not only verifies the ac measurement and de-embedding procedures used here for

extracting the intrinsic high frequency properties, but also suggests a conventional FET-like

behavior for grapheme transistors. The cutoff frequency fT deduced from S parameter

measurements exhibits strong gate voltage dependence and is proportional to the dc

transconductance. The peak cut-off frequency is found to be inversely proportional to the

square of the gate length, and for a gate length of 150 nm, a peak fT as high as 26 GHz is

obtained.

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Fig. A Optical image of the device layout

Fig. B

Fig. C Schematic cross-section of the graphene transistor

Fig. 1. Device layout of graphene field-effect transistors

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Figure 1 shows the device layout of graphene field-effect transistors with probe pads

designed for high-frequency measurements. Graphene was prepared by mechanical

exfoliation on a high resistivity Si substrate (>10 kΩ cm) covered by a layer of 300nm⋅

thermal SiO2, and Raman spectroscopy was employed to count the number of graphene

layers. Fig. 1(B) shows the optical image of a graphene flake, where the region on the left

was identified to be single-layer graphene. Source and drain electrodes made of 1 nm Ti as

the adhesion layer and 50 nm-thick Pd were defined by e-beam lithography and lift-off. A 12-

nm-thick Al2O3 layer was then deposited by atomic layer deposition (ALD) at 250ºC as the

gate insulator. In order to form a uniform coating of oxide on graphene, a functionalization

layer consisting of 50 cycles of NO2- TMA (trimethylaluminum) was first deposited prior to

the growth of gate oxide. This NO2-TMA functionalization layer was essential for the ALD

process to achieve thin (<10 nm) gate dielectrics on grapheme without producing pinholes

that cause gate leakage. The dielectric constant of ALD-grown Al2O3 is determined by C-V

measurements and found to be about 7.5. Lastly, 10nm/50nm Pd/Au was deposited and

patterned to form the top gate.

As shown in Fig. 1(B), the source electrodes were designed to overlap the entire

graphene flake (see figure inset) in order to minimize the uncertainty in the de-embedding

process for high-frequency Sparameter measurements, as explained below.

In the device shown in Fig. 1(B), the distance between the source and drain electrodes

is 500 nm, and the top gate underlaps the source-drain gap with a gate length LG of 360 nm.

The total gate width (or channel width), including both channels, is ~ 40μm.

Fig. 1(A) shows the optical image of the complete device layout where the standard

ground-signal-ground probing pads are realized for the gate and the drain to allow for

transition from coax to on-chip coplanar waveguide (CPW) electrodes. Measurements of dc

electrical properties of graphene devices were performed in order to gain insight into their

high-frequency response. In addition, the dc electrical characteristics were monitored at each

fabrication step so that issues affecting the final device performance could be identified.

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Fig. Measured output characteristics of the graphene transistor for various top-gate voltages

The dc electrical characteristics of the completed graphene device after the deposition

of the top-gate electrode are shown in Fig. The inset shows the measured current as a

function of (top-gate) voltage VG at a drain bias of VD = 100 mV. Despite the small on/off

ratio, the graphene devices are essentially ambipolar field-effect transistors, as indicated by

the "V"-shape gate dependence in the measured ID-VG curve. In these graphene field-effect

transistors (GFET), the transport is dominated by electrons and holes for positive and

negative gate voltages, respectively, and the conductance minimum is denoted as the Dirac

point where electrons and holes make equal contributions to the transport.

Fig. shows the n-type output characteristics, ID-VD, of the grapheme transistor at

various gate voltages. It is found that the top-gated GFETs studied here exhibit a nearly linear

ID-VD dependence up to 1.6 V for the gate voltage ranges measured. This lack of current

saturation is due to the fact that graphene is a zero-gap semiconductor. It has been suggested

that velocity saturation at higher biases may lead to the current saturation phenomenon in

graphene transistors. However, a higher carrier mobility may be required to achieve this

saturation velocity within the drain bias of practical interest.

The de-embedded S parameters constitute a complete set of coefficients to describe

intrinsic input and output behaviors of the graphene device, and can be used to derive other

important electrical properties such as gain.

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Fig. The current gain h21

In Fig. the de-embedded current gain h21 decreases with increasing frequency

following the 1/f slope expected for a conventional FET. In a regular FET, this 1/f frequency

dependence of h21, equivalent to a decay slope of -20dB/decade, results from the gate

impedance given by Z = 1/jωCG, where ω = 2πf and CG is the gate capacitance, that

decreases with increasing frequency. Therefore, the 1/f dependence of current gain obtained

in Fig. is significant because it not only validates the high-frequency measurements and the

de-embedding procedures used to extract the intrinsic GFET characteristics, but it also

suggests regular FET-like behaviors for graphene transistors as a function of frequency. One

of the important figures of merit for characterizing high-frequency transistors is the cut-off

frequency fT, defined as the frequency where the current gain becomes unity (h21 = 1). In

practice, for a transistor possessing the ideal -20dB/decade slope for h21, the cut-off

frequency fT is determined by the product of h21 and frequency, i.e. f × h21(f), over the

measured frequency range. Thus, for the device shown in Fig. 4, the cut-off frequency fT can

be determined by either approach to be ~ 4 GHz. The high-frequency operation of the

graphene transistor is found to be highly dependent on the dc bias condition. Fig. 5 shows the

measured cut-off frequency fT of the GFET as a function of gate voltage. At all gate voltages,

the de-embedded current gain h21 exhibits the 1/f frequency dependence similar to that

shown in Fig. so that the cut-off frequency can be reliably determined. The n-branch of the

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graphene transistor is shown here because of the higher transconductance for electrons than

for holes in this device.

These results show that the high-frequency behavior of these graphene transistors can

be described as an FET with a static, constant gate capacitance within a significant portion of

the bias range. In principle, the maximum cut-off frequency of an FET can be improved by

reducing the gate length. To investigate the length dependence of fT in graphene devices,

graphene transistors with various gate lengths down to 150 nm were fabricated and

investigated for their high-frequency operations.

All of the graphene devices studied here were prepared in one batch and on the same

chip in order to minimize the device-to-device variations introduced in the fabrication

processes. As before, mobility degradation was observed in all devices after ALD oxide

deposition. The maximum fT was found to increase with reduced gate lengths, as expected,

and for the 150-nmgate GFET, a peak cut-off frequency as high as 26 GHz was obtained, as

shown in Fig. 6. To the authors’ knowledge, this is the highest value measured for graphene

transistors to date.

In summary, top-gated graphene transistors of various gate lengths were fabricated

and their high-frequency response was directly characterized by standard S-parameter

measurements. The short-circuit current gain showed the ideal 1/f frequency dependence,

confirming the measurement quality and the FET-like behavior for graphene devices. As the

gate voltage is varied, the measured fT was found to be proportional to the dc

transconductance gm, following the relation fT = gm/(2π CG). Furthermore, fT was found to

increase with decreasing channel length, with the scaling dependence fT ~ 1/LG 2 for the

GFETs studied here. A peak cut-off frequency fT as high as 26 GHz was measured for a

150-nm-gate graphene transistor, establishing the state of the art for graphene transistors.

These results also indicate that if the high mobility of graphene can be preserved during the

device fabrication process, a cut-off frequency approaching THz may be achieved for

graphene FET with a gate length of just 50nm and carrier mobility of 2000 cm2/V⋅s.

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Graphene Nanoribbon Field-Effect Transistors

Fig. GNRFET device

Sub-10nm wide graphene nanoribbon field-effect transistors (GNRFETs) are studied

systematically. All sub-10nm GNRs afforded semiconducting FETs without exception, with

Ion/Ioff ratio up to 106 and on-state current density as high as ~2000μA/μm. We estimated

carrier mobility ~200cm2/Vs and scattering mean free path ~10nm in sub-10nm GNRs.

Scattering mechanisms by edges, acoustic phonon and defects are discussed. The sub-10nm

GNRFETs are comparable to small diameter (d≤~1.2nm) carbon nanotube FETs with Pd

contacts in on-state current density and Ion/Ioff ratio, but have the advantage of producing all-

semiconducting devices.

Since our GNRFETs were Schottky barrier (SB) type FETs where the current was

modulated by carrier tunnelling probability through SB at contacts, high work function metal

Pd was used to minimize the SB height for holes in p-type transistors. In fact we used Ti/Au

as contact and found that Pd did give higher Ion in device with similar dimensions. 10nm SiO2

gate dielectrics was also important to achieve higher Ion because it significantly reduced SB

width at contacts compared to 300nm in previous work

For wide GNR devices, they all showed metallic behavior because of vanishingly

small bandgaps. Compared to sub-10nm GNRFETs with similar channel length, the current

density in wide GNR devices was usually higher (~3000μA/μm at Vds=1V for the device in.

We note that our wide GNRs showed relatively weak gate dependence in transfer

characteristics, likely due to interaction between layers. The Dirac point was usually not

observed around zero gate bias, indicating p-doping effects at the edges or by physisorbed

species during the chemical treatment steps.

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Fig. Transfer and output characteristics of the device

We next analyze how close the GNRFET operates to the ballistic performance limits

by comparing experiments with theoretical modelling. The theoretical model computes the

ballistic performance limits by assuming a single ballistic channel and ideal contacts

(sufficiently negative SBs).

Any subsequent edge scattering after OP/ZBP emission has a small direct effect on

the DC current because edge scattering is elastic and does not change the carrier energy. Such

a carrier rattles around in the channel and finally diffuses out of the drain. At high drain biases,

therefore, only elastic scattering near the beginning of the channel matters and the rest of the

channel essentially operates as a carrier absorber.

Our sub-10nm GNRFETs afford all-semiconducting nano-scale transistors that are

comparable in performance to small diameter carbon nanotube devices. GNRs are possible

candidates for future nano-electronics. Future work should focus on elucidating the atomic

structures of the edges of our GNRs and correlate with the performances of GNRFETs. The

integration of ultra thin high dielectrics and more aggressive channel length scaling is also

needed to achieve better electrostatics, higher Ion and ideal subthreshold slope.

Fabrication Process of GNRFETs

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We obtained the graphene suspension in PmPV/DCE solution. We soaked the 10nm

SiO2/p++ Si substrate with pre-patterned metal markers (2nm Ti/20nm Au) in the solution for

~20mins, rinsed with isopropanol and blew dry with argon. Then the chip was calcined in air

at 350ºC for ~10mins and annealed in vacuum at 600ºC for ~10mins to further clean the

surface. We used tapping mode AFM to find GNRs around the pre-patterned markers and

recorded the location. Next we used electron beam lithography to pattern the S/D of the

devices. 20nm Pd was then thermally evaporated as contact metal followed by a standard lift-

off process. Finally, we annealed the device in argon at 200ºC for ~15mins to improve the

contact.

Tunable Graphene Single Electron Transistor

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We report electronic transport experiments on a graphene single electron transistor.

The device consists of a graphene island connected to source and drain electrodes via two

narrow grapheme constrictions. It is electrostatically tunable by three lateral graphene gates

and an additional back gate. The tunneling coupling is a strongly nonmonotonic function of

gate voltage indicating the presence of localized states in the barriers. We investigate energy

scales for the tunneling gap, the resonances in the constrictions and for the Coulomb

blockade resonances. From Coulomb diamond measurements in different device

configurations (i.e. barrier configurations) we extract a charging energy of _ 3.4 meV and

estimate a characteristic energy scale for the constriction resonances of _ 10 meV.

Fig. Graphene single electron transistor(SET)

Fig. Schematic illustration of the tunable SET device with electrode assignment

Here we investigate a fully tunable single electron transistor (SET) that consists of a

width modulated grapheme structure exhibiting spatially separated transport gaps. SETs

consist of a conducting island connected by tunneling barriers to two conducting leads.

Electronic transport through the device can be blocked by Coulomb interaction for

temperatures and bias voltages lower than the characteristic energy required to add an

electron to the island. The sample is fabricated based on single-layer grapheme flakes

obtained from mechanical exfoliation of bulk graphite. These flakes are deposited on a highly

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doped silicon substrate with a 295 nm silicon oxide layer. Electron beam (e-beam)

lithography is used for patterning the isolated graphene flake by subsequent Ar/O2 reactive

ion etching. Finally, an additional e-beam and lift-off step is performed to pattern Ti/Au (2

nm/50 nm) electrodes.

TABLE I: Capacitances and lever arms of the different gate electrodes, including source and

drain contacts, with respect to the graphene island. Most values are independent from the

measurement regime, NN or NP. If there is a difference the NP value is given and the NN value

is put in brackets.

In conclusion, we have fabricated and characterized a fully tunable graphene single

electron transistor based on an etched width-modulated graphene nanostructure with lateral

graphene gates. Its functionality was demonstrated by observing electrostatic control over the

tunneling barriers. From Coulomb diamond measurements it was estimated that the charging

energy of the grapheme island is 3.4 meV, compatible with its lithographic dimensions.

These results give detailed insights into tunable graphene quantum dot devices and open the

way to study graphene quantum dots with smaller dimensions and at lower temperatures.

Transfer Characteristics in Graphene Field-Effect Transistors with Co Contacts

Graphene field-effect transistors with Co contacts as source and drain electrodes show

anomalous distorted transfer characteristics. The anomaly appears only in short-channel

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devices (shorter than approximately 3 μm) and originates from a contact-induced effect. Band

alteration of a graphene channel by the contacts is discussed as a possible mechanism for the

anomalous characteristics observed.

In order to construct such electronic devices, metallic materials should make a contact

with the grapheme layers. The effect of metal contacts can be detected using the structure of a

field-effect transistor (FET) and measuring the transfer characteristics (drain current, D I , vs.

gate voltage, G V , characteristics). For instance, the difference between the drain currents of

graphene FETs at exactly opposite charge densities (at the same carrier densities with

opposite charge polarities) has been explained by a metal-contact effect. Charge transfer from

metal to graphene leads to a p-p, n-n or p-n junction in graphene, depending on the polarity of

carriers in the bulk of the graphene sheet. An additional resistance arises as a result of the

density step created along the graphene channel, which causes asymmetry.

In this we analyse the effect of metal contacts on the transfer characteristics of

graphene FETs. In particular, the choice of metal and the gap between the metal contacts

(source and drain electrodes) have been examined by employing a FET structure. It was

found that graphene FETs with Co contacts and short channels display anomalous distorted

transfer characteristics, indicating that the anomaly originates from Co contacts.

Fig. Schematic diagram of a graphene FET.

Graphene layers were formed onto a highly-doped Si substrate with a 300 nm thick

thermal oxide layer using conventional mechanical exfoliation. The starting graphite crystal

used was Super Graphite from Kaneka Corporation. The thicknesses of the graphene layers

were determined to be approximately 1nm by atomic force microscopic observations in

tapping mode. These layers were determined to be one-atom thick from the optical contrast.

Metal electrodes (Co and Au) were fabricated onto the grapheme layers by electron beam

lithography and liftoff techniques. For the Au electrodes, 5nm thick Cr was deposited as an

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adhesive layer prior to Au deposition. The electrodes fabricated in this study had a total

thickness of 50nm. The FET characteristics were measured in low vacuum at room

temperature.

Fig. Transfer characteristics of a graphene FET with Cr/Au electrodes with channel length 1.5 μm.

Fig Transfer characteristics of a graphene FET with Co electrodes. The channel length was 2.0 μm

The transfer characteristics are shown in Figs. 1(b) and 1(c) for Cr/Au and Co

source/drain electrodes, respectively. Cr/Au is a conventionally used metallic material for

electronic devices, and Co is a popular material for spin-electronic devices as a source of

spinpolarized current. Although the graphene FET with Cr/Au contacts exhibits conventional

transfer characteristics, as widely reported previously, that with the Co contacts displays

anomalous distorted characteristics, especially in the negatively gated region.

The shorter channel results in lower channel resistance, and the resistance originating

from the contacts should have a more dominant effect on the two-terminal resistance. In fact,

the resistances at the D I minima are not proportional to the ratio of channel length to channel

width, and thus the contact-related effects contribute to the device resistance.

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Fig. Wide-ranging transfer characteristics of Co-contacted graphene FETs with a channel length of 3 μm.

In the wide-ranging transfer characteristics of the 3 μm channel device decreases in

the current compared with ordinary transfer characteristics can be seen at gate voltages of -70

and +30 V in addition to the minimum at a gate voltage of +2 V. The minimum at +2 V is

considered to be the charge neutrality point (the so-called Dirac point); the other two

anomalous points are therefore a consequence of the metal contacts.

Another possible mechanism is the diffusion of Co atoms into/onto graphene

channels. In a single charge tunneling device of a single CdTe nanorod with Cr/Pd contacts, a

chemical transformation was found to occur by the diffusion of Pd atoms 20-30 nm into the

nanorod.20 However, the robust honeycomb lattice structure of graphene and the possibly

strong chemical interactions at Co/graphene interfaces should prevent Co atoms from

diffusing a long distance into and onto graphene channels. In summary, the effect of metallic

electrode materials contacting graphene channel layers was studied using FET structures.

Cr/Au and Co contacts were investigated, and it was found that graphene FETs with Co

contacts and short channels exhibit distorted transfer characteristics that have two peaks at

-0.20 and +0.13 ev. The present study ascertained the metal-induced alteration of the FET

characteristics of graphene. These results indicate particularly crucial issues for the

development of future graphene microelectronics that consist of short-channel devices.

Epitaxial Graphene Transistors on SiC Substrates

This describes the behavior of top gated transistors fabricated using carbon,

particularly epitaxial graphene on SiC, as the active material. In the past decade research has

identified carbon-based electronics as a possible alternative to silicon-based electronics. This

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enthusiasm was spurred by high carbon nanotube carrier mobilities. However, nanotube

production, placement, and control are all serious issues. Graphene, a thin sheet of graphitic

carbon, can overcome some of these problems and therefore is a promising new electronic

material.

Although graphene devices have been built before, in this work we provide the first

demonstration and systematic evaluation of arrays of a large number of transistors entirely

produced using standard microelectronics methods. Graphene devices presented feature high-

k dielectric, mobilities up to 5000 cm2/Vs and, Ion/Ioff ratios of up to 7, and are

methodically analyzed to provide insight into the substrate properties. Typical of graphene,

these micron-scale devices have negligible band gaps and therefore large leakage currents.

Materials and Substrate Preparation:-

Graphitic films on SiC substrates were prepared by solid-state decomposition of

single crystal 4HSiC (0001) in vacuum. The method involves an inductively heated vacuum

furnace in which 3.5 mm X 4.5 mm X 0.3 mm SiC chips, are heated to about 1400 °C. In this

process, Si sublimes to produce carbon-rich surfaces that subsequently graphitize. The

graphitization produces epitaxially ordered stacked layers of graphene, with a high structural

coherence length. Figure 1 shows this multi-layered epitaxial graphene (MEG) at the

different stages of preparation.

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Fig. Preparation stages of the G/SiC substrate chips (4.5x3.5mm).

Prior to integration G/SiC chips were characterized using optical and AFM

measurements at MIT LL. It is important to note that SiC is not symmetric, the Si – C bond in

the [0001] direction has an asymmetry just due to the fact that one end is Si and the other is

C. Consider cleaving the SiC lattice by breaking that particular bond along the (0001) plane.

This cleave results in two interfaces, the silicon terminated surface is called the Si-face, and

the carbon terminated surface is called the C-face, figure

Fig. Crystal structure of SiC showing the two faces of the crystal cut along the (0001) plane.

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A typical SiC wafer will have a Si-face in the front with a [0001] normal, and a C-

face in the back with a [000-1] normal. During silicon sublimation graphene layers are

generated on both faces of the SiC wafer, however the film generated on the C-face has

different properties from the film generated on the Si-face.

Device integration:-

After characterization, G/SiC chips were mounted on 150-mm silicon carrier wafers

using epoxy bonding. This was done so that the silicon fabrication tools are able to process

the small chips. First, alignment marks were defined with standard g-line lithography and

etched into the G/SiC with a Cl2/He plasma etch. These marks are required because the

active MEG layer is too difficult to see optically for consistent alignment of subsequent

layers. Following the alignment mark etch, the resist was stripped in 80°C sulfuric acid; this

strip did not affect the appearance or resistivity of the MEG layer. Next, the active MEG

layer was patterned using a low energy O2 plasma etch. The source/drain layers were

deposited directly on the MEG film layer and consisted of 2 nm Ti and 20 nm of Pt, defined

using a lift off process. A 40 nm HfO2 layer was then deposited over the entire chip, using

thermal evaporation. The HfO2 film was verified to have a dielectric constant of 23 via a

capacitive measurement of a finished device. Finally, a 100 nm Al gate was deposited and

defined using lift-off. The AFM of a finished device is shown in Figure 5.

The mask pattern used in this experiment contained approximately 100 devices, with

different gate lengths, graphene widths, and alignment conditions. The nominal device was a

one with a source to drain spacing of 10 μm, a graphene width of 5 μm, and a 15 μm gate

overlapping the source and drain by 2.5 μm on each face. Hundreds of transistors where

fabricated, with functional yield as high as 95% for some samples.

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Figure 5: AFM scan of a finished nominal device

Although promising, graphene based electronics faces many obstacles before it can

become a competitive technology. Minimum conduction has to be decreased, device to

device variability has to be controlled, and a stable gate dielectric must be found. However

the chip level integration of hundreds of graphene devices on insulating SiC substrates is a

step towards making graphene technology possible. The main driver for a graphene

technology is clearly mobility. Even in this preliminary experiment mobilities up to 5000

cm2/Vs have been achieved. This is already 10 times better than silicon technology which

has had decades of optimization. It doesn’t seem unreasonable to expect that after thorough

investigation and process optimization, graphene devices will have mobilities over 10,000

cm2/Vs. The greatest obstacle to a graphene technology is the lack of a band-gap, and thus an

inability to turn off conduction below a certain level. It is likely that some method of

obtaining an on/off ratio for current in the hundreds will be demonstrated in the near future.

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CONCLUSION

Although promising, graphene based electronics faces many obstacles before it can

become a competitive technology. Minimum conduction has to be decreased, device to

device variability has to be controlled, and a stable gate dielectric must be found. However

the chip level integration of hundreds of graphene devices on insulating SiC substrates is a

step towards making graphene technology possible. The main driver for a graphene

technology is clearly mobility.

A necessary and important aspect of engineering course is technical seminar. It gives

an engineer to face and gain the knowledge of various technical fields. Knowledge of that

field helps the student to connect from the technical world.

This seminar report represents the whole knowledge of Graphene Transistor. In

everywhere in industries programmable logic controller is used. We can say that now a days

the grapheme transistor become the back bone of the modern electronic field.

So, I thought to take my technical seminar onGraphene Transistor. I learn a lot of knowledge.

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BIBLIOGRAPHY

1. en.wikipedia.org/wiki/Graphene

2. www.ias.ac.in/currsci/may252007/1338.pdf

3. http://images.google.co.in/images

4. http://www.whereisdoc.com/

5. whatis.techtarget.com/definition/graphene-transistor.html

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