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n Vi xl v Cu trc my tnh- LAB 3: MIPS 32-bit single- cycle

Nhm 14: Q.Bnh Q.Ton V.Chc Page 1

N MN HC

VI XL V CU TRC MY TNH

Lab 3: Design M IPS 32-bit single- cycle CPU

SVTH: To Quang Bnh. 09DT1

Trn Quc Ton. 09DT2

Nguyn Vn Chc. 09DT1Nhm: 14

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1. Yu cu lab 3:o Thit k chip MIPS 32-bit single- cycle thc hin c cc lnh: ADD, SUB,

SLT, XORI, LW, SW, J, JR, BNE.

o Da trn cc module c sn: regfile, ALU, instrmem, datamem.2. Tp lnh:o Cc lnh chia lm 3 nhm: R- format, I- format, J- format

2.1. R- format.- ngha lnh:

+ ADD rd, rs, rt:

Reg[rd] = Reg[rs] + Reg[rt].

+ SLT rd, rs, rt:

If (Reg[rs] < Reg[rt])

Reg[rd] = 1

else

Reg[rd] = 0.

+ SUB rd, rs, rt:

Reg[rd] = Reg[rs]Reg[rt].

+ JR rs:

PC = Reg[rs].

- Khun dng:

opcode rs rt rd Shamt function

6 bit 5 bit 5 bit 5 bit 5 bit 6 bit

2.2. I- format.- ngha lnh:

+ BNE rs, rt, imm16:

if (Reg[rs] != Reg[rt])

PC = PC + 4 + Sign_ext(Imm16)

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+ LW rt, imm16(rs):

Reg[rt] = Mem[Reg[rs] + Sign_ext(Imm16)].

+ SW rt, imm16(rs):

Mem[Reg[rs] + Sign_ext(Imm16)] = Reg[rt].+ XORI rt, rs, imm16:

Reg[rt] = Reg[rs] XOR Zero_ext(Imm16).

- Khun dng:

opcode rs rt address/immediate

6 bit 5 bit 5 bit 16 bit

2.3. J-format:

- ngha lnh:

+ J target:

PC = { PC[31:28], target, 00 }.

- Khun dng:

opcode target address

6 bit 26 bit

3. Thit k:3.1. S khi tng qut:

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3.2. Thit kcc module.3.2.1. Khi tm v ly lnh.

o B nh lnh: Instruction Memory: Dng lu tr lnh di dng m my.Trong bi lab ny, bnhlnh c cho trong file: instrmem.v

o Thanh ghi PC: L thanh ghi 32 bit, cha a chca lnh sp c thc thi. cxy dng trn cc D_FF.

o Bcng: Tng gi trthanh ghi PC ln 4.o M hnh khi tm v ly lnh ban u.

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o3.2.2. Khi thanh ghi 32 bits

o Khi thanh ghi 32 bits ny c hon thnh lab 1.o Trong ReadRegister 1 v ReadRegister 2 l cc thanh ghi dng la chn 2

trong 32 thanh ghi, gi trca chng sc c Read Data1 v Read Data 2.o Writer Data l ng vo la chn ch cho thao tc ghi.o RegWrite l tn hiu iu khin ghi. Nu RegWrite = 1 th d liu ng vo s

c ghi vo thanh ghi WriteData.

o S khi ca 1 file thanh ghi nh sau:

oo S chi tit ca 1 file thanh ghi nh sau:

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o a chtruy cp bnhl 32 bits. Tc l vi 32bits a ch, ta struy cp c bytes hay words. Trong bi lab ny, ta m phng vi 1024 bytes, tc

l

o S khi bnhdliu:

o

3.2.5. Ghp ni bsung datapath Ty vo tng lnh trong tp lnh m MIPS cn thc hin ghp ni bsung

databapath cho ph hp. i vi cc lnh khun dng R: Gm ADD,SUB, SLT v JR

+ Cc lnh ADD, SUB, SLT yu cu: Ly dliu tfile thanh ghi, a sangkhi ALU tnh ton, luli vo file thanh ghi. Ring lnh JR th chcn ly dliu tfile thanh ghi thay i thanh ghi PC.

Thm lnh XORI:XORI rt, rs, imm16: Reg[rt]=Reg[rs] XORZero_ext(Imm16).

Cn bsung:- Khi Zero_extend- BMultiplexor chn u vo cho ALU (ReadData2 hoc Zero_ext(Imm16)

)

- BMultiplexor chn a chcho WriteRegister (rd hoc rt )

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3.2.6.2. Khi ALUControlBng gi trtn hiu iu khin khi ALUControl

ALUOp Funtion ALUControl ALUOperation Instruction

11 XXXXXX 01 XOR XORI

00 XXXXXX 00 ADD LW-SW01 XXXXXX 10 SUB BNE

10 100000 00 ADD R- format ADD

10 100010 10 SUB R- format SUB

10 101010 11 SLT R- format- SLT

Cc tn hiu iu khin i vi cc lnh JR v BNE:o JRControl:

+ Nu ALUOp = 10 (R-format) v Function= 001000 thJRControl= 1, cn ngc li th JRControl = 0.

o bneControl:+ bneControl = 1 nu Branch = 1, ZeroFlag = 0.+ Ngc li bneControl = 0.

4. Module chnh.`timescale 1 ps / 100 fs

// MIPS 32BIT - SINGLE - CYLCE - CPU

module MIPS(clk, reset);

input clk, reset;

/************************************

************* KHAI BAO *************

************************************/

// KHAI BAO DIA CHI

wire [31:0] PCin,PC; // PCin: dia chi ngo vao cua thanh ghi PC

wire [31:0] PC_4, // PC_4 : Dia chi lenh tiep theo

PC_Bne, // PC_Bne : Dia chi neu thuc hien lenh Branch

PC_Jump, // PC_Jump: Dia chi neu thuc hien lenh Jump

PC_JR, // PC_JR : Dia chi neu thuc hien lenh Jump Register

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Bne_Address, // Bne_Address: Dia chi Branch

Jump_Address, // Jump_Address: Dia chi Jump

JR_Address; // JR_Address: Dia chi Jump Register ( =

ReadData1)

// KHAI BAO INSTRUCTION MEMORY

wire [31:0] Instruction; // Lenh dang xu ly

wire [5:0] Opcode,Funct;

wire [4:0] Rs,Rt,Rd;

wire [15:0] Imm16; // gia tri 16bit immediate

assign Opcode = Instruction[31:26];

assign Rs = Instruction[25:21];assign Rt = Instruction[20:16];

assign Rd = Instruction[15:11];

assign Funct = Instruction[5:0];

assign Imm16 = Instruction[15:0];

// KHAI BAO CONTROL UNIT

wire RegDst,

Jump,

Branch,MemRead,

MemtoReg,

MemWrite,

ALUSrc,

RegWrite,

SignZero;

wire [1:0]ALUOp;

// KHAI BAO ALU

wire [31:0] ALUin1, // 2 ngo vao cua bo ALU

ALUin2;

wire [31:0] ALUResult; // Ket qua cua bo ALU

wire Zero,

Negative,

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Overflow,

Carry; // Cac co` cua bo ALU

wire JR_Control; // Tin hieu dieu khien lenh Jump Register

wire Bne_Control; // Tin hieu dieu khien lenh BNEwire [1:0] ALU_Control; // Tin hieu ra cua ALU_Control_Unit

wire [31:0] Extend; // 32bit mo rong dau cua 16bit immediate

// KHAI BAO REGISTER FILE

wire [31:0] ReadData1,ReadData2; // Gia tri cac thanh ghi

wire [31:0] Reg_WriteData; // Gia tri ghi vao thanh ghi dich

wire [4:0] WriteRegister; // Thanh ghi dich

// KHAI BAO DATA MEMORY

wire [31:0] Mem_ReadData, // Du lieu xuat ra tu bo nho

Mem_Address, // Dia chi DataMemory

Mem_WriteData; // Du lieu ghi vao bo nho ( = ReadData2)

// KHAI BAO SHIFTER

wire [31:0] Bne_shift_in, // Ngo vao bo dich trai (BNE)Bne_shift_out, // Ngo ra bo dich trai (BNE)

Jump_shift_in, // Ngo vao bo dich trai (JUMP)

Jump_shift_out; // Ngo ra bo dich trai (JUMP)

/************************************

********* CAU TRUC MIPS ************

************************************/

/* KHOI THANH GHI PC */

PC_Register ProgramCounter( PC,

PCin,

reset,

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clk);

// Dia chi lenh tiep theo duoc thuc hien

Add_32bit Adder_PC( PC, // PC_4 = PC + 4

{29'b0,3'b100},,,

PC_4);

/* INSTRUCTION MEMORY - BO NHO LENH */

InstructionMem InstructionMemory(Instruction, PC);

/* MAIN CONTROL UNIT - KHOI DIEU KHIEN CHINH */

Control_Unit Control( RegDst,

ALUSrc,MemtoReg,

RegWrite,

MemRead,

MemWrite,

Branch,

ALUOp,

Jump,

SignZero,

Opcode );

/* REGISTER FILE - BO THANH GHI */

Mux_2x5to5 Mux_RegDst(WriteRegister,Rt,Rd,RegDst); // Chon

WriteRegister ( giua lenh R-type & I-type)

RegisterFile RegFile( ReadData1,

ReadData2,

Reg_WriteData,

Rs,

Rt,

WriteRegister,

RegWrite,

reset,

clk );

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/* SIGN-ZERO EXTEND */

Extender Sign_Extend(Extend, Imm16, SignZero);

/* ALU - KHOI TINH TOAN CHINH */assign ALUin1 = ReadData1;

Mux_2x32to32 Mux_Input_ALU( ALUin2,

ReadData2,

Extend,

ALUSrc);

ALU ALU_Unit(ALUResult,

ALUin1,

ALUin2,

Carry,Zero,

Overflow,

Negative,

ALU_Control);

ALU_Control_Unit ALUControl( ALU_Control,

ALUOp,

Funct);

/* DATA MEMORY - BO NHO DU LIEU */

assign Mem_WriteData = ReadData2;

assign Mem_Address = ALUResult;

DataMem DataMemory( Mem_ReadData,

ALUResult,

Mem_WriteData,

MemWrite,

MemRead,

clk);

Mux_2x32to32 Mux_WriteData( Reg_WriteData,

ALUResult,

Mem_ReadData,

MemtoReg);

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/* BNE CONTROL */

assign Bne_shift_in = Extend;

Shiftleft2 Shift_bne( Bne_shift_out, Bne_shift_in);Add_32bit Adder_bne( PC_4,

Bne_shift_out,,,

Bne_Address);

not #(50) notBNE(NotZero,Zero);

and #(50) andBNE(Bne_Control,Branch,NotZero);

Mux_2x32to32 Mux_BNE( PC_Bne,

PC_4,Bne_Address,

Bne_Control);

/* JUMP CONTROL */

assign Jump_shift_in = {6'b0,Instruction[25:0]};

assign Jump_Address = {PC_4[31:28],Jump_shift_out[27:0]};

Shiftleft2 Shift_jump(Jump_shift_out,Jump_shift_in);Mux_2x32to32 Mux_Jump(PC_Jump,

PC_Bne,

Jump_Address,

Jump);

/* JUMP REGISTER CONTROL */

assign JR_Address = ReadData1;

assign PCin = PC_JR;

JR_Control_Unit JRControlUnit1( ALUOp, Funct,JR_Control);

Mux_2x32to32 MuxJR( PC_JR,

PC_Jump,

JR_Address,

JR_Control);

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endmodule

Testbench:`timescale 1 ps / 100 fs

module Stimul();

parameter ClockPeriod = 10000;

reg clk,reset;

MIPS M(clk, reset);initial clk = 0;

always #(ClockPeriod/2) clk = ~clk;

initial

begin

reset = 1;

#ClockPeriod;

reset = 0;

#150000;reset =1;

#ClockPeriod;

reset = 0;

end

endmodule

end

endmodule

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