1303855214 Lab 01

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Laboratory #1

Tutorial on Xilinx ISE 9.2i

Objectives To become familiar with using Xilinx ISE 9.2i to draw schematic representations of PLD circuits

To become familiar with using Xilinx ISE 9.2i to conduct graphical waveform simulations of PLDcircuits

To become familiar with using Xilinx ISE 9.2i to write HDL representations of PLD circuits

To become familiar with using Xilinx ISE 9.2i to write HDL testbench simulations of PLD

circuits

To become familiar with downloading PLD circuits to the Basys development board

Introduction

There is more than one way to do it (TIMTOWTDI, usually pronounced "Tim Toady") is a

Perl motto. The language was designed with this idea in mind, so that it "doesn't try to tell theprogrammer how to program". This makes it easy to write extremely messy programs, but, as

proponents of this motto argue, it also makes it easy to write beautiful and concise ones.

The Zen of Python has a principle which is the exact opposite of TIMTOWTDI: "There should

be oneand preferably only oneobvious way to do it."1

In designing programmable logic, and in the tools used to do so, there is definitely more than one way to

do it.

Part I Drawing Schematics

The Xilinx Integrated Software Environment (ISE) allows users to design circuits for Xilinx FPGAs andCPLDs. It involves the use of Project Navigator, a user interface that helps users manage the entire

design process including design entry, simulation, synthesis, implementation and finally downloading the

design onto an FPGA or CPLD.

1.

Start ISE from the Start menu by selecting Start -> Programs -> Xilinx ISE 9.2i -> Project

Navigator.The ISE Project Navigator opens as shown in Figure 1. The Project Navigator lets you

manage the sources and processes in your ISE project.

1Description reprinted from Wikipedia

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Copyright 2008 GVSU School of Engineering

Figure 1: Launching ISE Project Navigator

2.

The next step is to create a new ISE project. To create a new project for this tutorial:

Select File ->New Project. The New Project Wizard appears as shown in Figure 2.

First, enter a location (directory path) for the new project. Choose a location on your USB drivesince files stored on laboratory computers do not persist once the computer shuts down.

Type counter in the Project Name field. When you type counter in the Project Name field, a

counter subdirectory is created automatically in the directory path you selected.

Select Schematic in the Top-Level Source Type list, indicating that the top-level file in yourproject will be a schematic rather than HDL, EDIF or NGC/NGO. Click Next to go to the Device

Propertieswindow

Figure 2: Creating a new project

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3. In the Device Properties window, you will be selecting your Target device, Simulator tool, Synthesistool and Hardware language in which you will be writing your design code. Figure 3 shows the

selections you need to make.

Figure 3: Target Device and Tool Selection

4.

Click Nextthree times and you will reach the Project Summarywindow. This window gives you an

overview of your project created so far. Click on Finishand your project is created as shown in Figure

4. Verify that the project name is counter.ise (shown as the last component in the title bar of theProject Navigator). You can also verify by going to the location where you created the project and

double-clicking on the folder namedcounter

.

Figure 4: Successful creation of project

5.

Now you will create a top level schematic for your design. In the Sources window, right click on

xc3s100e-5tq144 and select New Source. A New Source Wizard window appears as shown in

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Figure 5. Select Schematic and enter counter under file name. Make sure the Add to projectcheckbox is checked.

Figure 5: Creation of a schematic source file

6.

Click Next two times followed by Finish to create the counter.sch file under the project folder.

Figure 6 shows the final layout of the project after the source file is created. If you dont see the

schematic, you may see a Design Summary. Click on the counter.sch tab at the bottom of the main

design window to see the schematic.

Figure 6: Project Navigator showing top-level schematic

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7. The Sources window at the top-left should have the Symbols tab selected (there are 4 tabs at thebottom of the window). From this tab, you can select schematic symbols to add to the schematic.

From the Categories listbox, select Counter. Then, from the Symbols listbox, select cb2ce. Move

your cursor to the main schematic window on the right and you will see a schematic symbol attachedto the cursor. Left-click to place the symbol on the schematic. Press ESCAPE to detach the symbol

from the cursor, and then press the F8 key several times to zoom in on the symbol you placed. The

result should be as shown in Figure 7.

Figure 7: CB2CE symbol added to schematic

8. To enable the counter to count, we have to tie the CLR input low, since this is an active-high

asynchronous clear input. From the Categories listbox on the left, select General, and from the

Symbols listbox select gnd. Place a ground symbol on the schematic below the connection point ofthe CLR pin.

9.

The CE clock-enable pin is active-high. To allow the counter to count, we have to tie this pin high.

From the Categories listbox, select the choice right at the top, and type vcc in the

Symbol Name Filter textbox (a quicker way to add symbols when you already know the name). Click

on the vcc symbol name in the Symbols listbox and use the cursor to place a VCC symbol above theCE pin on the schematic.

10.Press Ctrl-W to start drawing wires, then click on the connection point of the CE pin (the smallsquare). Draw a wire ending at the connection point of the VCC symbol. Similarly, connect the CLR

pin and GND symbol together. The result should be as shown in Figure 8.

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Figure 8: VCC and GND symbols connected to the CB2CE symbol

11.Press Ctrl-G or click on the Add I/O Marker tool in the toolbar to start placing I/O markers (whichare connections to the outside world). Place an I/O marker directly over the connection point for the C

(clock) input. An I/O port symbol with an arbitrary name such as XLXN_3 will appear. Press

ESCAPE and use the mouse to click and drag this I/O port symbol away from the symbol. A wire willautomatically be drawn to keep the I/O port and clock pin connected.

12.Right-click on the I/O port symbol, select Rename Port and type in the name CLK. The result shouldbe as shown in Figure 9.

Figure 9: CB2CE symbol connected to an I/O port

13.Finally, add two I/O ports for the Q0 and Q1 outputs and connect them. Name the I/O ports Q0 andQ1. This is a good time to save your work (press Ctrl-S).

14.The counterdesign must now be synthesized, i.e., converted to a representation that maps to actualhardware resources on the Xilinx FPGA that you selected. To do so, go to the Processes window

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below the Sources window and click on the Processes tab. Then, double-click on the Synthesize-XSTitem. Its OK if a yellow warning icon appears next to this item once the process is complete.

Part II Constructing Waveform Simulations

1. In the Sources window at the top-left, click the Sources tab at the bottom of the window. Right-click

on the counter.sch filename and and select New Source. In the New Source Wizard dialog, select

Test Bench Waveformfrom the window on the left and enter countersimin the File nametext box.

Make sure the Add to project checkbox is checked (see Figure 10). Click Nextand make sure that

counteris the top-level module name selected for this test bench waveform file. Click Nextfollowed

by Finish.

Figure 10: A test bench waveform file is added to the project

2.

The Initial Timing and Clock Wizarddialog opens, which allows you to create a clock stimulus forthe 2-bit counter design. Set the values in the dialog as shown in Figure 11 and then click Finish.

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Figure 11: Clock stimulus settings for behavioral simulation

3.

You should see a timing diagram display that looks like a logic analyzer with the filename

countersim.tbw, as shown in Figure 12. Press Ctrl-S to save the file.

Figure 12: Test bench waveform for 2-bit counter

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4.

To run the simulation, go to the Sources window at the top-left and use the drop-down listbox to

switch from Synthesis/Implementation to Behavioral Simulation. Click on the countersim.tbw

module name. In the Processes window below it, click on the Processes tab, then open the Xilinx ISESimulator tree control. Finally, double-click on the Simulate Behavioral Modelitem.

5.

After a surprisingly long time for such a simple circuit, the simulation results should appear in aSimulation window, as shown in Figure 13. Verify that your circuit functions as a 2-bit counter with

Q1 as the most significant bit.

Figure 13: Results of 2-bit counter simulation

Part III Circuit Design with VHDL

1. Close the 2-bit counter project by using the File->Close Projectmenu item. Now create a new project

by selecting File->New Project. In the New Project Wizarddialog, set the name for this project to

be counter_vhdl, and set the Top-Level Source Type to be HDL. The wizard should appear as inFigure 14.

Figure 14: Creating a new project using VHDL as the top-level source

2. Click Next, and verify that the Device Propertiesare the same as for the previous project (Spartan3EXC3S100E TQ144-5 device, VHDL as the preferred language, XST synthesis tool, ISE simulator).

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3. In the Create New Sourcedialog, click on the New Sourcebutton. The New Source Wizarddialogappears. Set the file name to be counter_vhdl and select the VHDL Module type. Make sure the

Add to project checkbox is checked. Click Next.

4.

The Define Moduledialog box appears. In this dialog you will set the names of the input and output

pins of the circuit. Set the fields of this dialog to appear as in Figure 15 and click Nextand then

Finish.

Figure 15: Defining the inputs and outputs of a VHDL module

5. Back in the New Project Wizarddialog, click Nexttwice then Finish. After the process completes,

you should see the counter_vhdl.vhd file, as shown in Figure 16.

Figure 16: A new project showing the VHDL top-level source

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6. Some of the VHDL code has already been written for you. Finish implementing the circuit bymodifying the source code as shown in Figure 17. Press Ctrl-S to save your work.

Figure 17: VHDL code implementation of an 8-bit counter

7.

To verify that you typed in the code correctly, perform a syntax check by opening the Synthesize-

XST tree control in the Processes window and double-clicking on the Check Syntax item. If your

code is correct, a green checkbox will eventually appear next to this item.

8. Once the code is correct, synthesize the design by double-clicking on the Synthesize-XSTtree control

in the Processeswindow.

9.

After synthesizing the design, lets perform a behavioral simulation of the design. Right-click oncounter_vhdl.vhd in the Sourceswindow and select New Source. In New Source Wizard,select

Test Bench Waveform and set the File name to be countersim. Click Next and then make sure

counter_vhdl is the top level module name with which you are associating this test bench file. Click

Next followed by Finish to open Initial Timing and Clock Wizard. Make changes as shown inFigure 18 and then click Finish.

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Figure 18: Setting a clock stimulus for the counter_vhdlcircuit.

10.Once you click on Finish, the Test bench waveform window opens as shown in Figure 19.

Figure 19: Test bench waveform stimulus for counter_vhdlcircuit

11.To run the simulation, switch the Sourceswindow drop-down listbox from

Synthesis/Implementation to Behavioral Simulation. Under the Processeswindow, click on the

Processestab and expand Xilinx ISE Simulatorand double-click Simulate Behavioral Model.

12.

The simulator runs and opens another window which has the results of the simulation. You may need

to zoom in on the simulation by clicking on icon on the toolbar at the top of the window. Figure20 shows the simulation output.

Figure 20: Results of behavioral simulation for the counter_vhdldesign

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13.Scroll horizontally through the simulation results to verify that the circuit functions as an 8-bitcounter.

Part IV VHDL Test Benches

Although we can construct waveform stimulus for our designs using the graphical editor, doing so is

cumbersome, time consuming, and error-prone. Furthermore, the graphical simulation results must beverified by eye, which is also cumbersome, time-consuming, and error-prone. We can instead use

VHDL to both specify the input stimulus (just a clock so far) and check the output results.

1.

In the Sourceswindow, make sure the drop-down box setting is still Behavioral Simulation. In the

Processes window, select the Processes tab and expand the Xilinx ISE Simulator tree control.

Expand the Simulate Behavioral Model tree control and double-click on the Generate Self-

Checking Test Benchitem, as shown in Figure 21.

Figure 21: Generating a post-synthesis simulation model

2.

Note that a new entry has been added to the xc3s100e-5tq144 module in the Sources window.

Right-click on the new countersim_selfcheck_beh item in the Sourceswindow and select Open.

The countersim_selfcheck_beh.vhd file is a VHDL test bench that both provides clock stimulus toyour counter and also checks the outputs. Scroll through this file for a big-picture view of what it is

doing.

3. Simulate this test bench by opening the Xilinx ISE Simulatortree control in the Processeswindow

and double-clicking the Simulate Behavioral Modelitem.

4.

To verify that this test bench is capable of detecting errors, lets change an expected result. In the

countersim_selfcheck_beh.vhd file at about line 100 (simulation time of 75ns), change the line that

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reads CHECK_ledout(00000100, 75) to CHECK_ledout(10000100, 75). Double-click onSimulate Behavioral Model again and verify that the Transcript window indicates an error at 75ns.

Part V Downloading to the Hardware

1. After successfully verifying the behavior of the design, now we need to download the design onto the

actual hardware. But before that we need to slow down the clock, so that each count is visible to theuser through LEDs on the board. Close the simulation window and the

countersim_selfcheck_beh.vhd window. Go back to edit the original counter_vhdl.vhd sourcefile. Figure 22 below shows the change you need to make to your code to include a clock divider

process.

Figure 22: Modification to counter_vhdldesign to implement a clock divider

2. Synthesize your design again by double-clicking on the Synthesize-XST item in the Processes

window. On successful synthesis, you should see a green check next to Synthesize-XST, although ayellow caution symbol might also appear.

3. After converting your design into a hardware representation, the next step is to assign actual devicepins to your design input/output ports through a constraint file. Right click on counter_vhdl.vhd

under the Sourceswindow and select New Source. Select Implementation Constraints File in the

New Source Wizardwindow and enter the file name as counterpins.

4.

Click Next followed by Finish and you will see a counterpins.ucf file added under the

counter_vhdl.vhd file in the Sourceswindow. Select the counterpins.ucf file then open up the

User Constraints tree control in the Processes window. Finally, double-click on Assign Package

Pinsunder Processeswindow as shown in Figure 23.

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Figure 24: Assigning I/O pins

6. Save the file and close the Xilinx PACE application window. After assigning the pins, you now need

to convert and map your design to the logic blocks inside the FPGA. In the Sourceswindow, selectthe counter_vhdl.vhd file and under the Processeswindow, double-click on Implement Designas

shown in Figure 25. On successful implementation, you should see a yellow exclamation mark next toImplement Design.

Figure 25: Implementing the design

7. Now under the Processeswindow, double-click on Generate Programming Fileto create a bitfile(the file that will be downloaded onto your hardware). You should see a green check beside it when

the process completes.

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8. Now you need to open a downloading tool that will download your design onto the FPGA. Go to

Start -> Programs -> Digilent -> Adept -> ExPortto open the tool as shown in Figure 26.

Figure 26: The Digilent ExPort downloading tool

9.

Connect your BASYSboard to the computer using the USBcable provided with the board. Make sure

SW8 (the switch on the lower left corner on the board) is positioned to VUSB. Now click on the

Initialize Chainbutton in the Digilent ExPortwindow. Two devices are detected, FPGA and ROMas shown in Figure 27.

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Figure 27: Detecting the devices on the Basys board

10.

Click on the FPGA graphic (not the checkbox next to it). It should turn green indicating its selected.

Then click on Browse and go to your design folder and select the counter_vhdl.bit file and click

Open. A warning window appears. Click Yesand you will see the counter_vhdl.bit file associated

with the FPGA as ahown in Figure 28.

Figure 28: Associating a .BIT file with the FPGA

11.

Ensure that jumper JP3 on the Basys board (near the VGA connector) has been set to the JTAG

position (connecting the rightmost two pins).

12.

Click on Program Chainand your program is downloaded on FPGA. You will see the 8 LEDs

counting in binary.

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13.Once you verify that the program works, try modifying the counter_vhdl.vhd file to achieve a fastercount rate. You may have to think and experiment a bit!

14.Once you are done, slide the switch SW8to VEXTand disconnect the USB cable from the computer.Close the Digilent ExPortand Xilinx ISEapplications.

1303855214 Lab 01

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