13 Oct 2008 CEME

1

Utilizing a Digital PWM Controller to Monitor the Health of a Power Supply

Mark HagenSystems Engineer

Digital Power Group

Texas Instruments

13 Oct 2008 CEME

2

A Digitally Controlled Power Supply

Reasons to go digital Programmable start/stop sequencing.

(Programmable start/stop delay and voltage ramp rates.)

Monitoring of system power and health metrics of the circuit. Ease of adjusting the loop compensation.

PC design tool does the math Can be tailored to the system late in the process since it is defined by serial bus

commands instead of by RC components.

Vin

+Vout

-

L

C1

RLoadGate drivers

iL

C2

R1

R2CpEAmp

Vref

DAC

digital Compensator

error ADC-

+

ramp counter

vsense+

verr

Vref

e[n]d[n]u[n]

RCS CCS

+-

current ADC

supervising CPU

serial I/O

Power Stage

divider network

Digital PWM Controller

to host

isense

13 Oct 2008 CEME

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Start/Stop Sequence

PMBus Standard supports sequencing commands TON_DELAY TON_RISE TRACKING_MODE

Digital controller operation Delay timed digitally. Track desired ramp under

closed loop control by slewing Vref setpoint DAC

May want separate loop compensation for start/stop ramps

Operating modes: Start/stop ramp Regulate Light load

rail#2 tracks rail#3

ramp rate defined by TON_RISE &

VOUT_COMMAND

Vout follows digitally

defined ramp

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Digitally Monitored Parameters

VIN (scaled input voltage)

IIN (requires dedicated current sense circuit) Shunt resistor: 4-terminal, low TCR type. Current sense amplifier:

INA13x, INA19x, INA21x, etc. "READ_IN" PMBus command

VOUT

PMBus provides for a separate measure of Vout from the control loop voltage sense.

IOUT

Either shunt sense circuit like Iin or Inductor DCR sense. Amplifier typically internal to controller or driver IC.

Temperature Ambient temperature measured at controller. Component temperature at each controlled power stage.

duty cycle "READ_DUTY_CYCLE" PMBus command Combined with Vin and Iout measure, forms a efficiency/circuit-health metric.

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Power Supply as a Feedback Controlled System

System consists of Plant (Power stage) Sensor network (voltage divider) Setpoint reference (Vref. Typically a DAC in digital PWM controllers.) Error amplifier (fast ADC) Compensator (digital filter) Pulse width modulator (fast digital counter) Delay elements (account for phase loss due to the time it takes to

calculate and apply the control effort)

Vin

+Vout

-

L

C1

RLoadGate drivers

iL

C2

R1

R2CpEAmp

Vref

DAC

digital Compensator

error ADC-

+

ramp counter

vsense+

verr

Vref

e[n]d[n]u[n]

RCS CCS

+-

current ADC

supervising CPU

serial I/O

Power Stage

divider network

Digital PWM Controller

to host

isense

13 Oct 2008 CEME

6

Modeling the Loop

Example with analog summing junction

G Delay 2 G PlantVout

G Div

K PW M K NLR K EADCd[n] e[n]

u[n]

G(s)

H(s)

G Delay 1 G CLA K AFE refVrVe

Vsense

K DAC+

Open-loop gain

Closed-loop gain

where KAFE = analog front end gain in V/V

KEADC = error ADC gain in LSB/volt

KNLR = Nonlinear boost gain

GCLA = Control-law accelerator (digital compensator) gain

GDelay1 = Total sampling and CLA computational delay

KPWM = PWM gain in duty/LSB

GDelay2 = On-time and any delay to multiple power stages driving Vout

GPlant = Transfer function from d to Vout of the power stage

GDiv = Divider network transfer function in V/V

sGsHv

v

error

Sense

sGsH

sGsH

ref

vSense

1

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Loop Stability Criteria

PM

GM

The frequency response is derived from the average model of the power stage

Open-loop gain = H(f)•G(f) Stability criteria

(same as analog control) Phase margin: Phase distance

from 180º at the frequency where gain = 0 dB want 45º to 65º

Gain margin: Gain at frequency where phase = 180º want > 6 dB

G Delay 2 G PlantVout

G Div

K PW M K NLR K EADCd[n] e[n]

u[n]

G(s)

H(s)

G Delay 1 G CLA K AFE refVrVe

Vsense

K DAC+

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Power-Stage Model

A (discrete) time model is needed to get accurate estimates of transient performance and stability

Define continuous-timestate equations

(states are iL and vC)

Convert to discrete-time difference equations

Design software such as Spice or the Fusion Digital Designer integrates difference equations for each interval to simulate the power stage

q q g

out q q g

x A x B V and

v C x D V

out

ˆˆ ˆx[n] x[n 1] d[n 1] and

ˆ ˆv [n] Cx[n]

Story7RevFig7PP5.cdr

G Delay 2 G PlantVout

G Div

K PW M K NLR K EADCd[n] e[n]

u[n]

G(s)

H(s)

G Delay 1 G CLA K AFE refVrVe

Vsense

K DAC+

c(t)

R esr

R L

C

RHvo

H=1vc+

–

iLL

vref

DPW M eADCG(z)

Vg

+

–

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Define the Plant (power stage)

Enter component parameter values Gain elements Vin and duty (from Vout) Series elements L, DCR, RDS(on) Parallel elements C, ESR, ESL

Lump like components together

Resulting transfer function for the plant

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Divider-Network Model

Divider scales Vout to error-ADCinput range.

With Cp, forms anti-alias low-passfor error-ADC. Set RC lowpass corner frequency at 35% to 45%

of error-ADC sample frequency. Continuous model

Digital power-design software creates a discrete model from continuous circuit description. Apply discrete transform to continuous model evaluated at each error-ADC sample time

2Div

1 2

RK

R R

1 z

Div DivDiv 1 z p

R C s 1G s K

K R C C s 1

G Delay 2 G PlantVout

K PW M K NLR K EADCd[n] e[n]

u[n]

G(s)

H(s)

G Delay 1 G CLA K AFE refVrVe

Vsense

K DAC+

G Div

CpR2

R1

G (f )Div

Cz

Vout

Vsense

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Define the divider network

Set the divider gain (attenuation) Set nominal Vout at ~75% of

error-ADC dynamic range headroom for margining, over-voltage detection.

Communicated to device by PMBus commands VOUT_SCALE_LOOP VOUT_SCALE_MONITOR

Define capacitors to set pole (or zero) Good idea to roll off high frequency

at 70% to 90% of Nyquist frequency. (35% tp 45% of switching frequency.)

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Model the Compensator

POL applications require 2nd-order compensation Two zeros and a pole at zero Hz This is a classical PID controller (Proportional, Integral, Derivative) Discrete form:

Additional poles improve effect of error-voltage quantization by smoothing the CLA output:

To model in discrete time, the design software evaluates the compensator difference equation:

2

01 11 21CLA

b z b z bduty(z)G z

e(z) z 1

2

01 11 21CLA 2

11 21

b z b z bduty(z)G z

e(z) z a z a

01 11 21 11 21d n b e n b e n 1 b e n 2 a d n 1 a d n 2

1 201 11 21

1 211 21

b b z b zd(z) e(z)

1 a z a z

2 zeros

pole at origin

2 zeros

2 poles

G Delay 2 G PlantVout

K PW M K NLR K EADCd[n] e[n]

u[n]

G(s)

H(s)

G Delay 1 K AFE refVrVe

Vsense

K DAC+

G Div

G CLA

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Types of Compensator Realizations

2nd-order table look-up (UCD9112)

Direct-form digital filter (UCD9240)

PID-form digital filter (conceptual)

20 1 2

21 2

d z b z b z b

e z z a z a

P I D

2P I D P I D P D

2

d z z z 1K K K

e z z 1 z

K K K z K 1 K 2K z K K

z 1 z

20 1 2d z K z K z K

e z z 1

e[n]

Numerator Denominator

e[n 2] –

d[n 1] –

d[n]

K0N K 1N K 2N

K 00 K 10 K 20

z –1 z –1

z –1

K 01 K 11 K 21

... ... ...... ... ...

e[n]

e[n – 1] e[n – 2]

z –1 z –1

b0 b1 b2

d[n – 1]

d[n – 2]

d[n]

z –1z –1

a1 a2

Num erator Denominator

e[n]

z –1

z –1

z –1

e[n – 1]

KP

K D

K l

d [n]D

d [n]P

d [n]l

d[n]Proportional

Integral

Derivative

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Choosing the Compensation

Choose continuous time parameters to shape the Bode-plot loop gain to achieve desired phase and gain margin

DC gain KDC

Zeros ωz1 ωz2

Poles: origin, ωp2

Then transform the continuous-time polynomial in s to a discrete-time polynomial in z. This is typically done by the design software

TI Fusion Digital Power Designer performs the transformation by:1. Apply the bilinear transformation by

substituting s into the above polynomial:

2. Then solve for discrete-time polynomial coefficients:

20 1 2

21 2

d z b z b z b

e z z a z a

2

2z1 z2 r r

DC DC 2

p2p2

s ss s11 1

d s QK or K

e s ss ss 1

sz 1

s 2Fz 1

G Delay 2 G PlantVout

K PW M K NLR K EADCd[n] e[n]

u[n]

G(s)

H(s)

G Delay 1 K AFE refVrVe

Vsense

K DAC+

G Div

G CLA

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Define the compensation

Center zeros on 2nd order plant pole Spreading the zeros either side of the plant pole

improves the output impedance of the system In above example I reduced the 2nd order zero

frequency a bit to buy some phase margin.

Define the compensator poles Integrator function defines 1st pole at the origin. Set 2nd pole above 0 dB cross-over to increase

gain margin.

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Effect of locating zeros

Perfectly canceling plant 2nd order pole does not result is lowest possible closed loop output impedance

Results in increased load transient settle time.

perfect cancellation

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Effect of locating zeros, cont.

Spreading zeros minimizes output impedance Lower output impedance improves load transient

settle time.

zeros spread

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Adding Nonlinear gain to the compensation

Strictly linear compensation flat gain Transient response

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Adding Nonlinear gain to the compensation

Reduce gain for quiescent cond. where verror near 0. gain high for transient, gain low at around zero. Improves steady state voltage, peak error reduced.

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Nonlinear Boost

Scope traces with and without nonlinear boost

Param eter

Peak-to-Peak O utput

Excursion

U niform gain of 1X 130.5 m V 5.2 m V

G ain boosted 3X for |v | > 5err

108.1 m V 5.0 m V

G ain boosted 4X for |v | > 5err

88.4 m V 5.0 m V

R M S E rrorD uring

Q uiescentO peration

0 2 0 0 6 0 0 8 0 0 1 0 0 0

T i m e ( µ s )

4 0 0

V (

V)

ou

t

1.3

1.25

1.2

1.15

1.1

1.05

1

0.95

0.9

0.85

0.8

load current

4X boost

3X boost

no boost

rmspk-pk

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System Identification (Transfer Function)

Digital PWM controllers offer the opportunity to identify the system dynamics (System-ID) by measuring the transfer function of the system in situ (in place).

No external test equipment No auxiliary circuits or probes

To do this we need to: Generate an excitation signal Inject that signal at a summing junction Capture the response of the system to the excitation

From this response, calculate the open loop gain From the open loop gain determine key performance metrics of

bandwidth, gain margin and phase margin. For a digitally controlled system the logical location to make the

measurement is just before or just after the digital compensator.

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Possible Measurement Locations

Inject a sinewave at r, x1 or x2

Measure response at node y, e, c, d or u

Solve for GH

G(s)

power stage

H(z)

digital compensator

-e

y'u'

digital controllerADCPWM

u y

x2x1

c r

yre

xec

Hcd

xdu

Guy

1

2

Given the following basic system equations:

The closed loop response at each node is:d

21

21

21

21

21

111

111

1

1

1111

1

1

11

111

xGH

Gx

GH

GHr

GHe

xGH

Gx

GHr

GHc

xGH

GHx

GH

Hr

GH

Hd

xGH

xGH

Hr

GH

Hu

xGH

Gx

GH

GHr

GH

GHy

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Calculate the open-loop gain from the closed-loop response

Note that the formula for calculating open loop gain contains the compensator gain H(f) if the system is excited before the compensator and measured after, or vice-a-versa.

This is not a big problem since a digital compensator is completely deterministic. Its frequency response can be calculated as:

yr

y

1

u

rH 1

d

rH 1

c

r1

e

r

yx

y

111

u

xH 11

d

xH 11

c

x 11 e

x

Hyx

Hy

2

12 u

xdx

d

2 Hcx

Hc

2ex

e

2

Loop gain G(f)H(f)

Measure response at:

y u d c e

inject at:

r

x1

x2

Solution of G(f)H(f) for various injection and measurement nodes:

smeassmeassmeas

meas

TfjTfTfjzazaz

bzbzbfH

2π2π2π sincosexp21

221

20

(for a 2nd order compensator)

Ts is the compensator sample period

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Type of Excitation to use for System-ID

sinewave white noise# of frequencies per measurement 1 N/2

Needed dynamic range narrow (few bits) wide (many bits)

Needed memory (RAM) 2 words 1k words or more

Max meas. interval 1 M samples* limited by available memory

Measurement signal to noise high medium

* 12 bit samples, 32 bit accumulator

Accurate Fast

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Sinewave Generation

Use table look-up technique Digital controllers such as the UCD9240 or TMS320C2801, have a

build-in sinewave table in ROM. For each sample, step through the table with a step size defined as

then generate the excitation signal as:phase = phase + step;

index = phase >> PHASE2INDEX; // use MSB bits for sine table index

sine_signal = sine_table(index); // lookup excitation signal value in table

When the end of the table is reached, wrap to the beginning of the table by subtracting the table length from the index.

By maintaining the fractional part of the table index and rounding to determine the table entry, very high frequency resolution can be obtained.

ratesample

meas

F

FNstep tableLen

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Response Measurement The definition of a Discrete Fourier Transform (DFT) is:

This says that we can calculate the real and imaginary magnitudes of the kth harmonic of a signal by multiplying that signal by a sine and cosine sequence and summing.

Since we've already generated a sinewave to inject into the loop as the excitation signal, the response measurement is simply:

cosSum += d*Xcos; // Accumulate cosine sum// for measurement node d

sinSum -= d*Xsin; // Accumulate sine sum// for measurement node d

(Note that since a sine is shifted by π/2 from a cosine, the cosine sequence is easily generated by adding an offset to the sine table index of 1/4 the table length.)

1

0

1

0

/

2sin2cosN

nn

N

n

Nnkjnk

nN

kjn

N

kv

evK

2π

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Example Calculation of G(f)H(f)

G(s)

power stage

H(z)

digital compensator

-e

y'u'

digital controllerADCPWM

y

xcos

r

Inject at r measure at d

• Return cosSum and sinSum for each injected excitation frequency.

Calculate open loop gain as follows:

d

z-1

z-1

xsin

cosSum

sinSum

121

sinSumjcosSum

XN

fjhfhd

rfHfHfGGain iropenloop

cos

• Where Xcos is the base to peak amplitude of the excitation and N is the # samples the response is summed over.

• Then plot magnitude and phase of G(f)H(f) to determine phase margin, gain margin and bandwidth.

xCPU

serial bus to host

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Practical Auto-ID measurements

Windowing The definition for the DFT produces the response just at harmonic

frequencies. These frequencies produce an integer number of cycles in the measurement interval. At other frequencies you need to do something to reduce "leakage".1. Window the measurement data. A raised cosine or triangle window are popular

options.

2. Modify the measurement interval so that an integer number of cycles are measured. (What we implemented.)

Settling We want just the forced response, so the controller needs to wait

some number of samples for the natural response to decay.

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Power Stage Transfer Function

The compensation in a digital PWM controller is deterministic

No gain or offset error Poles and zeros concisely defined.

So divide measured loop gain by known compensator TF.

Then use this measured response instead of modeled plant to choose compensation.

Note that the measured TF is more damped than the modeled TF.

Measurement takes into account losses not included in plant model. Losses show up as effective increase in resistance, which adds

damping.

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Monitor power system health

DC/low frequency measurements Vin, Iin Iout, Vout Temperature of each power stage

AC measurements Automatic Identification of the system transfer function Use linear (average) model of the plant to estimate component values

Look for a change in monitored parameter Use statistical process control techniques to decide if it has changed.

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Statistical Process Control

Many techniques Mean & Range charts Mean & Sigma charts

Key concepts Average a set (sample) of measurements.

This guarantees normally distributed measurement error based on central limit theorem.

Compare sample average to a confidence interval to decide if the mean has changed.

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Confidence Interval

Given where σ is the expected population standard deviation, n is

the sample size and is the probability that the sample mean is

within the confidence interval. Then the interval is Example

During product development μ, σ of open loop bandwidth were found to be to beμ = 55.0 kHzσ = 0.750 kHz.

Last 4 measurements of BW using Auto-IDare 56, 58, 53, 55 kHz. = 55.5 kHz

for 90% confidence is 1.96 So confidence interval is

[ 54.2650, 55.7350] Therefore we can say with 95% confidence

that the mean has not changed.

n

zk

2

2z

kk ,

sigma (zα/2)double sided

probability (%) event ppm

1.00 68.26 317k

1.65 90.00 100k

1.96 95.00 50k

2.00 95.44 45.6k

2.58 99.00 10k

3.00 99.73 2.7k

3.09 99.98 2.0k

3.29 99.99 1.0k

3.48 500

3.89 100

4.00 63.6

5.00 0.6

6.00 2 ppb

x

2z

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"Health" metrics

Transfer function based measures open loop bandwidth, phase margin, gain margin

Compare to expected values Don't have to measure full frequency range. One freq may be sufficient.

Power stage Q Lossy components cause Q to be reduced.

Input power vs. output power efficiency =

Average duty cycle (see next slide). Temperature

Power stage balance UCD9240 allows closed loop control of temperature balance

Power stage vs ambient (measured at controller IC.)

LOUT

ININ

iv

iv

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Average Duty Cycle

Capture duty cycle at output of digital compensator. At DC

Then

Monitor RS and compare to SPC control limits

FET switchs

RDCR

L1

RLOAD

CC

RC

RDS(ON)

RS

RSW(LOSS)IN

SLoad

LoadOUT VD

RR

Rv

IN

LsOUT

V

iRVD

L

OUTINS i

VVDR

0 5 10 15 2037.5

38

38.5

39

39.5

40

inductor current in Ampsdu

ty in

%

25 30 35 40 455

10

15

20

25

serie

s re

sist

ance

in m

Ohm

s

duty in %

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Conclusion

Digital PWM Controllers now offer: Programmable start/stop sequencing. Ability to Monitor power and health metrics.

Power stage voltages and currents Temperature Duty cycle

Complete control of compensation gain, zeros and poles. In situ measurement of system dynamics.

Enables measurement at other than the lab bench.(For instance, on factory floor or installed in end equipment.)

Use monitored parameters to assist in predicting failure Apply statistical confidence limits to decide if the parameter has changed. If a mean shift is indicated, issue a warning to the host system.

Design tools for Digital Power: Pull together sequencing, monitoring and control configuration in one place. Allow sophisticated, accurate frequency and time simulation of the target system. Automatic System Identification of the power supply dynamics. Automatic tuning of the loop compensation.