12f1501

2011 Microchip Technology Inc. Preliminary DS41615A

PIC12(L)F1501Data Sheet

8-Pin Flash, 8-Bit Microcontrollers

*8-bit, 8-pin devices protected by Microchips Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. andforeign patents and applications may be issued or pending.

Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breacher ou of in

rned

r cane.

mitteay b

workInformation contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyers risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,

knowledge, require using the Microchip products in a mannSheets. Most likely, the person doing so is engaged in theft

Microchip is willing to work with the customer who is conce

Neither Microchip nor any other semiconductor manufacturemean that we are guaranteeing the product as unbreakabl

Code protection is constantly evolving. We at Microchip are comproducts. Attempts to break Microchips code protection feature mallow unauthorized access to your software or other copyrightedDS41615A-page 2 Prelimin

suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

the code protection feature. All of these methods, to our tside the operating specifications contained in Microchips Data tellectual property.

about the integrity of their code.

guarantee the security of their code. Code protection does not

d to continuously improving the code protection features of oure a violation of the Digital Millennium Copyright Act. If such acts, you may have a right to sue for relief under that Act.ary 2011 Microchip Technology Inc.

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-61341-765-2

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Companys quality system processes and procedures are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

High-Performance RISC CPU: C Compiler Optimized Architecture Only 49 Instructions 1K Words Linear Program Memory Addressing 64 bytes Linear Data Memory Addressing Operating Speed:

- DC 20 MHz clock input- DC 200 ns instruction cycle

Interrupt Capability with Automatic Context Saving

16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset

Direct, Indirect and Relative Addressing modes:- Two full 16-bit File Select Registers (FSRs)- FSRs can read program and data memory

Flexible Oscillator Structure: 16 MHz Internal Oscillator Block:

- Factory calibrated to 1%, typical- Software selectable frequency range from

16 MHz to 31 kHz 31 kHz Low-Power Internal Oscillator Three External Clock modes up to 20 MHz

Special Microcontroller Features: Operating Voltage Range:

- 1.8V to 3.6V (PIC12LF1501)- 2.3V to 5.5V (PIC12F1501)

Self-Programmable under Software Control Power-on Reset (POR) Power-up Timer (PWRT) Programmable Low-Power Brown-Out Reset

(LPBOR) Extended Watchdog Timer (WDT):

- Programmable period from 1 ms to 256s Programmable Code Protection In-Circuit Serial Programming (ICSP) via Two

Pins Enhanced Low-Voltage Programming (LVP) Power-Saving Sleep mode:

- Low-Power Sleep mode- Low-Power BOR (LPBOR)

Integrated Temperature Indicator

Low-Power Features (PIC12LF1501): Standby Current:

- 20 nA @ 1.8V, typical Watchdog Timer Current:

- 200 nA @ 1.8V, typical Operating Current:

- 30 A/MHz @ 1.8V, typicalPeripheral Features: Analog-to-Digital Converter (ADC):

- 10-bit resolution- 4 external channels- 2 internal channels:

- Fixed Voltage Reference and DAC channels- Temperature Indicator channel

- Auto acquisition capability- Conversion available during Sleep

1 Comparator:- Rail-to-rail inputs- Power mode control- Software controllable hysteresis

Voltage Reference module:- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels- 1 rail-to-rail resistive 5-bit DAC with positive

reference selection 6 I/O Pins (1 Input-only Pin):

- High current sink/source 25 mA/25 mA- Individually programmable weak pull-ups- Individually programmable interrupt-on-change

(IOC) pins Timer0: 8-Bit Timer/Counter with 8-Bit

Programmable Prescaler Enhanced Timer1:

- 16-bit timer/counter with prescaler- External Gate Input mode

Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler

Four 10-bit PWM modules 2 Configurable Logic Cell (CLC) modules:

- 16 selectable input source signals- Four inputs per module- Software control of combinational/sequential

8-Pin Flash, 8-Bit Microcontrollers

PIC12(L)F1501 2011 Microchip Technology Inc. Preliminary DS41615A-page 3

128 Bytes High-Endurance Flash:- 100,000 write Flash endurance (minimum)

logic/state/clock functions- AND/OR/XOR/D Flop/D Latch/SR/JK- External or internal inputs/outputs- Operation while in Sleep

PIC12(L)F1501

Peripheral Features (Continued): Numerically Controlled Oscillator (NCO):

- 20-bit accumulator- 16-bit increment- True linear frequency control- High-speed clock input- Selectable Output modes:

- Fixed Duty Cycle (FDC) mode- Pulse Frequency (PF) mode

Complementary Waveform Generator (CWG):- 8 selectable signal sources- Selectable falling and rising edge dead-band

control- Polarity control- 4 auto-shutdown sources- Multiple input sources: PWM, CLC, NCO

PIC12(L)F1501/PIC16(L)F150X Family Types

Device

Dat

a Sh

eet I

ndex

Prog

ram

Mem

ory

Flas

h (w

ords

)

Dat

a SR

AM

(byt

es)

I/Os

(2)

10-b

it A

DC

(ch)

Com

para

tors

DA

C

Tim

ers

(8/1

6-bi

t)

PWM

EUSA

RT

MSS

P (I2

C/S

PI)

CW

G

CLC

NC

O

Deb

ug(1

)

XLP

PIC12(L)F1501 (1) 1024 64 6 4 1 1 2/1 4 1 2 1 H PIC16(L)F1503 (2) 2048 128 12 8 2 1 2/1 4 1 1 2 1 H PIC16(L)F1507 (3) 2048 128 18 12 2/1 4 1 2 1 H PIC16(L)F1508 (4) 4096 256 18 12 2 1 2/1 4 1 1 1 4 1 I/H YPIC16(L)F1509 (4) 8192 512 18 12 2 1 2/1 4 1 1 1 4 1 I/H YNote 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header.

2: One pin is input-only.Data Sheet Index: (Unshaded devices are described in this document.)

1: Future Product PIC12(L)F1501 Data Sheet, 8-Pin Flash, 8-bit Microcontrollers.2: DS41607 PIC16(L)F1503 Data Sheet, 14-Pin Flash, 8-bit Microcontrollers.3: DS41586 PIC16(L)F1507 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.4: DS41609 PIC16(L)F1508/1509 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.DS41615A-page 4 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501

FIGURE 1: 8-PIN PDIP, SOIC, MSOP, DFN DIAGRAM FOR PIC12(L)F1501

TABLE 1: 8-PIN ALLOCATION TABLE (PIC12(L)F1501)

I/O

8-Pi

n PD

IP/S

OIC

/MSO

P/D

FN

AD

C

Ref

eren

ce

Com

para

tor

Tim

er

CW

G

NC

O

CLC

PWM

Inte

rrup

t

Pull-

Up

Bas

ic

RA0 7 AN0 DACOUT1 C1IN+ CWG1B(1) CLC2IN1 PWM2 IOC Y ICSPDATRA1 6 AN1 VREF+ C1IN0- NCO1(1) CLC2IN0 IOC Y ICSPCLKRA2 5 AN2 DACOUT2 C1OUT T0CKI CWG1A(1)

CWG1FLT CLC1(1) PWM1 INT

IOCY

RA3 4 T1G(2) CLC1IN0 IOC Y MCLRVPP

RA4 3 AN3 C1IN1- T1G(1) CWG1B(2) CLC1(2) PWM3 IOC Y CLKOUTRA5 2 T1CKI CWG1A(2) NCO1(2)

NCO1CLKCLC1IN1

CLC2PWM4 IOC Y CLKIN

VDD 1 VDDVSS 8 VSS

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.2: Alternate location for peripheral pin function selected by the APFCON register.

PDIP, SOIC, MSOP, DFN

Note: See Table 1 for location of all peripheral functions.

1

2

3

4

8

7

6

5

VDD

RA5

RA4

MCLR/VPP/RA3

VSS

RA0/ICSPDAT

RA1/ICSPCLK

RA2PIC

12(L

)F15

01 2011 Microchip Technology Inc. Preliminary DS41615A-page 5

PIC12(L)F1501

Table of Contents1.0 Device Overview .......................................................................................................................................................................... 92.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 133.0 Memory Organization ................................................................................................................................................................. 154.0 Device Configuration .................................................................................................................................................................. 395.0 Oscillator Module........................................................................................................................................................................ 456.0 Resets ........................................................................................................................................................................................ 537.0 Interrupts .................................................................................................................................................................................... 618.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 759.0 Watchdog Timer ......................................................................................................................................................................... 7910.0 Flash Program Memory Control ................................................................................................................................................. 8311.0 I/O Ports ..................................................................................................................................................................................... 9912.0 Interrupt-On-Change ................................................................................................................................................................ 10513.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 10914.0 Temperature Indicator Module ................................................................................................................................................. 11115.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 11316.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 12717.0 Comparator Module.................................................................................................................................................................. 13118.0 Timer0 Module ......................................................................................................................................................................... 14119.0 Timer1 Module with Gate Control............................................................................................................................................. 14520.0 Timer2 Module ......................................................................................................................................................................... 15721.0 Pulse-Width Modulation (PWM) Module .................................................................................................................................. 16122.0 Configurable Logic Cell (CLC).................................................................................................................................................. 16723.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 18324.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 19325.0 In-Circuit Serial Programming (ICSP) ............................................................................................................................... 20926.0 Instruction Set Summary .......................................................................................................................................................... 21127.0 Electrical Specifications............................................................................................................................................................ 22528.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 24729.0 Development Support............................................................................................................................................................... 24930.0 Packaging Information.............................................................................................................................................................. 253Appendix A: Data Sheet Revision History.......................................................................................................................................... 267Index .................................................................................................................................................................................................. 269The Microchip Web Site ..................................................................................................................................................................... 275Customer Change Notification Service .............................................................................................................................................. 275Customer Support .............................................................................................................................................................................. 275Reader Response .............................................................................................................................................................................. 276Product Identification System............................................................................................................................................................. 277DS41615A-page 6 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. Wewelcome your feedback.

Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following: Microchips Worldwide Web site; http://www.microchip.com Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.

Customer Notification SystemRegister on our web site at www.microchip.com to receive the most current information on all of our products. 2011 Microchip Technology Inc. Preliminary DS41615A-page 7

PIC12(L)F1501

NOTES:DS41615A-page 8 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15011.0 DEVICE OVERVIEWThe PIC12(L)F1501 are described within this data sheet.They are available in 14-pin packages. Figure 1-1 showsa block diagram of the PIC12(L)F1501 devices. Table 1-2shows the pinout descriptions.

Reference Table 1-1 for peripherals available perdevice.

TABLE 1-1: DEVICE PERIPHERAL SUMMARY

Peripheral

PIC

12F1

501

PIC

12LF

1501

Analog-to-Digital Converter (ADC) Complementary Wave Generator (CWG) Digital-to-Analog Converter (DAC) Fixed Voltage Reference (FVR) Numerically Controlled Oscillator (NCO) Temperature Indicator Comparators

C1 Configurable Logic Cell (CLC)

CLC1 CLC2

PWM ModulesPWM1 PWM2 PWM3 PWM4

TimersTimer0 Timer1 Timer2 2011 Microchip Technology Inc. Preliminary DS41615A-page 9

PIC12(L)F1501

FIGURE 1-1: PIC12(L)F1501 BLOCK DIAGRAM

Note 1: See applicable chapters for more information on peripherals.2: See Table 1-1 for peripherals available on specific devices.

CPU

ProgramFlash Memory

RAM

TimingGeneration

INTRCOscillator

MCLR

(Figure 2-1)

NCO1

PWM4

Timer2Timer1Timer0CLC2

PWM1 PWM2 PWM3

PORTA

CWG1CLC1

ADC10-Bit FVR

Temp.Indicator

CLKIN

CLKOUT

C1

DACDS41615A-page 10 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TABLE 1-2: PIC12(L)F1501 PINOUT DESCRIPTION

Name Function Input TypeOutput Type Description

RA0/AN0/C1IN+/DACOUT1/CWG1B(1)/CLC2IN1/PWM2/ICSPDAT

RA0 TTL CMOS General purpose I/O.AN0 AN A/D Channel input.

C1IN+ AN Comparator positive input.DACOUT1 AN Digital-to-Analog Converter output.

CWG1B CMOS CWG complementary output.CLC2IN1 ST Configurable Logic Cell source input.

PWM2 CMOS Pulse Width Module source output.ICSPDAT ST CMOS ICSP Data I/O.

RA1/AN1/VREF+/C1IN0-/NCO1(1)/CLC2IN0/ICSPCLK


VREF+ AN A/D Positive Voltage Reference input.C1IN0- AN Comparator negative input.NCO1 CMOS Numerically Controlled Oscillator output.

CLC2IN0 ST Configurable Logic Cell source input.ICSPCLK ST ICSP Programming Clock.

RA2/AN2/C1OUT/DACOUT2/T0CKI/INT/PWM1/CLC1(1)/CWG1A(1)/CWG1FLT

RA2 ST CMOS General purpose I/O.AN2 AN A/D Channel input.

C1OUT CMOS Comparator output.DACOUT2 AN Digital-to-Analog Converter output.

T0CKI ST Timer0 clock input.INT ST External interrupt.

PWM1 CMOS Pulse Width Module source output.CLC1 CMOS Configurable Logic Cell source output.

CWG1A CMOS CWG complementary output.CWG1FLT ST Complementary Waveform Generator Fault input.

RA3/CLC1IN0/VPP/T1G(2)/MCLR RA3 TTL General purpose input.CLC1IN0 ST Configurable Logic Cell source input.

VPP HV Programming voltage.T1G ST Timer1 Gate input.

MCLR ST Master Clear with internal pull-up.RA4/AN3/C1IN1-/CWG1B(2)/CLC1(2)/PWM3/CLKOUT/T1G(1)


C1IN1- AN Comparator negative input.CWG1B CMOS CWG complementary output.

CLC1 CMOS Configurable Logic Cell source output.PWM3 CMOS Pulse Width Module source output.

CLKOUT CMOS FOSC/4 output.T1G ST Timer1 Gate input.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open DrainTTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.2: Alternate location for peripheral pin function selected by the APFCON register. 2011 Microchip Technology Inc. Preliminary DS41615A-page 11

PIC12(L)F1501RA5/CLKIN/T1CKI/CWG1A(2)/NCO1(2)/NCO1CLK/CLC1IN1/CLC2/PWM4

RA5 TTL CMOS General purpose I/O.CLKIN CMOS External clock input (EC mode).T1CKI ST Timer1 clock input.

CWG1A CMOS CWG complementary output.NCO1 ST Numerically Controlled Oscillator output.

NCO1CLK ST Numerically Controlled Oscillator Clock source input.CLC1IN1 ST Configurable Logic Cell source input.

CLC2 CMOS Configurable Logic Cell source output.PWM4 CMOS Pulse Width Module source output.

VDD VDD Power Positive supply.VSS VSS Power Ground reference.

TABLE 1-2: PIC12(L)F1501 PINOUT DESCRIPTION (CONTINUED)

Name Function Input TypeOutput Type Description

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open DrainTTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.2: Alternate location for peripheral pin function selected by the APFCON register.DS41615A-page 12 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15012.0 ENHANCED MID-RANGE CPUThis family of devices contain an enhanced mid-range8-bit CPU core. The CPU has 49 instructions. Interruptcapability includes automatic context saving. Thehardware stack is 16 levels deep and has Overflow andUnderflow Reset capability. Direct, Indirect, andRelative addressing modes are available. Two FileSelect Registers (FSRs) provide the ability to readprogram and data memory.

Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set

2.1 Automatic Interrupt Context Saving

During interrupts, certain registers are automaticallysaved in shadow registers and restored when returningfrom the interrupt. This saves stack space and usercode. See Section 7.5 Automatic Context Saving,for more information.

2.2 16-level Stack with Overflow and Underflow

These devices have an external stack memory 15 bitswide and 16 words deep. A Stack Overflow or Under-flow will set the appropriate bit (STKOVF or STKUNF)in the PCON register and, if enabled, will cause a soft-ware Reset. See section Section 3.4 Stack for moredetails.

2.3 File Select RegistersThere are two 16-bit File Select Registers (FSR). FSRscan access all file registers and program memory,which allows one Data Pointer for all memory. When anFSR points to program memory, there is one additionalinstruction cycle in instructions using INDF to allow thedata to be fetched. General purpose memory can nowalso be addressed linearly, providing the ability toaccess contiguous data larger than 80 bytes. There arealso new instructions to support the FSRs. SeeSection 3.5 Indirect Addressing for more details.

2.4 Instruction SetThere are 49 instructions for the enhanced mid-rangeCPU to support the features of the CPU. SeeSection 26.0 Instruction Set Summary for moredetails. 2011 Microchip Technology Inc. Preliminary DS41615A-page 13

PIC12(L)F1501

FIGURE 2-1: CORE BLOCK DIAGRAM

Data Bus 8

14ProgramBus

Instruction reg

Program Counter

8 Level Stack(13-bit)

Direct Addr 7

12

Addr MUX

FSR reg

STATUS reg

MUX

ALUInstructionDecode &

Control

TimingGeneration

CLKIN

CLKOUT

8

8

12

3

InternalOscillator

Block

ConfigurationData Bus 8

14ProgramBus

Instruction reg

Program Counter

8 Level Stack(13-bit)

Direct Addr 7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W Reg

InstructionDecode &

Control

TimingGeneration

8

8

3

InternalOscillator

Block

Configuration 15 Data Bus 8

14ProgramBus

Instruction Reg

Program Counter

16-Level Stack(15-bit)

Direct Addr 7

RAM Addr

Addr MUX

IndirectAddr

FSR0 Reg

STATUS Reg

MUX

ALUInstruction

Decode andControl

TimingGeneration

8

8

3

InternalOscillator

Block

Configuration

FlashProgramMemory

RAM

FSR regFSR regFSR1 Reg15

15

MU

X

15

Program MemoryRead (PMR)

12

FSR regFSR regBSR Reg

5

Power-upTimer

Power-onReset

WatchdogTimer

VDD

Brown-outReset

VSSVDD VSSVDD VSSDS41615A-page 14 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15013.0 MEMORY ORGANIZATIONThese devices contain the following types of memory:

Program Memory- Configuration Words- Device ID- User ID- Flash Program Memory

Data Memory- Core Registers- Special Function Registers- General Purpose RAM- Common RAM

The following features are associated with access andcontrol of program memory and data memory:

PCL and PCLATH Stack Indirect Addressing

3.1 Program Memory OrganizationThe enhanced mid-range core has a 15-bit programcounter capable of addressing 32K x 14 programmemory space. Table 3-1 shows the memory sizesimplemented. Accessing a location above theseboundaries will cause a wrap-around within theimplemented memory space. The Reset vector is at0000h and the interrupt vector is at 0004h (seeFigure 3-1).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Size (Words)Last Program Memory

AddressHigh-Endurance Flash

Memory Address Range(1)

PIC12F1501PIC12LF1501 1,024 03FFh 0380h-03FFh

Note 1: High-Endurance Flash applies to the low byte of each address in the range. 2011 Microchip Technology Inc. Preliminary DS41615A-page 15

PIC12(L)F1501

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR PIC12(L)F1501

3.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in pro-gram memory. The first method is to use tables ofRETLW instructions. The second method is to set anFSR to point to the program memory.

3.1.1.1 RETLW InstructionThe RETLW instruction can be used to provide accessto tables of constants. The recommended way to createsuch a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very sim-ple to implement. If your code must remain portablewith previous generations of microcontrollers, then theBRW instruction is not available so the older table readmethod must be used.

PC

15

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

Stack Level 1

0005hOn-chipProgramMemory

Page 003FFh

Wraps to Page 0

Wraps to Page 0

Wraps to Page 0

0400h

CALL, CALLW RETURN, RETLW

Interrupt, RETFIE

Rollover to Page 0

Rollover to Page 07FFFh

constantsBRW ;Add Index in W to

;program counter to;select data

RETLW DATA0 ;Index0 dataRETLW DATA1 ;Index1 dataRETLW DATA2RETLW DATA3

my_function; LOTS OF CODEMOVLW DATA_INDEXcall constants; THE CONSTANT IS IN WDS41615A-page 16 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501

3.1.1.2 Indirect Read with FSRThe program memory can be accessed as data by set-ting bit 7 of the FSRxH register and reading the match-ing INDFx register. The MOVIW instruction will place thelower 8 bits of the addressed word in the W register.Writes to the program memory cannot be performed viathe INDF registers. Instructions that access the pro-gram memory via the FSR require one extra instructioncycle to complete. Example 3-2 demonstrates access-ing the program memory via an FSR.

The HIGH directive will set bit if a label points to alocation in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR

3.2 Data Memory OrganizationThe data memory is partitioned into 32 memory bankswith 128 bytes in each bank. Each bank consists of(Figure 3-2):

12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM

The active bank is selected by writing the bank numberinto the Bank Select Register (BSR). Unimplementedmemory will read as 0. All data memory can beaccessed either directly (via instructions that use thefile registers) or indirectly via the two File SelectRegisters (FSR). See Section 3.5 IndirectAddressing for more information.Data memory uses a 12-bit address. The upper 7 bitsof the address define the Bank address and the lower5 bits select the registers/RAM in that bank.

3.2.1 CORE REGISTERSThe core registers contain the registers that directlyaffect the basic operation. The core registers occupythe first 12 addresses of every data memory bank(addresses x00h/x08h through x0Bh/x8Bh). Theseregisters are listed below in Table 3-2. For detailedinformation, see Table 3-4.

TABLE 3-2: CORE REGISTERS

constantsRETLW DATA0 ;Index0 dataRETLW DATA1 ;Index1 dataRETLW DATA2RETLW DATA3

my_function; LOTS OF CODEMOVLW LOW constantsMOVWF FSR1LMOVLW HIGH constantsMOVWF FSR1HMOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

Addresses BANKxx00h or x80h INDF0x01h or x81h INDF1x02h or x82h PCLx03h or x83h STATUSx04h or x84h FSR0Lx05h or x85h FSR0Hx06h or x86h FSR1Lx07h or x87h FSR1Hx08h or x88h BSRx09h or x89h WREGx0Ah or x8Ah PCLATHx0Bh or x8Bh INTCON 2011 Microchip Technology Inc. Preliminary DS41615A-page 17

PIC12(L)F1501

3.2.1.1 STATUS RegisterThe STATUS register, shown in Register 3-1, contains:

the arithmetic status of the ALU the Reset status

The STATUS register can be the destination for anyinstruction, like any other register. If the STATUSregister is the destination for an instruction that affectsthe Z, DC or C bits, then the write to these three bits isdisabled. These bits are set or cleared according to thedevice logic. Furthermore, the TO and PD bits are notwritable. Therefore, the result of an instruction with theSTATUS register as destination may be different thanintended.

For example, CLRF STATUS will clear the upper threebits and set the Z bit. This leaves the STATUS registeras 000u u1uu (where u = unchanged).It is recommended, therefore, that only BCF, BSF,SWAPF and MOVWF instructions are used to alter theSTATUS register, because these instructions do notaffect any Status bits. For other instructions notaffecting any Status bits (Refer to Section 26.0Instruction Set Summary).

Note 1: The C and DC bits operate as Borrowand Digit Borrow out bits, respectively, insubtraction.

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

TO PD Z DC(1) C(1)

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as 0u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets1 = Bit is set 0 = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as 0bit 4 TO: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction0 = A WDT time-out occurred

bit 3 PD: Power-Down bit1 = After power-up or by the CLRWDT instruction0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit1 = The result of an arithmetic or logic operation is zero0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)1 = A carry-out from the 4th low-order bit of the result occurred0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.DS41615A-page 18 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501

3.2.2 SPECIAL FUNCTION REGISTERThe Special Function Registers are registers used bythe application to control the desired operation ofperipheral functions in the device. The Special FunctionRegisters occupy the 20 bytes after the core registers ofevery data memory bank (addresses x0Ch/x8Chthrough x1Fh/x9Fh). The registers associated with theoperation of the peripherals are described in the appro-priate peripheral chapter of this data sheet.

3.2.3 GENERAL PURPOSE RAMThere are up to 80 bytes of GPR in each data memorybank. The Special Function Registers occupy the 20bytes after the core registers of every data memorybank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.2.3.1 Linear Access to GPRThe general purpose RAM can be accessed in anon-banked method via the FSRs. This can simplifyaccess to large memory structures. See Section 3.5.2Linear Data Memory for more information.

3.2.4 COMMON RAMThere are 16 bytes of common RAM accessible from allbanks.

FIGURE 3-2: BANKED MEMORY PARTITIONING

3.2.5 DEVICE MEMORY MAPSThe memory maps for PIC12(L)F1501 are as shown inTable 3-3.

0Bh0Ch

1Fh20h

6Fh70h

7Fh

00h

Common RAM(16 bytes)

General Purpose RAM(80 bytes maximum)

Core Registers(12 bytes)

Special Function Registers(20 bytes maximum)

Memory Region7-bit Bank Offset 2011 Microchip Technology Inc. Preliminary DS41615A-page 19

PIC12(L)F1501

A

BLE

3-3

:PI

C12

(L)F

1501

MEM

OR

Y M

AP

BA

NK

0B

AN

K 1

BA

NK

2B

AN

K 3

BA

NK

4B

AN

K 5

BA

NK

6B

AN

K 7

000h

Cor

e R

egis

ters

(T

able

3-2)

080h

Cor

e R

egis

ters

(T

able

3-2)

100h

Cor

e R

egis

ters

(T

able

3-2)

180h

Cor

e R

egis

ters

(T

able

3-2)

200h

Cor

e R

egis

ters

(T

able

3-2)

280h

Cor

e R

egis

ters

(T

able

3-2)

300h

Cor

e R

egis

ters

(T

able

3-2)

380h

Cor

e R

egis

ters

(T

able

3-2)

00B

h08

Bh

10B

h18

Bh

20B

h28

Bh

30B

h38

Bh

00C

hP

OR

TA08

Ch

TRIS

A10

Ch

LATA

18C

hA

NS

ELA

20C

hW

PU

A28

Ch

30

Ch

38

Ch

00

Dh

08

Dh

10

Dh

18

Dh

20

Dh

28

Dh

30

Dh

38

Dh

00

Eh

08

Eh

10

Eh

18

Eh

20

Eh

28

Eh

30

Eh

38

Eh

00

Fh

08Fh

10

Fh

18Fh

20

Fh

28Fh

30

Fh

38Fh

01

0h

090h

11

0h

190h

21

0h

290h

31

0h

390h

01

1hP

IR1

091h

PIE

111

1hC

M1C

ON

019

1hP

MA

DR

L21

1h

291h

31

1h

391h

IOC

AP

012h

PIR

209

2hP

IE2

112h

CM

1CO

N1

192h

PM

AD

RH

212h

29

2h

312h

39

2hIO

CAN

013h

PIR

309

3hP

IE3

113h

19

3hP

MD

ATL

213h

29

3h

313h

39

3hIO

CA

F01

4h

094h

11

4h

194h

PM

DA

TH21

4h

294h

31

4h

394h

01

5hTM

R0

095h

OPT

ION

_RE

G11

5hC

MO

UT

195h

PMC

ON

121

5h

295h

31

5h

395h

01

6hTM

R1L

096h

PC

ON

116h

BO

RC

ON

196h

PMC

ON

221

6h

296h

31

6h

396h

01

7hTM

R1H

097h

WD

TCO

N11

7hFV

RC

ON

197h

VR

EG

CO

N21

7h

297h

31

7h

397h

01

8hT1

CO

N09

8h

118h

DA

CC

ON

019

8h

218h

29

8h

318h

39

8h

019h

T1G

CO

N09

9hO

SCC

ON

119h

DA

CC

ON

119

9h

219h

29

9h

319h

39

9h

01A

hTM

R2

09A

hO

SC

STA

T11

Ah

19

Ah

21

Ah

29

Ah

31

Ah

39

Ah

01

Bh

PR

209

Bh

ADR

ESL

11B

h

19B

h

21B

h

29B

h

31B

h

39B

h

01C

hT2

CO

N09

Ch

AD

RE

SH11

Ch

19

Ch

21

Ch

29

Ch

31

Ch

39

Ch

01

Dh

09

Dh

AD

CO

N0

11D

hA

PFC

ON

19D

h

21D

h

29D

h

31D

h

39D

h

01E

h

09E

hA

DC

ON

111

Eh

19

Eh

21

Eh

29

Eh

31

Eh

39

Eh

01

Fh

09Fh

AD

CO

N2

11Fh

19

Fh

21Fh

29

Fh

31Fh

39

Fh

020h

Gen

eral

Pur

pose

R

egis

ter

48 B

ytes

0A0h

Uni

mpl

emen

ted

Rea

d as

0

120h

Uni

mpl

emen

ted

Rea

d as

0

1A0h

Uni

mpl

emen

ted

Rea

d as

0

220h

Uni

mpl

emen

ted

Rea

d as

0

2A0h

Uni

mpl

emen

ted

Rea

d as

0

320h

Uni

mpl

emen

ted

Rea

d as

0

3A0h

Uni

mpl

emen

ted

Rea

d as

0

04Fh

0EFh

050h

Uni

mpl

emen

ted

Rea

d as

0

06Fh

16Fh

1EFh

26Fh

2EFh

36Fh

3EFh

070h

Com

mon

RA

M

0F0h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

170h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

1F0h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

270h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

2F0h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

370h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

3F0h

Com

mon

RA

M(A

cces

ses

70h

7F

h)07

Fh0F

Fh17

Fh1F

Fh27

Fh2F

Fh37

Fh3F

Fh

Lege

nd:

= U

nim

plem

ente

d da

ta m

emor

y lo

catio

ns, r

ead

as 0

DS41615A-page 20 Preliminary 2011 Microchip Technology Inc.

T

PIC12(L)F1501AB

LE 3

-3:

PIC

12(L

)F15

01 M

EMO

RY

MA

P (C

ON

TIN

UED

)B

AN

K 8

BA

NK

9B

AN

K 1

0B

AN

K 1

1B

AN

K 1

2B

AN

K 1

3B

AN

K 1

4B

AN

K 1

540

0h

40B

h

Cor

e R

egis

ters

(T

able

3-2)

480h

48B

h

Cor

e R

egis

ters

(T

able

3-2)

500h

50B

h

Cor

e R

egis

ters

(T

able

3-2)

580h

58B

h

Cor

e R

egis

ters

(T

able

3-2)

600h

60B

h

Cor

e R

egis

ters

(T

able

3-2)

680h

68B

h

Cor

e R

egis

ters

(T

able

3-2)

700h

70B

h

Cor

e R

egis

ters

(T

able

3-2)

780h

78B

h

Cor

e R

egis

ters

(T

able

3-2)

40C

h

48C

h

50C

h

58C

h

60C

h

68C

h

70C

h

78C

h

40D

h

48D

h

50D

h

58D

h

60D

h

68D

h

70D

h

78D

h

40E

h

48E

h

50E

h

58E

h

60E

h

68E

h

70E

h

78E

h

40Fh

48

Fh

50Fh

58

Fh

60Fh

68

Fh

70Fh

78

Fh

410h

49

0h

510h

59

0h

610h

69

0h

710h

79

0h

411h

49

1h

511h

59

1h

611h

PWM

1DC

L69

1hC

WG

1DB

R71

1h

791h

41

2h

492h

51

2h

592h

61

2hP

WM

1DC

H69

2hC

WG

1DB

F71

2h

792h

41

3h

493h

51

3h

593h

61

3hP

WM

1CO

N69

3hC

WG

1CO

N0

713h

79

3h

414h

49

4h

514h

59

4h

614h

PWM

2DC

L69

4hC

WG

1CO

N1

714h

79

4h

415h

49

5h

515h

59

5h

615h

PW

M2D

CH

695h

CW

G1C

ON

271

5h

795h

41

6h

496h

51

6h

596h

61

6hP

WM

2CO

N69

6h

716h

79

6h

417h

49

7h

517h

59

7h

617h

PWM

3DC

L69

7h

717h

79

7h

418h

49

8hN

CO

1AC

CL

518h

59

8h

618h

PW

M3D

CH

698h

71

8h

798h

41

9h

499h

NC

O1A

CC

H51

9h

599h

61

9hP

WM

3CO

N69

9h

719h

79

9h

41A

h

49A

hN

CO

1AC

CU

51A

h

59A

h

61A

hPW

M4D

CL

69A

h

71A

h

79A

h

41B

h

49B

hN

CO

1IN

CL

51B

h

59B

h

61B

hP

WM

4DC

H69

Bh

71

Bh

79

Bh

41

Ch

49

Ch

NC

O1I

NC

H51

Ch

59

Ch

61

Ch

PW

M4C

ON

69C

h

71C

h

79C

h

41D

h

49D

h

51D

h

59D

h

61D

h

69D

h

71D

h

79D

h

41E

h

49E

hN

CO

1CO

N51

Eh

59

Eh

61

Eh

69

Eh

71

Eh

79

Eh

41

Fh

49Fh

NC

O1C

LK51

Fh

59Fh

61

Fh

69Fh

71

Fh

79Fh

42

0h

Uni

mpl

emen

ted

Rea

d as

0

4A0h

Uni

mpl

emen

ted

Rea

d as

0

520h

Uni

mpl

emen

ted

Rea

d as

0

5A0h

Uni

mpl

emen

ted

Rea

d as

0

620h

Uni

mpl

emen

ted

Rea

d as

0

6A0h

Uni

mpl

emen

ted

Rea

d as

0

720h

Uni

mpl

emen

ted

Rea

d as

0

7A0h

Uni

mpl

emen

ted

Rea

d as

0

46Fh

4EFh

56Fh

5EFh

64Fh

6EFh

76Fh

7EFh

470h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

4F0h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

570h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

5F0h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

650h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

6F0h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

770h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

7F0h

Com

mon

RA

M(A

cces

ses

70h

7F

h)47

Fh4F

Fh57

Fh5F

Fh67

Fh6F

Fh77

Fh7F

Fh

BA

NK

16

BA

NK

17

BA

NK

18

BA

NK

19

BA

NK

20

BA

NK

21

BA

NK

22

BA

NK

23

800h

80B

h

Cor

e R

egis

ters

(T

able

3-2

)

880h

88B

h

Cor

e R

egis

ters

(T

able

3-2)

900h

90B

h

Cor

e R

egis

ters

(T

able

3-2)

980h

98B

h

Cor

e R

egis

ters

(T

able

3-2)

A00

h

A0B

h

Cor

e R

egis

ters

(T

able

3-2)

A80

h

A8B

h

Cor

e R

egis

ters

(T

able

3-2)

B00

h

B0B

h

Cor

e R

egis

ters

(T

able

3-2)

B80

h

B8B

h

Cor

e R

egis

ters

(T

able

3-2)

80C

hU

nim

plem

ente

dR

ead

as 0

88C

hU

nim

plem

ente

dR

ead

as 0

90C

hU

nim

plem

ente

dR

ead

as 0

98C

hU

nim

plem

ente

dR

ead

as 0

A0C

hU

nim

plem

ente

dR

ead

as 0

A8C

hU

nim

plem

ente

dR

ead

as 0

B0C

hU

nim

plem

ente

dR

ead

as 0

B8C

hU

nim

plem

ente

dR

ead

as 0

86Fh

8EFh

96Fh

9EFh

A6Fh

AE

FhB

6Fh

BE

Fh87

0hC

omm

on R

AM

(Acc

esse

s70

h

7Fh)

8F0h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

970h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

9F0h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

A70

hC

omm

on R

AM

(Acc

esse

s70

h

7Fh)

AF0h

Com

mon

RA

M(A

cces

ses

70h

7F

h)

B70

hC

omm

on R

AM

(Acc

esse

s70

h

7Fh)

BF0

hC

omm

on R

AM

(Acc

esse

s70

h

7Fh)

87Fh

8FFh

97Fh

9FFh

A7Fh

AFF

hB

7Fh

BFF

hLe

gend

:=

Uni

mpl

emen

ted

data

mem

ory

loca

tions

, rea

d as

0 2011 Microchip Technology Inc. Preliminary DS41615A-page 21

T

PIC12(L)F1501

A

BLE

3-3

:PI

C12

(L)F

1501

MEM

OR

Y M

AP

(CO

NTI

NU

ED)

Lege

nd:

= U

nim

plem

ente

d da

ta m

emor

y lo

catio

ns, r

ead

as 0

.

BA

NK

24

BA

NK

25

BA

NK

26

BA

NK

27

BA

NK

28

BA

NK

29

BA

NK

30

BA

NK

31

C00

h

C0B

h

Cor

e R

egis

ters

(T

able

3-2)

C80

h

C8B

h

Cor

e R

egis

ters

(T

able

3-2)

D00

h

D0B

h

Cor

e R

egis

ters

(T

able

3-2)

D80

h

D8B

h

Cor

e R

egis

ters

(T

able

3-2)

E00

h

E0B

h

Cor

e R

egis

ters

(T

able

3-2)

E80

h

E8B

h

Cor

e R

egis

ters

(T

able

3-2)

F00h

F0B

h

Cor

e R

egis

ters

(T

able

3-2)

F80h

F8B

h

Cor

e R

egis

ters

(T

able

3-2)

C0C

h

C8C

h

D0C

h

D8C

h

E0C

h

E8C

h

F0C

h

See

Tab

le3-

3 fo

r re

gist

er m

appi

ng

deta

ils

F8C

h

See

Tab

le3-

3 fo

r re

gist

er m

appi

ng

deta

ils

C0D

h

C8D

h

D0D

h

D8D

h

E0D

h

E8D

h

F0D

hF8

Dh

C0E

h

C8E

h

D0E

h

D8E

h

E0E

h

E8E

h

F0E

hF8

Eh

C0F

h

C8F

h

D0F

h

D8F

h

E0F

h

E8F

h

F0Fh

F8Fh

C10

h

C90

h

D10

h

D90

h

E10

h

E90

h

F10h

F90h

C11

h

C91

h

D11

h

D91

h

E11

h

E91

h

F11h

F91h

C12

h

C92

h

D12

h

D92

h

E12

h

E92

h

F12h

F92h

C13

h

C93

h

D13

h

D93

h

E13

h

E93

h

F13h

F93h

C14

h

C94

h

D14

h

D94

h

E14

h

E94

h

F14h

F94h

C15

h

C95

h

D15

h

D95

h

E15

h

E95

h

F15h

F95h

C16

h

C96

h

D16

h

D96

h

E16

h

E96

h

F16h

F96h

C17

h

C97

h

D17

h

D97

h

E17

h

E97

h

F17h

F97h

C18

h

C98

h

D18

h

D98

h

E18

h

E98

h

F18h

F98h

C19

h

C99

h

D19

h

D99

h

E19

h

E99

h

F19h

F99h

C1A

h

C9A

h

D1A

h

D9A

h

E1A

h

E9A

h

F1A

hF9

Ah

C1B

h

C9B

h

D1B

h

D9B

h

E1B

h

E9B

h

F1B

hF9

Bh

C1C

h

C9C

h

D1C

h

D9C

h

E1C

h

E9C

h

F1C

hF9

Ch

C1D

h

C9D

h

D1D

h

D9D

h

E1D

h

E9D

h

F1D

hF9

Dh

C1E

h

C9E

h

D1E

h

D9E

h

E1E

h

E9E

h

F1E

hF9

Eh

C1F

h

C9F

h

D1F

h

D9F

h

E1F

h

E9F

h

F1Fh

F9Fh

C20

h

Uni

mpl

emen

ted

Rea

d as

0

CA

0h

Uni

mpl

emen

ted

Rea

d as

0

D20

h

Uni

mpl

emen

ted

Rea

d as

0

DA

0h

Uni

mpl

emen

ted

Rea

d as

0

E20

h

Uni

mpl

emen

ted

Rea

d as

0

EA0

h

Uni

mpl

emen

ted

Rea

d as

0

F20h

FA0h

C6F

hC

EFh

D6F

hD

EFh

E6F

hE

EFh

F6Fh

FEFh

C70

hC

omm

on R

AM

(Acc

esse

s70

h

7Fh)

CF0

hC

omm

on R

AM

(Acc

esse

s70

h

7Fh)

D70

hC

omm

on R

AM(A

cces

ses

70h

7F

h)

DF0

hC

omm

on R

AM(A

cces

ses

70h

7F

h)

E70

hC

omm

on R

AM(A

cces

ses

70h

7F

h)

EF0

hC

omm

on R

AM(A

cces

ses

70h

7F

h)

F70h

Com

mon

RAM

(Acc

esse

s70

h

7Fh)

FF0h

Com

mon

RAM

(Acc

esse

s70

h

7Fh)

CFF

hC

FFh

D7F

hD

FFh

E7F

hE

FFh

F7Fh

FFFhDS41615A-page 22 Preliminary 2011 Microchip Technology Inc.

T

PIC12(L)F1501

TABLE 3-3: PIC12(L)F1501 MEMORY MAP (CONTINUED)

Bank 30F0Ch F0Dh F0Eh F0Fh CLCDATAF10h CLC1CONF11h CLC1POLF12h CLC1SEL0F13h CLC1SEL1F14h CLC1GLS0F15h CLC1GLS1F16h CLC1GLS2F17h CLC1GLS3F18h CLC2CONF19h CLC2POLF1Ah CLC2SEL0F1Bh CLC2SEL1F1Ch CLC2GLS0F1Dh CLC2GLS1F1Eh CLC2GLS2F1Fh CLC2GLS3F20h

UnimplementedRead as 0

F6Fh

Bank 31F8Ch

FE3h

UnimplementedRead as 0

FE4h STATUS_SHADFE5h WREG_SHADFE6h BSR_SHADFE7h PCLATH_SHADFE8h FSR0L_SHADFE9h FSR0H_SHADFEAh FSR1L_SHADFEBh FSR1H_SHADFECh FEDh STKPTRFEEh TOSLFEFh TOSH

Legend: = Unimplemented data memory locations, read as 0. 2011 Microchip Technology Inc. Preliminary DS41615A-page 23

PIC12(L)F1501

3.2.6 CORE FUNCTION REGISTERS

SUMMARYThe Core Function registers listed in Table 3-4 can beaddressed from any Bank.

TABLE 3-4: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value onPOR, BORValue on all other Resets

Bank 0-31x00h or x80h INDF0

Addressing this location uses contents of FSR0H/FSR0L to address data memory(not a physical register) xxxx xxxx uuuu uuuu

x01h or x81h INDF1

Addressing this location uses contents of FSR1H/FSR1L to address data memory(not a physical register) xxxx xxxx uuuu uuuu

x02h or x82h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x03h or x83h STATUS TO PD Z DC C ---1 1000 ---q quuu

x04h or x84h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x05h or x85h FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x06h or x86h FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x07h or x87h FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x08h or x88h BSR BSR ---0 0000 ---0 0000

x09h or x89h WREG Working Register 0000 0000 uuuu uuuu

x0Ah or x8Ah PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

x0Bh or x8Bh INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0, r = reserved. Shaded locations are unimplemented, read as 0.DS41615A-page 24 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501

on all er ets

xxxx

--00-0----00

uuuuuuuuuuuu-u-uuxuu

000011110000

1111

--00-0----00

1111qquu0110

1-00--qquuuuuuuu0000--00----s 0.TABLE 3-5: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value onPOR, BORValue

othRes

Bank 000Ch PORTA RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx 00Dh Unimplemented

00Eh Unimplemented

00Fh Unimplemented

010h Unimplemented

011h PIR1 TMR1GIF ADIF TMR2IF TMR1IF 00-- --00 00-- 012h PIR2 C1IF NCO1IF --0- -0-- --0- 013h PIR3 CLC2IF CLC1IF ---- --00 ---- 014h Unimplemented

015h TMR0 Holding Register for the 8-bit Timer0 Count xxxx xxxx uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu 018h T1CON TMR1CS T1CKPS T1SYNC TMR1ON 0000 -0-0 uuuu 019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONET1GVAL T1GSS 0000 0x00 uuuu

01Ah TMR2 Timer2 Module Register 0000 0000 0000 01Bh PR2 Timer2 Period Register 1111 1111 1111 01Ch T2CON T2OUTPS TMR2ON T2CKPS -000 0000 -000 01Dh Unimplemented

01Eh Unimplemented

01Fh Unimplemented

Bank 108Ch TRISA TRISA5 TRISA4 (2) TRISA2 TRISA1 TRISA0 --11 1111 --11 08Dh Unimplemented

08Eh Unimplemented

08Fh Unimplemented

090h Unimplemented

091h PIE1 TMR1GIE ADIE TMR2IE TMR1IE 00-- --00 00-- 092h PIE2 C1IE NCO1IE --0- -0-- -00- 093h PIE3 CLC2IE CLC1IE ---- --00 ---- 094h Unimplemented

095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS 1111 1111 1111 096h PCON STKOVF STKUNF RWDT RMCLR RI POR BOR 00-1 11qq qq-q 097h WDTCON WDTPS SWDTEN --01 0110 --01 098h Unimplemented

099h OSCCON IRCF SCS -011 1-00 -011 09Ah OSCSTAT HFIOFR LFIOFR HFIOFS ---0 --00 ---q 09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu 09Ch ADRESH A/D Result Register High xxxx xxxx uuuu 09Dh ADCON0 CHS GO/DONE ADON -000 0000 -000 09Eh ADCON1 ADFM ADCS ADPREF 0000 --00 0000 09Fh ADCON2 TRIGSEL 0000 ---- 0000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read aNote 1: PIC12F1501 only.

2: Unimplemented, read as 1. 2011 Microchip Technology Inc. Preliminary DS41615A-page 25

PIC12(L)F1501

-uuu

-100-000

---0---u0000-0--0000

0-00

-111

00000000uuuuuuuuq0000000--01

on all er ets

s 0. Bank 210Ch LATA LATA5 LATA4 LATA2 LATA1 LATA0 --xx -xxx --uu 10Dh Unimplemented

10Eh Unimplemented

10Fh Unimplemented

110h Unimplemented

111h CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1HYS C1SYNC 0000 -100 0000 112h CM1CON1 C1INTP C1INTN C1PCH C1NCH 0000 -000 0000 113h Unimplemented

114h Unimplemented

115h CMOUT MC1OUT ---- ---0 ---- 116h BORCON SBOREN BORFS BORRDY 10-- ---q uu-- 117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR ADFVR 0q00 0000 0q00 118h DACCON0 DACEN DACOE1 DACOE2 DACPSS 0-00 -0-- 0-00 119h DACCON1 DACR ---0 0000 ---0

11Ahto

11Ch Unimplemented

11Dh APFCON CWG1BSEL CWG1ASEL T1GSEL CLC1SEL NCO1SEL 00-- 0-00 00-- 11Eh Unimplemented

11Fh Unimplemented

Bank 318Ch ANSELA ANSA4 ANSA2 ANSA1 ANSA0 ---1 -111 ---1 18Dh Unimplemented

18Eh Unimplemented

18Fh Unimplemented

190h Unimplemented

191h PMADRL Flash Program Memory Address Register Low Byte 0000 0000 0000 192h PMADRH Flash Program Memory Address Register High Byte -000 0000 -000 193h PMDATL Flash Program Memory Read Data Register Low Byte xxxx xxxx uuuu 194h PMDATH Flash Program Memory Read Data Register High Byte --xx xxxx --uu 195h PMCON1 (2) CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 196h PMCON2 Flash Program Memory Control Register 2 0000 0000 0000 197h VREGCON(1) VREGPM Reserved ---- --01 ----

198hto

19Fh Unimplemented

TABLE 3-5: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)


othRes

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read aNote 1: PIC12F1501 only.

2: Unimplemented, read as 1.DS41615A-page 26 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501

1111

000000000000

00000000000000000000

---0--00

on all er ets

s 0. Bank 420Ch WPUA WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11

20Dhto

21Fh Unimplemented

Bank 528Ch

to29Fh

Unimplemented

Bank 630Ch

to31Fh

Unimplemented

Bank 738Ch

to390h

Unimplemented

391h IOCAP IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 392h IOCAN IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 393h IOCAF IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00

394hto

39Fh Unimplemented

Bank 840Ch

to41Fh

Unimplemented

Bank 948Ch

to497h

Unimplemented

498h NCO1ACCL NCO1ACC 0000 0000 0000 499h NCO1ACCH NCO1ACC 0000 0000 0000 49Ah NCO1ACCU NCO1ACC 0000 0000 0000 49Bh NCO1INCL NCO1INC 0000 0000 0000 49Ch NCO1INCH NCO1INC 0000 0000 0000 49Dh Unimplemented

49Eh NCO1CON N1EN N1OE N1OUT N1POL N1PFM 0000 ---0 0000 49Fh NCO1CLK N1PWS N1CKS 0000 --00 0000



othRes



PIC12(L)F1501

----uuuu--------uuuu--------uuuu--------uuuu----

0000xxxx0--0-000-000

on all er ets

s 0. Bank 1050Ch

to51Fh

Unimplemented

Bank 1158Ch

to59Fh

Unimplemented

Bank 1260Ch

to610h

Unimplemented

611h PWM1DCL PWM1DCL 00-- ---- 00-- 612h PWM1DCH PWM1DCH xxxx xxxx uuuu 613h PWM1CON0 PWM1EN PWM1OE PWM1OUT PWM1POL 0000 ---- 0000 614h PWM2DCL PWM2DCL 00-- ---- 00-- 615h PWM2DCH PWM2DCH xxxx xxxx uuuu 616h PWM2CON0 PWM2EN PWM2OE PWM2OUT PWM2POL 0000 ---- 0000 617h PWM3DCL PWM3DCL 00-- ---- 00-- 618h PWM3DCH PWM3DCH xxxx xxxx uuuu 619h PWM3CON0 PWM3EN PWM3OE PWM3OUT PWM3POL 0000 ---- 0000 61Ah PWM4DCL PWM4DCL 00-- ---- 00-- 61Bh PWM4DCH PWM4DCH xxxx xxxx uuuu 61Ch PWM4CON0 PWM4EN PWM4OE PWM4OUT PWM4POL 0000 ---- 0000

61Dhto

61Fh Unimplemented

Bank 1368Ch

to690h

Unimplemented

691h CWG1DBR CWG1DBR --00 0000 --00 692h CWG1DBF CWG1DBF --xx xxxx --xx 693h CWG1CON0 G1EN G1OEB G1OEA G1POLB G1POLA G1CS0 0000 0--0 0000 694h CWG1CON1 G1ASDLB G1ASDLA G1IS 0000 -000 0000 695h CWG1CON2 G1ASE G1ARSEN G1ASDC1 G1ASDFLT G1ASDCLC2 00-- -000 00--

696hto

69Fh Unimplemented

Bank 14-29



othRes



PIC12(L)F1501

--000000uuuu-uuu-uuuuuuuuuuuuuuuuuuu0000uuuu-uuu-uuuuuuuuuuuuuuuuuuu

on all er ets

s 0. Banks 14-29x0Ch/x8Ch x1Fh/x9Fh

Unimplemented

Bank 30 F0Ch

toF0Eh

Unimplemented

F0Fh CLCDATA MLC1OUT MLC2OUT ---- --00 ---- F10h CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN LC1MODE 0000 0000 0000 F11h CLC1POL LC1POL LC1G4POL LC1G3POL LC1G2POL LC1G1POL 0--- xxxx 0--- F12h CLC1SEL0 LC1D2S LC1D1S -xxx -xxx -uuu F13h CLC1SEL1 LC1D4S LC1D3S -xxx -xxx -uuu F14h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu F15h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu F16h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu F17h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu F18h CLC2CON LC2EN LC2OE LC2OUT LC2INTP LC2INTN LC2MODE 0000 0000 0000 F19h CLC2POL LC2POL LC2G4POL LC2G3POL LC2G2POL LC2G1POL 0--- xxxx 0--- F1Ah CLC2SEL0 LC2D2S LC2D1S -xxx -xxx -uuu F1Bh CLC2SEL1 LC2D4S LC2D3S -xxx -xxx -uuu F1Ch CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu F1Dh CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu F1Eh CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu F1Fh CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu

F20hto

F6Fh Unimplemented



othRes



PIC12(L)F1501

-uuu

uuuu

uuuu

uuuu

uuuu

uuuu

uuuu

uuuu

1111uuuuuuuu

on all er ets

s 0. Bank 31F8Ch FE3h

Unimplemented

FE4h STATUS_SHAD

Z_SHAD DC_SHAD C_SHAD ---- -xxx ----

FE5h WREG_SHAD

Working Register Shadow xxxx xxxx uuuu

FE6h BSR_SHAD

Bank Select Register Shadow ---x xxxx ---u

FE7h PCLATH_SHAD

Program Counter Latch High Register Shadow -xxx xxxx uuuu

FE8h FSR0L_SHAD

Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu

FE9h FSR0H_SHAD

Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu

FEAh FSR1L_SHAD

Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu

FEBh FSR1H_SHAD

Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu

FECh Unimplemented

FEDh STKPTR Current Stack Pointer ---1 1111 ---1 FEEh TOSL Top-of-Stack Low byte xxxx xxxx uuuu FEFh TOSH Top-of-Stack High byte -xxx xxxx -uuu



othRes



PIC12(L)F1501

3.3 PCL and PCLATHThe Program Counter (PC) is 15 bits wide. The low bytecomes from the PCL register, which is a readable andwritable register. The high byte (PC) is not directlyreadable or writable and comes from PCLATH. On anyReset, the PC is cleared. Figure 3-3 shows the fivesituations for the loading of the PC.

FIGURE 3-3: LOADING OF PC IN DIFFERENT SITUATIONS

3.3.1 MODIFYING PCLExecuting any instruction with the PCL register as thedestination simultaneously causes the Program Coun-ter PC bits (PCH) to be replaced by the contentsof the PCLATH register. This allows the entire contentsof the program counter to be changed by writing thedesired upper 7 bits to the PCLATH register. When thelower 8 bits are written to the PCL register, all 15 bits ofthe program counter will change to the values con-tained in the PCLATH register and those being writtento the PCL register.

3.3.2 COMPUTED GOTOA computed GOTO is accomplished by adding an offset tothe program counter (ADDWF PCL). When performing atable read using a computed GOTO method, care shouldbe exercised if the table location crosses a PCL memoryboundary (each 256-byte block). Refer to ApplicationNote AN556, Implementing a Table Read (DS00556).

3.3.3 COMPUTED FUNCTION CALLSA computed function CALL allows programs to maintaintables of functions and provide another way to executestate machines or look-up tables. When performing atable read using a computed function CALL, careshould be exercised if the table location crosses a PCLmemory boundary (each 256-byte block).

If using the CALL instruction, the PCH and PCLregisters are loaded with the operand of the CALLinstruction. PCH is loaded with PCLATH.

The CALLW instruction enables computed calls by com-bining PCLATH and W to form the destination address.A computed CALLW is accomplished by loading the Wregister with the desired address and executing CALLW.The PCL register is loaded with the value of W andPCH is loaded with PCLATH.

3.3.4 BRANCHINGThe branching instructions add an offset to the PC.This allows relocatable code and code that crossespage boundaries. There are two forms of branching,BRW and BRA. The PC will have incremented to fetchthe next instruction in both cases. When using eitherbranching instruction, a PCL memory boundary may becrossed.

If using BRW, load the W register with the desiredunsigned address and execute BRW. The entire PC willbe loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +,the signed value of the operand of the BRA instruction.

PCLPCH 014PC

PCLPCH 014PC

ALU Result876

PCLATH0

Instruction withPCL as

Destination

GOTO, CALL

OPCODE 1146

PCLATH0

PCLPCH 014PC

W876

PCLATH0

CALLW

PCLPCH 014PC

PC + W15

BRW

PCLPCH 014PC

PC + OPCODE 15

BRA 2011 Microchip Technology Inc. Preliminary DS41615A-page 31

PIC12(L)F1501

3.4 StackAll devices have a 16-level x 15-bit wide hardwarestack (refer to Figures 3-4 through 3-7). The stackspace is not part of either program or data space. ThePC is PUSHed onto the stack when CALL or CALLWinstructions are executed or an interrupt causes abranch. The stack is POPed in the event of a RETURN,RETLW or a RETFIE instruction execution. PCLATH isnot affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVRENbit is programmed to 0 (Configuration Words). Thismeans that after the stack has been PUSHed sixteentimes, the seventeenth PUSH overwrites the value thatwas stored from the first PUSH. The eighteenth PUSHoverwrites the second PUSH (and so on). TheSTKOVF and STKUNF flag bits will be set on an Over-flow/Underflow, regardless of whether the Reset isenabled.

3.4.1 ACCESSING THE STACKThe stack is available through the TOSH, TOSL andSTKPTR registers. STKPTR is the current value of theStack Pointer. TOSH:TOSL register pair points to theTOP of the stack. Both registers are read/writable. TOSis split into TOSH and TOSL due to the 15-bit size of thePC. To access the stack, adjust the value of STKPTR,which will position TOSH:TOSL, then read/write toTOSH:TOSL. STKPTR is 5 bits to allow detection ofoverflow and underflow.

During normal program operation, CALL, CALLW andInterrupts will increment STKPTR while RETLW,RETURN, and RETFIE will decrement STKPTR. At anytime, STKPTR can be inspected to see how muchstack is left. The STKPTR always points at the currentlyused place on the stack. Therefore, a CALL or CALLWwill increment the STKPTR and then write the PC, anda return will unload the PC and then decrement theSTKPTR.

Reference Figure 3-4 through Figure 3-7 for examplesof accessing the stack.

FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1

Note 1: There are no instructions/mnemonicscalled PUSH or POP. These are actionsthat occur from the execution of theCALL, CALLW, RETURN, RETLW andRETFIE instructions or the vectoring toan interrupt address.

Note: Care should be taken when modifying theSTKPTR while interrupts are enabled.

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x0000

STKPTR = 0x1F

Initial Stack Configuration:

After Reset, the stack is empty. Theempty stack is initialized so the StackPointer is pointing at 0x1F. If the StackOverflow/Underflow Reset is enabled, theTOSH/TOSL registers will return 0. Ifthe Stack Overflow/Underflow Reset isdisabled, the TOSH/TOSL registers willreturn the contents of stack address 0x0F.

0x1F STKPTR = 0x1F

Stack Reset Disabled(STVREN = 0)

Stack Reset Enabled(STVREN = 1)

TOSH:TOSL

TOSH:TOSLDS41615A-page 32 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501



0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00 STKPTR = 0x00

This figure shows the stack configurationafter the first CALL or a single interrupt.If a RETURN instruction is executed, thereturn address will be placed in theProgram Counter and the Stack Pointerdecremented to the empty state (0x1F).

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

Return Address0x06

Return Address0x05

Return Address0x04

Return Address0x03

Return Address0x02

Return Address0x01

Return Address0x00

STKPTR = 0x06

After seven CALLs or six CALLs and aninterrupt, the stack looks like the figureon the left. A series of RETURN instructionswill repeatedly place the return addresses into the Program Counter and pop the stack.

TOSH:TOSL 2011 Microchip Technology Inc. Preliminary DS41615A-page 33

PIC12(L)F1501


3.4.2 OVERFLOW/UNDERFLOW RESETIf the STVREN bit in Configuration Words isprogrammed to 1, the device will be reset if the stackis PUSHed beyond the sixteenth level or POPedbeyond the first level, setting the appropriate bits(STKOVF or STKUNF, respectively) in the PCONregister.

3.5 Indirect AddressingThe INDFn registers are not physical registers. Anyinstruction that accesses an INDFn register actuallyaccesses the register at the address specified by theFile Select Registers (FSR). If the FSRn addressspecifies one of the two INDFn registers, the read willreturn 0 and the write will not occur (though Status bitsmay be affected). The FSRn register value is createdby the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows anaddressing space with 65536 locations. These locationsare divided into three memory regions:

Traditional Data Memory Linear Data Memory Program Flash Memory

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00 STKPTR = 0x10

When the stack is full, the next CALL oran interrupt will set the Stack Pointer to0x10. This is identical to address 0x00so the stack will wrap and overwrite thereturn address at 0x00. If the StackOverflow/Underflow Reset is enabled, aReset will occur and location 0x00 willnot be overwritten.

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

TOSH:TOSLDS41615A-page 34 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501

FIGURE 3-8: INDIRECT ADDRESSING

0x0000

0x0FFF

Traditional

FSRAddressRange

Data Memory

0x1000Reserved

LinearData Memory

Reserved

0x2000

0x29AF

0x29B0

0x7FFF0x8000

0xFFFF

0x0000

0x0FFF

0x0000

0x7FFF

ProgramFlash Memory

Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.

0x1FFF 2011 Microchip Technology Inc. Preliminary DS41615A-page 35

PIC12(L)F1501

3.5.1 TRADITIONAL DATA MEMORYThe traditional data memory is a region from FSRaddress 0x000 to FSR address 0xFFF. The addressescorrespond to the absolute addresses of all SFR, GPRand common registers.

FIGURE 3-9: TRADITIONAL DATA MEMORY MAP

Indirect AddressingDirect Addressing

Bank Select Location Select

4 BSR 6 0From Opcode FSRxL7 0

Bank Select Location Select00000 00001 00010 11111

0x00

0x7F

Bank 0 Bank 1 Bank 2 Bank 31

0 FSRxH7 0

0 0 0 0DS41615A-page 36 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501

3.5.2 LINEAR DATA MEMORYThe linear data memory is the region from FSRaddress 0x2000 to FSR address 0x29AF. This region isa virtual region that points back to the 80-byte blocks ofGPR memory in all the banks.

Unimplemented memory reads as 0x00. Use of thelinear data memory region allows buffers to be largerthan 80 bytes because incrementing the FSR beyondone bank will go directly to the GPR memory of the nextbank.

The 16 bytes of common memory are not included inthe linear data memory region.

FIGURE 3-10: LINEAR DATA MEMORY MAP

3.5.3 PROGRAM FLASH MEMORYTo make constant data access easier, the entireprogram Flash memory is mapped to the upper half ofthe FSR address space. When the MSB of FSRnH isset, the lower 15 bits are the address in programmemory which will be accessed through INDF. Only thelower 8 bits of each memory location is accessible viaINDF. Writing to the program Flash memory cannot beaccomplished via the FSR/INDF interface. Allinstructions that access program Flash memory via theFSR/INDF interface will require one additionalinstruction cycle to complete.

FIGURE 3-11: PROGRAM FLASH MEMORY MAP

70 1

70 0

Location Select 0x2000

FSRnH FSRnL

0x020

Bank 00x06F0x0A0Bank 10x0EF0x120

Bank 20x16F

0xF20Bank 30

0xF6F0x29AF

0

71

70 0

Location Select 0x8000

FSRnH FSRnL

0x0000

0x7FFF0xFFFF

ProgramFlashMemory(low 8bits) 2011 Microchip Technology Inc. Preliminary DS41615A-page 37

PIC12(L)F1501

NOTES:DS41615A-page 38 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15014.0 DEVICE CONFIGURATIONDevice Configuration consists of Configuration Words,Code Protection and Device ID.

4.1 Configuration WordsThere are several Configuration Word bits that allowdifferent oscillator and memory protection options.These are implemented as Configuration Word 1 at8007h and Configuration Word 2 at 8008h. 2011 Microchip Technology Inc. Preliminary DS41615A-page 39

PIC12(L)F1501

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

U-1 U-1 R/P-1 R/P-1 R/P-1 U-1

CLKOUTEN BOREN bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1CP MCLRE PWRTE WDTE FOSC

bit 7 bit 0

Legend:R = Readable bit P = Programmable bit U = Unimplemented bit, read as 10 = Bit is cleared 1 = Bit is set -n = Value when blank or after Bulk Erase

bit 13-12 Unimplemented: Read as 1bit 11 CLKOUTEN: Clock Out Enable bit

1 = CLKOUT function is disabled. I/O function on the CLKOUT pin0 = CLKOUT function is enabled on the CLKOUT pin

bit 10-9 BOREN: Brown-out Reset Enable bits(1)11 = BOR enabled10 = BOR enabled during operation and disabled in Sleep01 = BOR controlled by SBOREN bit of the BORCON register00 = BOR disabled

bit 8 Unimplemented: Read as 1bit 7 CP: Code Protection bit(2)

1 = Program memory code protection is disabled0 = Program memory code protection is enabled

bit 6 MCLRE: MCLR/VPP Pin Function Select bitIf LVP bit = 1:

This bit is ignored.If LVP bit = 0:

1 =MCLR/VPP pin function is MCLR; Weak pull-up enabled.0 =MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUE3 bit.bit 5 PWRTE: Power-Up Timer Enable bit

1 = PWRT disabled0 = PWRT enabled

bit 4-3 WDTE: Watchdog Timer Enable bits11 = WDT enabled10 = WDT enabled while running and disabled in Sleep01 = WDT controlled by the SWDTEN bit in the WDTCON register00 = WDT disabled

bit 2 Unimplemented: Read as 1bit 1-0 FOSC: Oscillator Selection bits

11 = ECH: External Clock, High-Power mode: on CLKIN pin10 = ECM: External Clock, Medium-Power mode: on CLKIN pin01 = ECL: External Clock, Low-Power mode: on CLKIN pin00 = INTOSC oscillator: I/O function on CLKIN pin

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.2: Once enabled, code-protect can only be disabled by bulk erasing the device.DS41615A-page 40 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501

REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

R/P-1 U-1 R/P-1 R/P-1 R/P-1 U-1

LVP LPBOR BORV STVREN bit 13 bit 8

U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 WRT

bit 7 bit 0

Legend:R = Readable bit P = Programmable bit U = Unimplemented bit, read as 10 = Bit is cleared 1 = Bit is set -n = Value when blank or after Bulk Erase

bit 13 LVP: Low-Voltage Programming Enable bit(1)1 = Low-voltage programming enabled0 = High-voltage on MCLR must be used for programming

bit 12 Unimplemented: Read as 1bit 11 LPBOR: Low-Power BOR Enable bit

1 = Low-Power Brown-out Reset is disabled0 = Low-Power Brown-out Reset is enabled

bit 10 BORV: Brown-out Reset Voltage Selection bit(2)1 = Brown-out Reset voltage (Vbor), low trip point selected0 = Brown-out Reset voltage (Vbor), high trip point selected

bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit1 = Stack Overflow or Underflow will cause a Reset0 = Stack Overflow or Underflow will not cause a Reset

bit 8-2 Unimplemented: Read as 1bit 1-0 WRT: Flash Memory Self-Write Protection bits

1 kW Flash memory:11 = Write protection off10 = 000h to 0FFh write-protected, 100h to 3FFh may be modified01 = 000h to 1FFh write-protected, 200h to 3FFh may be modified00 = 000h to 3FFh write-protected, no addresses may be modified

Note 1: The LVP bit cannot be programmed to 0 when Programming mode is entered via LVP.2: See Vbor parameter for specific trip point voltages. 2011 Microchip Technology Inc. Preliminary DS41615A-page 41

PIC12(L)F1501

4.2 Code ProtectionCode protection allows the device to be protected fromunauthorized access. Internal access to the programmemory is unaffected by any code protection setting.

4.2.1 PROGRAM MEMORY PROTECTIONThe entire program memory space is protected fromexternal reads and writes by the CP bit in ConfigurationWords. When CP = 0, external reads and writes ofprogram memory are inhibited and a read will return all0s. The CPU can continue to read program memory,regardless of the protection bit settings. Writing theprogram memory is dependent upon the writeprotection setting. See Section 4.3 WriteProtection for more information.

4.3 Write ProtectionWrite protection allows the device to be protected fromunintended self-writes. Applications, such asbootloader software, can be protected while allowingother regions of the program memory to be modified.

The WRT bits in Configuration Words define thesize of the program memory block that is protected.

4.4 User IDFour memory locations (8000h-8003h) are designated asID locations where the user can store checksum or othercode identifi

12f1501

Documents

Transcript of 12f1501