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12.2 Silicon Solar Cells 12.2.1. High Efficiency Crystalline Solar Cells

a. Monocrystalline silicon solar cells on p-type substrates: The following processes are being developed using the infrastructure available in the centre of excellence in nanoelectronics (CEN) at IIT Bombay. In the meanwhile PV specific process and characterization equipment are being procured and the learning would be further refined using the characterization tools and transferred to the new processing tools. Cell fabrication (JRF: Karthick Murukesan): We have fabricated solar cells from p type crystalline silicon, with efficiency of 10% with area of 1cm2 and efficiency of 11.3% with area 0.25 cm2 without correcting for the contact area coverage ~ 10%. The cells have antireflection coating, but have no texturing. This establishes a baseline process using the available silicon wafers. The process will now be checked for repeatability. This will also allow us to formulate a simpler process which can be used for training of students. Phosphorous diffusion from solid sources and plasma immersion implantation for junctions (JRF: Gaudhaman J.): The phosphorous junctions formed by diffusions at 890C was analyzed using SIMS at NPL. Also we have developed a plasma immersion ion implantation (PIII) system at IIT-B for phosphorous implantation in silicon. The SIMS profiles of the two cases is shown below. The diffused sample had given a sheet resistance of 80 ohm/sq. It is noticed that the surface has a high concentration of phosphorous in the diffused case and the carrier lifetime in this layer (dead layer) is expected to be low. A process is developed for the removal of the deadlayer, Fig. yy and optimization of the diffusion and deadlayer removal to obtain a sheet resistance of 70 ohm/sq. without the deadlayer is on-going. The PIII profile is looking very promising without any deadlayers.

Fig. xx: SIMS profiles of phosphorous in Si obtained by diffusion from a solid source and PIII.

Fig. yy: Etch rate of the deadlayer for various HNA solutions.

Optimization of SiNx for ARC: (students: Sandeep S. S. and Jim John): SiNx deposited by ICPCVD was found to change color after contact firing anneal. The color changed from deep blue to whitish blue. FTIR data shows that the anneal results in desorption of H species from the film. Several SiNx recipes with SiH4 + N2 and SiH4 + NH3 have been

A B C D E0

200

400

1000

1200

1400 Etch rate

Etch

rate

(nm

/min

)

HNA Solution0 100 200 300 400 500 600 700 8001E16

1E17

1E18

1E19

1E20

1E21

Diffused Plasma Doped

Phos

phor

us (c

m-3

)

Depth (nm)

2

developed and characterized for growth rate and refractive index. These are being evaluated after annealing.

Fig. zz: Si-H2 stretching mode (2150 cm-1) seen before anneal is not seen after anneal.

b. Monocrystalline silicon solar cells on n-type substrates (Student: Karthick Murukesan):

We have initiated some trials of fabricating solar cells starting with n type silicon wafers. This requires diffusion of boron into n type silicon base to form the emitter region. It turns out that a layer of silicon boride is formed near the surface region of the diffused silicon wafer , which is quite impervious. A low temperature oxidation treatment converts the boride into oxide which can be removed in conventional way . We have investigated the thin boride layer by TEM measurements, EDAX and AFM measurements before and after the low temperature oxidation followed by deglazing treatment. Material analysis was carried out at DMRL, Hyderabad with collaboration from D. V. Sridhara Rao and K. Muraleedharan. Monocrystalline silicon solar cells on n-type substrates (Student: Bandana Singha): Boron diffusion was done from spin-on-source (B-SOD) spin-coated over the n-type substrate and subsequent drive-in at 1000 OC. The resistivity, sheet resistance and carrier lifetime of the sample was measured at three stages-(a) just after RCA cleaning (b) after spin coating the SOD and (c) after diffusion at 1000 OC.

Results After drive in process sheet resistance value decreases from 90 (Ω/sq) from RCA cleaned wafer to 54.7 (Ω/sq) and minority carrier lifetime measured at specified MCD 1x 1015cm-3 changes from 6.25µs to 14µs. After the SOD film was coated, the measured lifetime showed the lowest value ~4µs at specified MCD 10x 1013cm-3 with almost similar sheet resistance and resistivity value with RCA cleaned wafers. In all the three cases, the measured resistivity was in between 2.4 – 2.6 Ω-cm.

The output of carrier lifetime measurement under QSS are shown below

0 1000 2000 3000 400075

80

85

90

95

before anneal

Tran

smitt

ance

(%)

wave number (cm-1)

after anneal

3

Fig 12.2.2: Carrier lifetime measurement Fig 12.2.3: Carrier lifetime measurement just after RCA cleaning at specified just after SOD film coated at specified

MCD 1x 1015 cm-3 MCD 1x 1013cm-3

Fig 12.2.4: Carrier lifetime measurement just after drive-in at specified MCD 1x 1015cm-3.

Hence it is observed that dopant diffusion results in increasing carrier lifetime value as well as lowering of the sheet resistance value for sufficient SOD source coated on the surface.

12.2.2. 3D Junctions(Student: Som Mondal)

Theoretical: The temperature profile within the material under absorption of laser radiation has been studied at earlier stage. The temperature limit was set to be 1687 K as that is the melting point of silicon. But to realize the high diffusion coefficient of Boron or Phosphorous, the doping is expected to happen in the melt or sub-melt phase. Hence the model of the melting process of material and subsequent heating under absorption of laser radiation is being formulated. The system being under a phase change, modification of boundary condition and heat transfer equation is being studied. Experimental: In the earlier experiments, it was observed that the Voc values after laser doping become very non-uniform over the surface. As we look at the surface after laser doping, there are many places where material ablation is observed. On the other hand, the dopant layer, spin-coated over the sample, being highly hygroscopic absorbs lot of moisture

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during experiments in open ambient. Hence, it is being tried to create a highly doped layer on the substrate by thermal diffusion first and then do the laser doping. Thermal diffusion of P from spin-on source has been done at 1000 oC for 60 minutes and 30 minutes. The sheet resistance measured for these two cases are 3.4 – 3.6 ohm/sq. and 3.9 ohm/sq. respectively. The sheet resistance is quite uniform over the substrate. However the sheet resistances are almost similar in value. 12.2.3. Silicon concentrator solar cells(Students: Mehul Ravel, Vishnu Kant)

Though the quality of metal contact is very much process dependent (Ni & Cu- deposition process parameters), still it's important to locate the step in which the device gets vulnerable situation. The different steps of metallization process are: grid structure patterning -> ARC removal -> Electroless-Ni deposition -> Drying -> annealing -> Cu-electroplating -> drying. So, at present it is being tried to find the major cause responsible for poor adhesion of Ni-Cu front contact with c-Si solar cells. In experimental work, Cu electroplating is performed on a sample (apparently uniform ~360 nm thick nickel layer, deposited on a 100 n-type c-Si wafer with resistivity of 0.1- 0.6 Ω-cm). The copper layer was uniformly deposited and adhesion was good. But after drying the Cu-layer completely peeled-off from the sample. So it is observed that the adhesion between Ni & Si is good even without annealing but the adhesion between Ni & Cu is not much stronger. 12.2.4. Novel technology for contact formation using temperature sensitive paste(Students:

Akella Sastry, Mehul Ravel) Objective: Photovoltaic solar cell uses solar radiation and converts it into electricity. Even though the converting efficiencies are reached to 25% for a crystalline silicon solar cell, the commercially available cells are at 17%. Hence, there is a huge gap between the commercial scale production and laboratory scale production. Top surface of the solar cell is covered with anti reflective coating, SiXNY (ARC). The ARC is opened selectively to make the top contact of solar cell in grid pattern, generally by fingers and bus-bars. A contact formation technique where establishment of ohmic contact to n- type emitter and firing through ARC is required at front side. Commercially available solar cells are patterned using screen printing technique to make contacts at front side with silver containing metal paste. Screen printed solar cells have average finger widths 125-150 µm and fill factors 0.75, which are the limiting factors for optimum performance of solar cell. High finger widths leading to shading losses and less fill factors reduces the efficiency of the solar cell. In screen printed solar cells, emitter is heavily doped in order to achieve the good contact with silver, which leads to high resistive losses. Experimental: Removal of ARC can be done by chemical etching paste. The chemical etching paste (Merck’s Isishape) consists of H3P04 which is temperature sensitive. Etching paste is applied on a mechanical structure, developed by micromachining. Mechanical structure is designed in such a way that of a finger bus bar pattern. Paste containing structure is placed in contact with the top surface of solar cell (ARC side).

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Structure is incorporated with two electric heaters (each of 150W) and a temperature controller. Then, the solar cell is heated to 3900 C for about 90s and cleaned by ultrasonication bath.

Fig: Etched portion of a finger (≈160µm) The microscope observations of etched portion of finger- bus bar are shown in the above figure. Experiments are done with the mechanical structure with several fingers (7 no’s). Due to the poor machining of the structure, the thickness of the finger is not continuous and sharp enough throughout the individual finger. Hence, it will reflect in the solar cell etching. The etching observed with this structure is uneven. The thickness of each finger etched is about 150µm and discontinuous at some times. To avoid this, a new mechanical structure is suggested which have only two fine fingers. The structure is under machining work.

Fig 12.2.9: Mechanical structure with two fingers.

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12.2.5. Slicing of silicon wafers for PV applications using wire electric discharge machining (WEDM)

Introduction: Conventional methods used for silicon slicing that are inner diameter (ID) saws and wire saws. These methods create large mechanical contact forces while slicing the ingots that easily results in harmful surface micro-cracks or other damages to the wafer due to mechanical abrasive nature. However smaller wafer thickness is profitable because of the high material cost of monocrystalline silicon. This also makes the slicing process an important topic to be re-examined and re-investigated. The wire electrical discharge machining (WEDM) technology is adopted as a new candidate for silicon slicing to be compared with the existing procedures and testified if it can inevitably substitute for the ID saw or even compete with wire saws in some manufacturing orders. Thin and little geometrical error wafers are produced with this process. High contact resistance on the ingot surface is solved by nickel-plating. The surface roughness, cutting efficiency and micro-structures under different energy intensities are observed. However, the various parametric correlations and mechanism of cutting are not very well understood so far. Wire-EDM process: The scheme of the wire-EDM process is as shown in Fig. 1. In this process a thin single-strand metal wire, usually brass, is fed through the work piece which is either submerged in a tank of dielectric fluid or dielectric is supplied through nozzle.

Fig. 1 Schematic diagram of wire-EDM process

The wire is constantly fed from a spool and is held between upper and lower diamond guides. Due to the inherent properties of the process, wire-EDM can easily machine complex parts and precision components out of hard conductive materials. The phenomenon of erosion is same in wire-EDM process however; the tool electrode takes the form of a wire of generally Φ100 to 300 μm. Plan of work: Various activities planned as part of this project are illustrated in fig. 2. The project activities are going as per schedule:

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Fig. 2 Plan of work

Comprehensive review of existing and emerging techniques for dicing of silicon ingots, their capabilities and limitations: A comparative assessment of the existing and proposed methods of silicon dicing is presented in the Table 1. It is observed that existing process are having problems of higher kerf loss, subsurface damage and lower slicing rate. On the other hand, with the proposed method of wire-EDM for silicon slicing, it is possible to slice the thinnest wafers with a minimum kerf loss. In case of hybrid machining, slicing by EDM and anodic etching are combined together, which eliminates processing steps and can produce good quality wafers.

Table 1: Comparative assessment of existing and emerging methods in silicon slicing Process Features Existing Methods Proposed Methods

Diamond Wire-Saw

ID - Saw Wire-EDM Hybrid machining

Min. Wafer thickness (µm) 250 350 120 120 Kerf loss (%) 34 - 40 34 - 40 15 – 20 15 – 20 Surf roughness (µm Ra) 2 - 4 3 - 5 3 – 8 4.0 - 7.0 Time to slice 3” ingot (hr) 4.5 - 6.5 2.5 - 4.0 1.2 – 2 Issues Wire

breakage Large slices

Cleaning to remove wire

metal addition

Etch marks, immature process

Morphology

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Feasibility experiments and their analysis: Initial experimentation conducted at IIT Bombay, Machine Tool Lab, by using available micro wire-EDM setup (as shown in Fig. 3 below) for cutting silicon wafers to understand feasibility of the process, to measure the kerf loss and removal rates, and to observe the quality of cut surfaces as a function of process invariables voltage, capacitance wire feed rate, wire tension, polarity and dielectric fluid.

Fig. 3 Photograph of micro wire-EDM setup used for silicon cutting

This experimental analysis has shown that wire-EDM is promising process for silicon cutting. In this process, the materials removal rate increase with increasing capacitance. The dicing silicon produces minimum kerf loss of 27% if EDM oil is used as working fluid. However, if water is used as a working fluid, the kerf loss is more than 40%, see Figs. 4 a-b.

Fig. 4 a. MRR Vs Capacitance Fig. 4 b. Kerf loss Vs Working fluid

Experimentation to analyse the parametric effects in dicing of 3” square polycrystalline silicon ingot using metallic wire-EDM process: Screening experiments were conducted on conventional wire-EDM at Electronica Machine Tools, Pune. These experiments were successful in slicing 3” square polycrystalline silicon ingot with the slicing rate of 1mm/min, it means it will take 75 minutes to slice 3” silicon ingot. Fig. 5 shows the photograph of sliced wafer from silicon ingot.

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Fig. 5 Silicon wafers cut by wire-EDM process

Parametric evaluation of process parameters in silicon slicing by wire-EDM process: A CNC wire cut machine with distilled water as dielectric with submerged condition of cutting was used for conducting experiments. A 100mm diameter zinc coated brass wire as a tool electrode (cathode) and three inch square polycrystalline silicon ingot with resistivity 0.5 ohm-cm is used as a work piece. The scheme of cutting is shown in Fig. 6. Three inch silicon square polycrystalline silicon ingot is cut for a length of 5 mm with the thickness of wafer is 500 mm.

Table 2 Different control factors used with their level values

Variable Coding Level 1 2 3

Pulse on time (ms) Ton 1 1.5 2 Pulse off time (ms) Toff 26.2 41.2 69

Voltage (V) V 10 23 35 Water Pressure (Kg/cm2) WP 4 5 6

Fig.6 Scheme of cutting

The photograph shows 30 slots cut on 3” square silicon ingot at various levels of processing parameters as indicated in the table 2.

75 mm

75 mm

20 mm

Wire

Wafer

10

Fig. 7 Photograph of 30 slots cut on polycrystalline silicon ingot by wire-EDM

Analysis of cutting speed: Fig. 8 illustrates the contour plot of slicing speed vs. pulse on-time and pulse off-time. This graph indicates that for higher slicing speed, higher levels of pulse on time (2.5 ms) and lower levels of pulse off time (19.2 ms) must be used. If the pulse on-time and pulse-off time are away from the optimum values then excessive wire breakage or unsteady machining conditions will occur.

Fig. 8 Counter plot for slicing speed vs. Ton, Toff

Analysis of kerf loss: Counter plot for kerf area against pulse on-time and pulse off-time is shown in fig. 9. It is evident that in order to achieve smaller kerf area pulse on-time must be set at the minimum level that is at 0.5 ms, whereas the pulse off-time must be at maximum level that is at 104 ms.

Fig. 9 Counter plot for kerf area (mm2) vs. Ton, Toff

Slots cut by wire-EDM as per planned experiments

Slicing Speed

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Analysis of surface finish: To obtain lower roughness on a cut or machined surfaces of silicon wafer voltage and pulse on time must be at the lower levels (Fig. 10). It is known that at lower energy levels the size of crater generated will be less as compared to the higher energy level setting.

Fig. 10 Counter plot for surface roughness (‘Ra’ value in mm) vs Ton, SV

Concluding remarks: Based on the two sets of experiment one on silicon wafer cutting by micro wire-EDM and slicing of 3” square polycrystalline silicon ingot by wire-EDM process following observations are made

Slicing process of silicon ingot have been optimized to provide maximum of slicing speed at the same time minimizing the kerf loss and surface roughness of machined surface of silicon wafer.

In this experimentation minimum thickness of wafer achieved was 350 mm. The work has help to achieve the slicing rate of 1mm/min. At this rate slicing of one

3” square silicon wafer requires 75 minutes. This slicing rate 50 % less than the conventional methods of silicon ingot slicing.

Dimensional variation in the wafer thickness cut by wire-EDM process is about + 10 mm. This accuracy is 40-50% higher than the conventional silicon ingot slicing methods.

Plan for future work: Various activities of the project planned for future work are as follows: 1. Development of experimental setup for minimisation of wafer thickness: This work

involves development of experimental setup in order to accommodate various wire sizes preferably less than 100 µm in order to get minimum wafer thickness.

2. Detail study of process mechanics: Study of Voltage –Current characteristics, analysis of debris and effect of thermal spalling during cutting in order study process mechanism.

3. FEA based and Mathematical Modelling of silicon ingot slicing process: This work involves modelling of effect thermal spalling during slicing ingot slicing by wire-EDM

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process. Development of model for fracture mechanics of the process and validation of the same.

4. Advanced experiment in silicon ingot slicing: Analyse practicability for interfacing of ultrasonic vibrations, magnetic field application and hybrid machining capability in silicon ingot slicing process for better results.

5. Development of table top wire-EDM set up and detailed experimentation to understand the mechanism: Efforts are on with the Korean company Hybrid Precision, to develop dedicated wire-EDM machine which will have the facility of multi wire slicing. Detailed experimentations are planned which will be performed at Electronica Machine Tools, Pune in order to understand the process mechanism of slicing of silicon ingot by wire-EDM and obtain correlation between various process parameters and diced wafer quality.