12×12 Multiplier reduction (DSD)
-
Upload
engr-naveed-mazhar -
Category
Documents
-
view
50 -
download
3
description
Transcript of 12×12 Multiplier reduction (DSD)
![Page 1: 12×12 Multiplier reduction (DSD)](https://reader034.fdocuments.in/reader034/viewer/2022051413/552f1e094a7959485c8b4b18/html5/thumbnails/1.jpg)
ABBOTTABAD Assignment#02
Subject: Digital System Design
Submitted By: Naveed Mazhar FA09-BEE-143
Submitted To:
Sir Shahid Nawaz
Date: 31st October, 2012
![Page 2: 12×12 Multiplier reduction (DSD)](https://reader034.fdocuments.in/reader034/viewer/2022051413/552f1e094a7959485c8b4b18/html5/thumbnails/2.jpg)
1-Carry-Save Reduction The 12×12 Multiplier reduction using Carry-Save technique is shown step by step in
following figure:
![Page 3: 12×12 Multiplier reduction (DSD)](https://reader034.fdocuments.in/reader034/viewer/2022051413/552f1e094a7959485c8b4b18/html5/thumbnails/3.jpg)
Result: The Figure shows that
(I) No. of Full Adders = 109
(II) No. of Half Adders = 11
(III) Time Delay in reduction = 10 (F.A.)
![Page 4: 12×12 Multiplier reduction (DSD)](https://reader034.fdocuments.in/reader034/viewer/2022051413/552f1e094a7959485c8b4b18/html5/thumbnails/4.jpg)
2-Dual Carry-Save Reduction
Result: The Figure shows that
![Page 5: 12×12 Multiplier reduction (DSD)](https://reader034.fdocuments.in/reader034/viewer/2022051413/552f1e094a7959485c8b4b18/html5/thumbnails/5.jpg)
(I) No. of Full Adders = 104
(II) No. of Half Adders = 21
(III) Time Delay in reduction = 6 (F.A.)
3-Wallace Reduction Tree
Result: The Figure shows that
(I) No. of Full Adders = 102
(II) No. of Half Adders = 34
(III) Time Delay in reduction = 5 (F.A.)