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Abstract—The supervisor system based on MC68040/60

microprocessor is used to service the laboratory stand with TMS32C5402 signal processor. Memory address space sharing technique is utilized in order to achieve mutual communication. The laboratory stand uses VME standard and its own defined local bus for specific input/output card.

Index Terms—VME standard, signal processor card, memory sharing technique

I. INTRODUCTION he modern market of signal processors (sμp) has been dominated by solutions delivered by companies such as:

Texas Instruments (TI), Analog Devices (AD), and Freescale Semiconductor (FS) – previously Motorola. These companies, except from Motorola produce a wide range of fixed as well as floating point processors. Motorola’s successful M9600X floating point family disappeared from the mass production excluding substantive and economic reasons. There are development trends like: expansion of cache memory capacity (code-data, two-levels), constructions with double MAC (TMSC55X5), separated multiprocessor (ADSP2106X), multicore (TMSC647X and ’C66X; ADSP-BF5XX; MSC8XXX) and also tandem: the microcontroller with sμp components (ADUC 8XXX; ‘C7XXX; MC/DSP 56F8XX). In this last case, producers rely on their own microcontrollers and also on constructions based on the ARM7 architecture. Students, who study Electronics and Telecommunication at the Faculty of Computer Science, Electronics and Telecommunication have an optional subject of signal processors. Before the students begin get to know advanced systems in the form of so-called kits, connected with the computers, they are introduced into specific construction of sμp produced by TI, AD and FS. These basic processors are: TMS32C5402, ADSP2161 and MC56311 [1],[2],[3]. The laboratory stands,

Manuscript received November 12, 2012. B. J. Wi niewski, Department of Electronics, AGH University of

Science and Technology , al. Mickiewicza 30, 30-059 Krakow, Poland (corresponding author phone: 0048 609 192 139; fax: 0048 12 633 23 98 ; e-mail: bwisniew@agh.edu.pl).

B. E. Szecówka-Wi niewska, Department of Electronics, AGH University of Science and Technology, al. Mickiewicza 30, 30-059 Krakow, Poland (e-mail: bawisnie@agh.edu.pl).

J. A. Ostrowski, Department of Electronics, AGH University of Science and Technology, al. Mickiewicza 30, 30-059 Krakow, Poland (e-mail: ostrowsk@agh.edu.pl).

with regard to illustrative effects are not “closed-construction”, but “open-construction” in module form, with the dedicated bus.

II. LABORATORY STAND All the laboratory stands with signal processors were mutually standardized. As the base, the VME bus was used. This assumption comes from the fact, that all 32-bits microprocessor systems in this laboratory use this standard. In this case, a central bus arbiter is required and at least one card has to behave as MASTER. With regard to usage this stand for development and didactic purposes TMS32C5402 will operate in „microprocessor” mode – using external code and data memories. Activated application’s program could be transfer from master through HOST port. Transfered program comes to internal memory. In this case, it is impossible to observe of the bus cycle by cycle application’s operation (using !READY line logic - !means negation). This mode is irreplaceable during hardware activation and it allows to better understanding of system operation. It is necessary to provide direct access to external code and data space with omitting TMS32C5402 circuit. Taking over control by s p screen/keyboard service and for example self-assembling is however unprofitable. So it was decided that one of the microprocessor laboratory system take over application with TMS32C5402 circuit service. These systems cooperate with keyboard/screen interfaces and they are equipped with resident software (editor-assembler, disassembler, monitor-debugger). This system would prepare binary form of application program for TMS32C5402. Supervisor system should mutually share out its own memory space with TMS32C5402 circuit – program and data s p memories will be a part of address space of VME bus [4]. This standard is not able to predict lines for all individual interfaces. It has however numerous group of lines in order to define them by user. Every sμp has other internal lines. That is why only two serial ports and simple synchronic bus (addresses LA5-0, !LCS, !LRD, !LWR, !INTA, !INTB, LD15 - 0) has been defined. Cards cooperating with this bus will be mapped in data space of sμp. Above-cited idea is shown in the Fig. 1

Signal processor as a master of local bus and as a slave of global bus (VME standard) Bogus aw J. Wi niewski, Barbara E. Szecówka – Wi niewska, Jacek A. Ostrowski

T

2012

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In order to operation of s p interfaces also in other configurations (without sμp), the card which realize

mapping local bus space into the VME bus memory space has been constructed. Supervisor system is based on M68040/60 processor [6]. It has their own interfaces and resident software. It can also effectively ensure edition and assembling for TMS32C5402 circuit. Supervisor system should also have possibility instruction step by step work for application with sμp, with simultaneous viewing its contents and resources. Complete laboratory stand is shown in the Fig. 2. TMS32C5402 circuit has also testing port JTAG with basic functions set. There is a possibility of viewing sμp signals, after adding standard console of JTAG port. The solution, which is applied in laboratory has unified hardware and

successively added software for the next μp, equipped with JTAG port [5].

III. COOPERATION BETWEEN SYSTEMS Supervisor system has to take over a number of functions in relation to the application with sμp:

- edition of source file and check of syntax, - assembling with syntax detection, - loading binary code form into code memory space

of sμp, - software step by step work of sμp application, with

viewing registers and data memory of sμp. First two functions are internal problem of the system with μp M68040/60. The other functions base on mutually sharing out memory spaces. Detailed using of both superposed spaces is shown in Fig. 3. Some spaces are related to special activities. So there are:

- reset of sμp, - interrupt request to sμp (emergency stop of

application), - returnable interrupt to supervisor system.

Supervisor system, after code loading to common space, places there also procedure of INT0 interrupt service (the highest priority). The interrupt is used to software step by step work. INT0 interrupt service transfers registers states to supervisor system through the isolated space in data memory. Next it reads status word situated in the data memory. When supervisor system changes this status, sμp receives registers state and executes the next instruction of tested program. Because supervisor system sets earlier INT0 interrupt, all this procedure repeats again. In case of necessity of setting the software trap(s), supervisor system places the software interrupt instruction

Fig. 1. Organization of address space

Fig. 2. Laboratory stand with signal processor

Fig. 3. Organization of shared address space

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(SINT) at the given address instead of original instruction. The supervisor system has already loaded procedure of software interrupt (SINT) during the initialization handler. When the s p goes to SINT instruction service, it writes any values into its own data space (FF80 FFBF). As an effect, supervisor system receives the IRQ5 interrupt. Signal processor waits for supervisor system reaction (INT0 interrupt). Further actions will be determined by the bits of status location in the data memory. For viewing purposes, the possibility of emulation HOST port signals, through locations in address space has been predicted. The detailed description of such solutions is not in the frame of this article.

IV. CHOSEN HARDWARE IMPLEMENTATIONS Normally, the access to the memory from the both system side should be assured by two-port memory. Difficult to solve problems, which can lead to software cycle repetition may occur during the superposition of addresses. In order to avoid such situations, the safe method using !HOLD/!HOLDA lines of signal processor is applied. When the supervisor system addresses the common area, then s p receives bus request !HOLD signal. Until there is no answer on the !HOLDA line, supervisor system adds wait states into the cycle. Next, the finite state machine on the s ps card realizes the transfer. Only after finishing the transfer, the supervisor system receives acknowledge on the !DTACK line and transfer cycle can be finished. Block diagram is shown in the fig. 4. After reading from supervisor system, it is necessary to save the word, which is read from memory. Buffering is necessary only from the supervisor system. We take advantage of the fact that after setting !HOLDA signal, s p goes into high impedance state on its lines. Detailed timing, which illustrates the operation of finite state machine is shown in the fig. 5. The “safe” timings without finite state machine compression is assured. This ensures dependable transfer. Speed during the step by step work/trap is not an essential parameter.

V. CONCLUSIONS

The constructed stand has been checked during the creation of application and laboratory classes. The view of the complete TMS32C5402 card is shown in Fig. 6. Processor M68040/60 has turned out to be very effective during the process of creating editor/assembler and cooperate procedures. Therefore in the similar way, the development

systems for signal processors such as: Analog Devices and Motorola/Freescale Semiconductor was implemented. In the

case of s p, currently introduced into production, we can already use effective tools, connected with tests ports. It will be possible to build independent development system with embedded editor/assemble/debugger software.

Fig. 5. Timing for finite state machine

Fig. 6. View of the complete TMS32C5402 card.

Fig. 4. Block diagram of shared memory.

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REFERENCES [1] Company website: http://www.ti.com [2] Company website: http://www.freescale.com [3] Company website: http://www.analog.com [4] http://www.vita.com, VME Standard, 10.04.1995 [5] B. J. Wi niewski, B. E. Szecówka-Wi niewska, J. A. Ostrowski,

“Using the JTAG test port in the microprocessor system Lab”, PWT 2008, XIII Pozna skie Warsztaty Telekomunikacyjne, Pozna 11 grudnia 2008.

[6] B. J. Wi niewski, „ rodki uruchomieniowe w laboratorium dydaktycznym Techniki Mikroprocesorowej”, Elektronika : konstrukcje, technologie, zastosowania, vol. 50, no.10, pp. 42-45, Oct. 2009.