11/16/2004 EE 42 fall 2004 lecture 33 1

Lecture #33: Some example circuits

• Last lecture:– Edge triggers– Registers

• This lecture:– Example circuits– shift registers– Counters– adders

11/16/2004 EE 42 fall 2004 lecture 33 2

Examples of useful combinatorial circuits

• There are several patterns of combinatorial logic which appear fairly often, here are several examples

• The examples will be given in terms of gates as well as logic equations, but not in a minimal representation, but just a clear example

• In most cases, a computer program such as Verilog would be responsible for producing optimal implementations anyway.

11/16/2004 EE 42 fall 2004 lecture 33 3

Pattern recognizer

The output of this pattern recognition circuit is 1 only if the input is 10110, and otherwise zero

A

B

C

D

E

)( EDCBAQ

Q

11/16/2004 EE 42 fall 2004 lecture 33 4

Decoder•n inputs, 2n outputs

–one output is 1 for each possible input pattern, all other outputs are 0

A B O1 O2 O3 O4

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

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Decoder•n inputs, 2n outputs

–one output is 1 for each possible input pattern, all other outputs are 0

A

B

1

2

3

4

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CMOS switch

• A CMOS switch will allow a logic level to pass if activated, does not allow current through the gate if not activated

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Multiplexer (MUX)

•n-bit selector and 2n inputs, one output–output equals one of the inputs, depending on

selector

I1

I2

I3

I4

2 input decoderA

B

O

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Buffer• A buffer passes a logic level while increasing its drive

capability• A design like the previous slide would likely be

implemented with a buffer at its output

Often, wider transistors in the second stage

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Half Adder

• A half adder takes two bits and produces their sum, with a carry

• It is called a half adder because it does not have a carry input

A

BSum Output

Carry out

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Half adder

A B O C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

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Full Adder

•Add two bits and carry-in,produce one-bit sum

and carry-out.

A B Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

11/16/2004 EE 42 fall 2004 lecture 33 12

One bit Full adder• A single bit full adder can be made from

two half adders and an or gate

Half adder

A

B

O

C

Half adderSum out

C

Carry out

Carry in

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Full adder as a logic block• We can use our full adder as a logic block

to make a multi-bit adder by cascading the carry line

Full adder(one bit)

Cin

A B

Cout

Sum

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Three-bit Adder

half adder(one bit)

A0 B0

Sum0

Carry Full adder(one bit)

A1 B1

Sum1

Carry Full adder(one bit)

A2 B2

Sum2

Carry

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Adders

• It is interesting to note that in hardware, it is typical to dedicate an adder for one particular use, as contrasted with software on a CPU, where numbers are moved around to be added by a central adder.

• This is because the additional selectors and wires to move around numbers takes more area than just putting in separate adders for each purpose.

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Some register based digital blocks

• There are also several common digital blocks which are based around flip-flop registers, such as multi-bit data registers, shift registers, and counters

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Definition:Register•A register is a collection of flip-flops with similar controls and logic

•A register stores a multi-bit value.–Stored values somehow related (e.g., form binary

value)–Share clock, reset, and set lines–Similar logic at each stage

11/16/2004 EE 42 fall 2004 lecture 33 18

R S R S R S

D Q D Q D Q D Q

OUT1 OUT2 OUT3 OUT4

Write enable

IN1 IN2 IN3 IN4

R S

Reset“0”

Registers• Example: a collection of D-flip-flops, all controlled by a

common write enable (WE).– When WE transitions from 1 to zero (falling edge), a n-bit value

D is written to register.

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D Q D Q D Q D QIN OUT

shift

Shift Register

• Holds samples of past input values and shifts them in sequence into a string of flip-flops

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D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

Shift Register

• Holds samples of input– Store input values in sequence– 4-bit shift register used as a serial to parallel

converter:

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R S R S R S

D Q D Q D Q D Q

Shift

IN1

R S

Reset“0”

Parallel to serial converter

MUX“0” literal

IN2MUX MUX MUX

IN3 IN4

Load/Shift

Output

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parallel inputs

parallel outputs

serial transmission

Shift Register Application

• Parallel-to-serial conversion for serial transmission

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D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

OUT

Pattern Recognizer

• Combinational function of input samples– In this case, recognizing the pattern 1001 on

the single input signal

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Use of counters

• Counters are often used when something needs to happen a certain number of times.

• Counters can be designed to be preset to particular values, to count up or down, and/or to trigger some action at a particular count by the use of a pattern recognizer.

11/16/2004 EE 42 fall 2004 lecture 33 25

D Q D Q D Q D Q

OUT1 OUT2 OUT3 OUT4

CLK

"1"

Binary Counter

• Logic between registers (not just multiplexer)– XOR decides when bit should be toggled– Always for low-order bit, only when first bit is true for

second bit, and so on

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Sequential Logic Summary

• Fundamental building block of circuits with state– R-S latch, R-S master/slave, D master/slave, edge-triggered D FF

– Latch and flip-flop

• Timing methodologies– Use of clocks

– Cascaded FFs work because prop delays exceed hold times

– Beware of clock skew

• Asynchronous inputs and their dangers– Synchronizer failure: what it is and how to minimize its impact

• Basic registers– Shift registers

– Pattern detectors

– Counters