1.1) Definition of Boolean Algebra - Tel Aviv Universitymatias/Classes/Computer...

Chapter 1: Boolean Algebra ( © copyright by Daniel Seidner) 1

1.1) Definition of Boolean Algebra The Boolean algebra is named after George Bool who developed this algebra (1854) in order to analyze logical problems. An example to such problem is: Prove that if not fat and not triangle necessarily means not green then green must be fat or triangle (or both). We use the formal definition of the Boolean algebra as given by E. V. Huntington in 1904: Boolean algebra is an algebraic structure defined on a set B of variables along with two binary operators + and · so that the six Huntington rules shown below are satisfied. Before we give these six rules, we define the terms binary operator and a closed set: � A binary operator is defined on a set B and is a rule assigning a single member of B to any

pair of B. � A closed set in relation to a binary operator: If applying the operator on any pair of members

belonging to B results with a member of B, the set B is close set in relation to that operator. Huntington rules; I) The set B is closed in relation to the operators + and · . II) A unitary member for + is denoted by 0 and satisfies: XX =+ 0

A unitary member for · is denoted by 1 and satisfies: XX ÷�1 III) The operators + and · are commutative, i.e.,

XYYX ƒ÷ƒ and XYYX �÷� IV) The operators + and · are distributive, i.e.,

)()()( ZXYXZYX �ƒ�÷ƒ� and )()()( ZXYXZYX ƒ�ƒ÷�ƒ

V) Any member X of B has a complement X so that 1=+ XX and 0=⋅ XX

VI) The set B has at least two members We deal with Bi-level or Binary Boolean algebra in which the set B contains only two possible values, 0 and 1, i.e., }1,0{÷B . We call the operator + the logical OR operator and the operator ·, the logical AND operator. The logical OR operation has 4 possible combinations:

000 ÷ƒ 110 =+ 101 =+ 111 =+


Note that the result is 1 if the first operand OR the second (or both) are 1. This is the reason for naming this operator the OR operator. The logical AND operation has also 4 possible combinations:

000 =⋅ 010 =⋅ 001 =⋅

111 =⋅ Note that the result is 1 only if the first operand AND the second one are 1. This is the reason for naming this operator the AND operator. The complement operation is called NOT and is marked by a bar over the variable. Here we have only two possible cases:

10 = 01=

Let us verify that Huntington rules are satisfied: I) We see that any combination of OR and AND results with a member of B . II) The 2nd rule is satisfied since:

000 =+ and 101 =+ so, for any possible value of X we have XX =+ 0 similarly, 010 =⋅ and 111 =⋅ , so for any value of X we have XX =⋅1

III) We see that the operators + and · are commutative. IV) We can easily see that if 0=X , then both sides of the equation

)()()( ZXYXZYX �+�=+� are 0. If 1=X , the left hand side of the equation is 1 if Y or Z are 1, but so is the right hand side of that equation. Similarly, we can show this also for the equation )()()( ZXYXZYX +�+=�+ .

V) Is straight forward according the definition of the NOT operation VI) Is straight forward. We can now describe the example given above using the language of Boolean algebra. A is 1 if “fat” and 0 if “not fat”. B is 1 if “triangle” and 0 if “not triangle”. These two notions of “fat” and “triangle” just describe some property of something, that may or may not exist. If we denote the property “green” by C , we can define the problem as follows: Prove that if CBA �� then BAC +⇒ Or even: if α+⋅= BAC then 1=C means 1=+ BA .


1.2) Venn diagrams We may use Venn diagrams to visually describe the logical relations of such equations. The rectangle stands for all possible cases (e.g., “fat and triangle”, “green” and “not triangle” etc.). The circle represents all cases in which 1=A , i.e., in which that something we discuss is “fat”. The shaded area therefore, represents all cases in which 1=A , i.e., 0=A . In Figure2, the left hand side circle represents A , while the right hand side circle represents B , i.e., all cases in which 1=B , which means that the something we discuss is “fat”. The cases included in the expression BA + are represented by the union of the circles representing A and B . The intersection of the two circles represents BA ⋅ . The shaded area, is therefore all cases in which are A and at the same time also B , i.e., BA ⋅ .

Figure 1.1-Venn diagram of a single variable

A

A

Figure 1.2- Venn diagram of two variables

A

A·B

B

A·B


Since if CBA ⇒⋅ (or α+⋅= BAC ), C must include BA ⋅ , i.e., C is even larger than the shaded area in figure 2. In Figure 3, we see that C is therefore smaller than BA + . This means that in case C is 1, we must also have BA +=1 which is exactly what we wanted to prove. By the way, the area included in BA + but without C represents α . So we see that Venn diagrams can be helpful when we try to visually solve, or understand, logical problems.

Figure 1.3- Explanation of the example

A

A·B

B

C


1.3) Basic Identities Another way to solve or simplify logical equations, is to use some basic “laws” or “identities”. The following table, describe 10 basic laws that are useful in manipulation of Boolean equations.

1 XX =+ 0 (Identity law)

XX =⋅1

2 1=+ XX (inverse law)

0=⋅ XX

3 11=+X (one law)

00 =⋅X (zero law)

4 XXX =+

XXX =⋅

5 XX =)(

6 XYYX +=+ (Commutative law)

XYYX ⋅=⋅

7 )()( ZYXZYX ++=++ (Associative law)

)()( ZYXZYX ⋅⋅=⋅⋅

8 )()()( ZXYXZYX +⋅+=⋅+ (Distributive law)

)()()( ZXYXZYX ⋅+⋅=+⋅

9 YXYX ⋅=+ (DeMorgan’s law)

YXYX +=⋅

10 XYXX =⋅+ XYXX =+⋅ )(

The left-hand side of the table describes the identities related to the OR operation, while the right hand side has the “dual” identities related to the AND operation. The “duality” means that in order to find the dual identity, one should change all ORs to ANDs and vice versa and also change 0s to 1s and vice versa. Furthermore, we will see that proving any of the identities in the table can be used for proving the dual identity (replacing + with · and vice versa and 0s and 1s and vice versa and using dual rules when needed). Identities 1,2,5,6 and 8 follow Huntington rules. Let us prove identity 4 (for OR) using those identities


XXXXXXXXXXXXX =+=⋅+=+⋅+=⋅+=+ 0)()()(1)( We first used identity 1 (for AND), then identity 2 (for OR), then the distributive law (identity 8) followed by identity 2 (for AND) and finally identity 1(for OR). In order to prove the dual identity, i.e., identity 4 for AND, we use the dual identities in the same order (i.e., replacing + with · and vice versa and 0s and 1s and vice versa and using dual rules when needed):

XXXXXXXXXXXXX =⋅=+⋅=⋅+⋅=+⋅=⋅ 1)()()(0)( The proof of identity 3 (for OR) is:

1)1()1()()1(11 =+=⋅+=+⋅+=+⋅=+ XXXXXXXXX The proof of identity 10 (for OR) is:

XXYXYXYXXYXX =⋅=+⋅=+⋅=⋅+⋅=⋅+ 1)1()1(1 Let us now return to the example we had earlier: Prove: if α+⋅= BAC then 1=C means 1=+ BA .

Using DeMorgan’s law we have ααα ⋅+=⋅⋅=+⋅== )()()( BABABACC . We therefore see that if 1=C , we must have 1=+ BA since otherwise, the right hand side of the equation will be 0. 1.4) The Truth table A truth table is a table describing all the combinations of the possible values of the variables in a Boolean function. The truth table below describes all possible values of the variables of the function F where YXXYXfF ⋅+== ),( :

X Y YXXF ⋅+=

0 0 0000 ⋅+=

0 1 1000 ⋅+=

1 0 0111 ⋅+=

1 1 1111 ⋅+=


One can easily see that the right hand column describing the value of F for all possible combinations of the values of X and Y , is exactly the same as the left hand side column describing the variable X . This means that X equals YXX ⋅+ . This is another way to prove that identity 10 is true. Using truth table we can easily prove DeMorgan’s laws:

X Y YX + YX ⋅ YX ⋅ YX +

0 0 001 += 001 ⋅= 001 ⋅= 001 +=

0 1 100 += 100 ⋅= 101 ⋅= 101 +=

1 0 010 += 010 ⋅= 011 ⋅= 011 +=

1 1 110 += 110 ⋅= 110 ⋅= 110 +=

1.5) The order of operations As in regular math, we have a similar order of performing the logical operations. First evaluate the expressions in parenthesis. In evaluating an expression, first perform the NOTs then the ANDs and then the ORs. When we have a NOT of an expression, we first evaluate the expression and then perform the NOT, i.e., as if we had parenthesis under the bar.

For BCACBAF ⋅+⋅+⋅= )( where 1=A , 1=B and 0=C , we first calculate

0)00()0()1()11()( =+=+=+=+⋅=+⋅ CCCCBA . Then we calculate

1001 ==⋅=⋅=⋅ CCBC . Then we calculate

11011010)( =+=+⋅=+⋅=⋅+⋅+⋅= ABCACBAF . 1.6) The XOR operation We define the Exclusive OR (XOR) operation as BABAY ⋅+⋅= , and denote it by

BAY ⊕= . This means that 1=Y if BA ≠ . What is the definition of XOR of n variables? If an odd number of them are 1s, the XOR is …


1.7) Canonic representation of Boolean functions Let us describe the two Canonic representations of a Boolean function of three variables

),,( CBAfY = given by the following truth table:

A B C Y

0 0 0 1

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 0

1 1 1 0

The 3 equations below also describe the same function:

CBACBACBACBAY ⋅⋅+⋅⋅+⋅⋅+⋅⋅=

CBACBBAY ⋅⋅+⋅+⋅=

)()()()( CBACBACBACBAY ++⋅++⋅++⋅++= It is easy to see that each of the terms in the first equation matches one of the combinations of the variables that produce 1 in Y . One can also see that the 2nd equation is some simplification of the first one (which was simplified using some of the basic identities). The first two equations have the form of Sum Of Products (SOP). The third equation has the form of Products Of Sums (POS). Note that all the terms in the first equations are products of all the variables of

),,( CBAf . Products that include all of the variables of a function are call Standard Products or Minterms. The Canonic SOP representation of a function is a SOP in which all products are standard products. Therefore, the first equation is a Canonic representation of Y , while the 2nd is just a regular SOP representation.


One can use the laws (basic identities) to convert a SOP to the canonic SOP: The function BACBAfF ⋅== ),,( can be converted to its canonic representation by ANDing each term with the “missing” variable OR its complement and the Distributive law:

CBACBACCBABAF ⋅⋅+⋅⋅=+⋅⋅=⋅= )( . An easier way is to look at the truth table and write down the terms that should be 1 in F . In the truth table above, the function ),,( CBAfY = should be 1 for the combination

)1,0,1(),,( =CBA therefore the canonic SOP must include the term CBA ⋅⋅ which is 1 iff

)1,0,1(),,( =CBA . [This is the definition of AND: CBA ⋅⋅ is 1 only if 1=A and 1=B , i.e., 0=B , and 1=C ].

A sum that includes all of the variables of a function is called a Standard Sum or a Maxterm. The Canonic POS representation of a function, is a POS in which all sums are standard sums. Therefore the third equation is the Canonic POS of the function ),,( CBAfY = . We can find the POS canonic representation of an equation by ORing each term with the “missing” variable AND its complement and the Distributive law:

)()()( CBACBACCBABAF ++⋅++=⋅++=+= Again, an easier way is to look at the truth table and write down the terms that should be 0 in F . In the truth table above, the function ),,( CBAfY = should be 0 for the combination

)1,0,0(),,( =CBA therefore the canonic POS must include the term CBA ++ which is 0 iff

)1,0,0(),,( =CBA . [This is the definition of OR: CBA ++ is 0 only if 0=A and 0=B ,

and 0=C , i.e., 1=C . One May also use DeMorgan’s law to see that CBACBA ⋅⋅=++ , i.e., if and only if )1,0,0(),,( =CBA , we have 1=⋅⋅ CBA and therefore 0=++ CBA ]. Let us look again at the two canonic equations representing the same function Y given in the previous page:

CBACBACBACBAY ⋅⋅+⋅⋅+⋅⋅+⋅⋅=

)()()()( CBACBACBACBAY ++⋅++⋅++⋅++= Suppose we know that the right hand side term of the SOP equation is 1, what is the value of the left-hand side term of the SOP equation? What is the value of the left-hand side term of the POS equation? The left hand side term of the SOP must be 0 since if the term on the right hand side is 1, it means that the combination “identified” by this term is true. Therefore, any other combination, such as the one which should be identified by the left-hand side term cannot be true. Remember, each term “identifies” a distinct combination of the variables.


The left-hand side term of the POS equation must be 1. This is so since we know for sure that 1=Y , and so, all terms of the POS equation must be 1, otherwise we will have 0=Y .

Similarly, suppose we know that the right hand side term of the POS equation is 0, what is the value of the left-hand side term of the POS equation? What is the value of the left-hand side term of the SOP equation? The left-hand side term of the POS equation must be 1 since again, each term “identifies” a distinct combination, and a certain combination has already been “identified” by the right hand side term. The difference between SOP and POS is that in SOP, a term that “identifies” a combination of the variables becomes 1, while in POS, a term identifying a combination becomes 0. The value of the left hand side term of the SOP equation must be 0 since we know that 0=Y which means that all terms in the SOP must be 0. For any combination of the variables only one of the 23 terms of the two canonic equations will “identify” the combination. 1.8 Gates The basic building blocks which are used to implement a logic function are called gates. Any equation can be considered as a system having inputs (the variables) and outputs (the result of applying the functions on the variables). The equation ),,( CBAfY = describes a system having 3 inputs CBA ,, and a single output Y . 1.8.1 An AND gate Its equation is BAY ⋅= . We draw it as in Figure 1.4. Its truth table is given below and is identical to the AND operation.

A B Y

0 0 0 0 1 0 1 0 0 1 1 1

Figure 1.4 – An AND gate


1.8.2 An OR gate Its equation is BAY += . We draw it as in Figure 1.5. Its truth table is given below and is identical to the OR operation.

A B Y

0 0 0 0 1 1 1 0 1 1 1 1

1.8.3 A NOT gate (usually called an INVERTER) Its equation is AY = . We draw it as in Figure 1.6. Its truth table is given below and is identical to the NOT operation.

A Y

0 1 1 0

1.8.4 A NAND gate Its equation is BAY ⋅= . We draw it as in Figure 1.7. Its truth table is given below.

A B Y

0 0 1 0 1 1 1 0 1 1 1 0

Figure 1.6 – An Inverter (a NOT gate)

Figure 1.5 –An OR gate

Figure 1.7– A NAND gate


1.8.5 A NOR gate Its equation is BAY += . We draw it as in Figure 1.8. Its truth table is given below.

A B Y

0 0 1 0 1 0 1 0 0 1 1 0

1.8.6 A XOR gate Its equation is BABABAY ⊕=⋅+⋅= . We draw it as in Figure 1.9. Its truth table is given below.

A B Y

0 0 0 0 1 1 1 0 1 1 1 0

Figure 1.10 is a simple example of implementing a Boolean function using gates. We here build a XOR gate, using AND, OR and NOT gates:

Figure 1.8 – A NOR gate

Figure 1.9 – A XOR gate

Figure 1.10– Building a XOR gate using AND, OR & NOT gates

A

B

A

B

=


1.9 A Universal system Note that since the only operators we defined in Boolean algebra are the AND, OR and NOT operators, it is clear that having these three kind of gates in our hands, enables us to build any desired function. Therefore, we call the set of AND, OR and NOT gates, a universal system. A NAND gate is itself a universal system and so it is called a Universal Gate. In order to show that we can build any desired function using only NAND gates, we will show that we can implement all of the 3 operators AND, OR and NOT using only NAND gates. Let us start with the NOT operation. We want to implement AY = using a NAND gate whose function is

BAY ⋅= . If we choose B to be 1 or connect the input A to the other input, we create an inverter since AAY =⋅= 1 and also AAAY =⋅= : Since a NAND gate is just an AND gate which is followed by an inverter, all we need in order to convert it “back” to a regular AND gate, is to add one more inverter: Building the OR is a little bit more difficult. We need to use DeMorgan’s laws:

BABABAY ⋅=+=+= . Now, it is easy to implement the OR using 3 NAND gates, two as inverters and the third one to perform the NAND operation on the first two’s outputs.

Figure 1.11 – An inverter made of a NAND gate

A

1

Y or A Y

Figure 1.12 – An AND gate made of NAND gates

B Y A

Figure 1.13 – An OR gate made out of NAND gates

B

Y

A


Let us now try to implement a XOR gate using only NAND gates. The easiest way is to replace any inverter in Figure 1.10 with the inverter of Figure 1.11, and any AND gate with the AND gate of Figure 1.12, and finally, the OR gate with the OR of Figure 1.13: We can reduce the gate count, if we delete the two redundant pairs of inverters. Those are

redundant since XX =)( . Eventually we end with:

Figure 1.15 – A XOR gate made of NAND gates

Y

A

B

Figure 1.14 – Building a XOR gate using only NAND gates

A

B

Y

A

B

=

or

not

and


1.10 Timing issues of gates Let us first define some terms. A signal is a continuous function of the time t. A logic level “0” is a predefined voltage range that is recognized by a gate as a “0” level. In the well-known TTL 74xx logic family, a “0” level was defined as 0.0v to 0.2v. A logic level “1” is another predefined voltage range that is recognized by a gate as a “1” level. In the 74xx logic family, a “1” level was defined as 2.0v to 5.0v. The signal has a logic level when the value of the signal in the range of logic level “0” or in the range of logic level “1”. A signal is called stable at a time interval if it stays in the same logic level along the entire time interval. Let us explore the behavior of a simple gate. We input the signal A(t) to an inverter and receive the signal Y(t) at the inverter’s output.

The input signal A(t) starts at “1” so Y(t) is “0”. At a certain point at time, i.e., at t0, we change the input signal to be “0”. The gate does not respond immediately. Its response is depicted in Figure 1.17 below. We see that it takes some time till the output signal changes. The time period in which the output signal still stays in the initial logic level, i.e., the time in which the gate “does not response” to the input change, is called the contamination delay and is denoted by tcd. The time required for the output to reach its “final”, i.e., stable level, is called the propagation delay and is denoted by tpd. These two time intervals are described in Figure 1.17 below for the rising and falling of the signals A(t) and Y(t) where A(t) is changing at t0 and t1. When we implement a logical function using gates, we must consider the timing. When we want to know how soon will the output of a logical system be valid, i.e., in its stable logical level, we need to consider the worst case of all the gates. If this is a combinational system, we should take into account the sum of the delays of the maximum path between the input and the output signals. So, for our purposes, we can draw the signals as having valid logical values after the maximal tpd of the gates involved.

Figure 1.16 – Naming the signals of a NOT gate

A(t) Y(t)


In Figure 1.17, we see the input signal A(t) at the top. The response of an ideal gate, i.e., without any delay, is described as Yideal(t). The actual signal Y(t) at the output appears 2nd from the bottom. For our analysis of digital circuits we can use the “digital levels” picture shown at the bottom of Figure 1.17. 1.11 Multiple inputs gates Now we know that gates have delays. We should take that into account when we build systems that are more complex then a single gate. In computer science, the analysis of an algorithm usually deals with its complexity or performance, expressed as the number of operations required,

Figure 1.17 – The timing behavior of a NOT gate

t = 0 t

A(t)

“0”

“1”

0

t

Yideal(t)

“0”

“1”

0

t

The actual Y(t)

tcd tcd

tpd tpd

Logic level “1”

Logic level “0”

V0

V1

0

t

Y(t) in “digital levels”

tpd tpd

“0”

“1”

t0 t1

t0 t1


and its cost in the memory units required. In analysis of hardware systems, we have similar measures. The performance is measured by the maximum delay of the system and the cost by the number of required gates. Let us now build an n inputs AND gate using two inputs AND gates only. The simplest way is based on induction. When we want to build a three input AND gate using two inputs AND gate we’ll use the rules saying that CBACBAY ⋅⋅=⋅⋅= )( , i.e., we’ll use one gate to produce

BA ⋅ and another gate to AND the result with C . Using induction, we can quite easily build an n inputs AND gate, adding a single input at a time. This is depicted in Figure 1.18:

We will define such a structure “recursively” by describing an n inputs gate built of an (n-1) input gate and a simple 2 inputs gate: In this simple way, the cost of an n inputs AND gate is C(n)=n-1, i.e., we need n-1 gates, 2 input AND gates, in order to build an n inputs AND gate. The delay is given by D(n)=(n-1)T where T is the delay of a single 2 inputs AND gate. The reason for this dependency of the delay on the number of inputs is the chaining of the gates. Because of this structure, a change in the I0 should “propagate” through n-1 gated until it “reaches”, i.e., influences, the output Y. This seems a little exaggerated. There must be a better way. That way is to use binary tree structure. The depth of that tree will determine the maximal delay. This can be seen in Figure 1.20 below.

Figure 1.18 – Building an n inputs AND gate using 2 inputs AND gates

I0 I1 I2

In-2 In-1

Y

Figure 1.19 – Building an n inputs AND recursively

In-1 Y

I0 I1

In-2


Figure 1.20 – Building an n inputs AND gate using a tree of inputs AND gates

Y

I0 I1

I2 I3

In-4 In-3

In-2 In-1

I4 I5

I6 I7

In/2-1


We can define such a structure “recursively” by describing an n inputs gate built of two n/2 input gates: The cost of such an n inputs gate stays C(n)=n-1. This is so since it really does not matter how we add the inputs, since every new input forces us to add a single gate. It is quite clear from Figure 1.19 that the delay follows the recursive equations TnDnD += )2/()( . This immediately means that the delay is logarithmic, i.e., nTnD 2lg)( ⋅= . This is so since we can write:

TTTnDTTnDTnDnD +++=++=+= )8/()4/()2/()( , etc., so we see that we have to sum n2lg times the delay T. When n is not an exact power of 2, there are several optional trees, all with depth of n2lg , to arrange the gates. The delay in such case is given by nTnD 2lg)( ⋅= . We use basic gates of 2 inputs although in practice gates with more inputs are available. Note that if we had a basic gate of 3 inputs we would get nTnD 3lg)( ⋅= .

Figure 1.21 –A recursive building of an n inputs AND gate

Y

I0 I1

In/2-1

In/2

In/2+1

In-1

n/2 inputs

n/2 inputs


1.12 Decoders It is time now to get to our first useful system. We are going to build a Decoder. A decoder has n inputs and 2n outputs. Only one of its outputs is “1” at a given time. The combination of the n input lines, each can be “0” or “1”, determines which of the outputs is “on”, i.e., “1”. As a matter of fact, the combination at the input represents a binary number in which the rightmost digit has a value (or weight) of 1, the next digit has a value of 2, the next has a value of 4 and the next of 8 and so on. Thus the combination 0101 has a value of 0ּ8+1ּ4+0ּ2+1ּ1=5 and the combination 0111 has a value of 7 since 0ּ8+1ּ4+1ּ2+1ּ1=7. We would like to build a decoder having only two inputs, I0 and I1, forming together a two bit number [I1, I0] which can have the values 0,1,2 or 3. And so, the decoder has 4 outputs Y0, Y1, Y2, and Y3. We would like the i-th output to be “1” when the input has the combination that represent the number i. How do we do that? We use a truth table to describe the decoder and then find the equations of the outputs from that table;

[I1 I0] Y0 Y1 Y2 Y3

00 1 0 0 0

01 0 1 0 0

10 0 0 1 0

11 0 0 0 1

We immediately see that the equations of the outputs are given by:

010 IIY ⋅=

011 IIY ⋅=

012 IIY ⋅=

013 IIY ⋅= So the decoder can be built as described in Figure 1.22 below:


We would like to recursively build an n inputs decoder using (n-1) inputs decoders. The next figure shows how this is done:

Figure 1.22 – A 2 inputs → 4 outputs decoder

Y0

Y1

Y2

Y3

I0

I1

Figure 1.23 – A Recursive Decoder

I0 - In-2 n-1 Decoder #1 (n-1)→2(n-1)

Y0

Y1

Y2

Y2n-1

-1

In-1

Decoder #2 (n-1)→2(n-1)

Y2n-1

Y2n-1

+1

Y2n-1

2n-1 outputs

2n-1 outputs

2n outputs


The idea here is that whenever the new input, In-1, is “0” only the outputs of the upper decoder are “enabled”. Thus, one of them, which is determined by the combination of the inputs I0-In-2, will be “1”. The lower decoder has a “1” in the “parallel” output, but since all its outputs are “disabled” when In-1 is “0”, the lower outputs are all “0”. When In-1 is “1”, the situation is reversed. The lower decoder outputs are enabled and the upper decoder outputs are disabled, so we will have “1” in the appropriate output of the lower decoder only. We could see that through the truth table. The truth table of a single decoder is :

In-2 … I0 Y0 Y1 Y2n-1

-1

000…..00 1 000…..01 1 1

1 1 1

111…..10 1 111…..11 1

When we have two decoders but without the additional AND gates we would have the following truth table:

In-1 In-2 … I0 Y0 Y1 Y2n-1

-1 Y2n-1 Y2

n-1

000…..00 1 1 000…..01 1 1 1

1 1 1

1 1 1 1

111…..10 1 1

0

111…..11 1 1 000…..00 1 1 000…..01 1 1 1

1 1 1

1 1 1 1

111…..10 1 1

1

111…..11 1 1


With the AND gates, we make sure that the upper right hand side of the table is filled with zeros, i.e., the outputs of the lower decoder are all disabled when In-1=”0”. We also make sure that the lower left hand side of the table is filled with zeros, i.e., the outputs of the upper decoder are all disabled when In-1=”1”. And so we get the final truth table of:

In-1 In-2 … I0 Y0 Y1 Y2n-1

-1 Y2n-1 Y2

n-1

000…..00 1 000…..01 1 1

1 1 1

111…..10 1

0

111…..11 1 000…..00 1 000…..01 1

1 1 1 1

111…..10 1

1

111…..11 1 Eventually we got a truth table in which only the main diagonal has “1”s and the rest is filled with “0”s, which is exactly what is expected from a decoder. The decoder manufacturers are aware of the need of such an expansion so they add an enable input to their decoders:

Y0

Y1

Y2

Y3

I0

I1

Figure 1.24 – A decoder with an Enable input

E


This makes it simple to expand the decoder. In most cases the manufacturer adds several enable inputs, some with inverse polarity, so no glue logic is required when two such decoders are used. This is the case when we deal with discrete components. When we design a VLSI chip, we want to get rid of all redundant parts. Another look at Figure 1.23 reveals that the two decoders produce similar outputs. Therefore, a better design is to use a single decoder and duplicate its output as shown in Figure 1.26.

Y0

Y1

Y2

Y3

I0

I1

Figure 1.25 – A decoder with several Enable inputs

E1 E2 E3

Figure 1.26 – A Recursive Decoder

I0 - In-2 n-1 (n-1)→2(n-1)

Decoder

Y0

Y1

Y2

Y2n-1

-1

In-1

Y2n-1

Y2n-1

+1

Y2n-1

2n-1 outputs

2n-1 outputs

2n outputs


In Figure 1.27 we show the recursion for a 3→8 decoder built that way: It is quite easy to see that the delay of such a decoder is given by D(n)=D(n-1)+T where T is the delay of a single gate. This means that we have D(n)=n٠T. Note that this structure is similar to the first way in which we built an n input AND gate (Figures 1.18 and 1.19). We can use a "tree style" approach to get a logarithmic delay. Try to do that as a homework exercise. The cost of the system in Figure 1.26, is n inverters and much more AND gates so we just count the AND gates as the cost. Since we see that the cost follows the recursive equation C(n)= 2ּ2n-1+C(n-1)= 2n + C(n-1), we have a geometric sequence with q=2. Since C(1)=0, C(2)=4, we have C(n)= 22 + 23 + …+ 2n = 2n+1 – 4. There are two more issues in designing such systems that we did not consider. One is the length of the lines, i.e., the connecting wires. This has to do with the area of silicon that is required in

Figure 1.27 – A complete 3→8 recursive decoder

I2

I1

I0 Y0

Y7

Y1

Y2

Y3

Y4

Y5

Y6


order to implement the design on silicon. We will not discuss that issue. The other thing is the Fan out of the gates. The gates are electronic devices which output and input currents. Since the output current of a gate is limited, it can “drive” only a limited number of gates. The number of gate inputs that can be driven by the output of a gate is called the Fan out of that gate. A typical value of the Fan out is 10 to 20. We would like to analyze a much severe case where the fan out of a gate is only 2. (Less then 2 means that we can connect the output of a gate only to a single input. This is too restrictive.) In our decoder, we see that each AND gate drives two other gates, so there is no problem there. However, the inverters drive 2n-1 inputs, i.e., the number of the inputs that should be driven by the inverters is exponential! How can we overcome such a problem when the allowed fan out is only two? The answer is that we should build a “tree” of inverters to produce 2n-1 inverted outputs and 2n-1 non-inverted outputs from the In-1 input: Note that since the depth of such a tree is about n, we almost did not increase the delay of the decoder.

Figure 1.28 – A fan out expansion tree

In-1 In-1

In-1


1.13 Multiplexers A multiplexer (Mux), as a decoder, is one of the basic devices used in building computers. An n→m multiplexer, n>m, is a device with n inputs and m outputs. It also has some select inputs that determine which of the inputs are transferred to the outputs. 1.13.1 A simple mux We first define the simplest multiplexer which is a 2→1 multiplexer. It has two data inputs A and B (or I0 and I1) and one data output, Y. It also has a single select input denoted by S. Its drawing and function is given in Figure 1.29. As shown in Figure 1.29b, the multiplexer functions as a switch. The S input determines which of the two inputs is connected to the output Y. When S=”0”, we have Y=A (or Y=I0). When S=”1”, we have Y=B (or Y=I1). The function of the mux can be written as: A if S=0 Y = B if S=1

Figure 1.29b – A 2→1 mux selects between the 2 inputs

A (or I0)

B (or I1)

Y 2→1

S

Figure 1.29a – The schematic drawing of 2→1 multiplexer

A (or I0)

B (or I1)

Y

S

0

1


The truth table is therefore:

S A (I0) B (I1) Y

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

The logic function of a mux is very simple:

SBSAY ⋅+⋅= (or if we use the other notation: SISIY ⋅+⋅= 10 ). The implementation using gates is also simple:

Figure 1.30 – The inside of 2→1 multiplexer

A (or I0)

B (or I1)

Y

S


1.13.2 First expansion: A 2n→n mux , also called n*(2→1) mux The 2n→n mux has 2n inputs and n outputs as shown in Figure 1.31. The data inputs represent two n bit numbers and the S input determines which of them is transferred to the n outputs. We denote the A inputs by A[n-1:0]=[An-1,An-2,…,A0], the B inputs by B[n-1:0]=[Bn-1,Bn-2,…,B0], and the data outputs, Y by Y[n-1:0]=[Yn-1,Yn-2,…,Y0]. The function of the mux can is given by: A[n-1:0] if S=0 Y[n-1:0] = B[n-1:0] if S=1 This can be implemented using n regular 2→1 muxes, i.e., the Ai, Bi and the Yi are connected to a single 2→1 mux. So, now we understand why we called that mux an n*(2→1) mux. In Figure 1.32 we see the internal structure of a 3*(2→1) mux.

A[n-1:0]

B[n-1:0]

Y[n-1:0] n*(2→1)

Figure 1.31 – The schematic drawing of an n*( 2→1) multiplexor

S

n

n

n

Figure 1.32 – The inside of a 3*( 2→1) mux

A0

Y0

S

Y1 Y2

A1 A2

B0 B1 B2

B0

B1

B2

A0

A1

A2

Y0

Y1

Y2


1.13.3 Second expansion: A 2k→1 mux The 2k→n mux has 2k inputs and a single output as shown in Figure 1.31. There are also k select inputs denoted S[k-1:0]=[Sk-1,Sk-2,…,S1,S0]. There are 2k

combinations to the select lines. When S[k-1:0]=i, i.e., the combination of [Sk-1,…,S0] represents the number i, the i-th input is transferred to the output Y. Since there are 2k inputs we have chosen to denote those inputs by I0, I1, …, I2

k-1.

We would like to build an 8→1 (i.e., a 23→1) mux using 2 muxes of 4→1. This is pretty easy. We have to add another select input, S2, to the two select inputs, S1 and S0, of the 4→1 muxes (i.e., 22→1 muxes). This S2 input will choose between the two outputs of the two 4→1 muxes. See Figure 1.34.

I0

I2k

-1

Y2k→1

Figure 1.33 – The schematic drawing of a 2k→1 multiplexor

S[k-1:0]

I1

k

Figure 1.34 – A 23→1 mux build of two 22→1 muxes

Y2→1

S2

I0

4→1

S0

I1

S1

I3

I2

I4

4→1

S0

I5

S1

I7

I6

The number represented by S[k-1:0] is the serial number of the input transferred to the output.

S2 S1 S0

0 0 0 = 0 0 0 1 = 1 0 1 0 = 2 0 1 1 = 3 1 0 0 = 4 1 0 1 = 5 1 1 0 = 6 1 1 1 = 7


Since adding a select line exactly doubles the number of combinations, we can similarly build a 2k→1 mux using two 2k-1→1 muxes and a single 2→1 mux. Thus, we can build a 2k→1 mux recursively. In Figure 1.35 we see the recursive definition of such a mux.

The cost equation is C( k) = 2٠C(k-1) + C(1). This means that the cost is actually: C(k) = C(1)٠[1+ 2+4+…+2k-1]= C(1)٠(2k-1). Note that here we look at k instead of n where n is the number of the inputs and follows n=2k. So C(n)=C2→1٠(n-1). The delay equation is D( k) = D(k-1) + D(1). This means that the delay is given by D(k) = k٠D(1) or D(n) = lg 2 n٠ D2→1. In Figure 1.36 we show the entire tree of an 8→1 mux.

Figure 1.35 – Building a mux recursively

Y2→1

Sk-1

k-1

Sk-2,…,S0

I0

2k-1→1

I1

I2k-1

-1

I2k-1

2k-1→1

I2k-1

+1

I2k

-1 k-1

k-1

2k-1 inputs

2k-1 inputs


Figure 1.36 – The entire recursion depth in an 8→1 mux

S2

I0

I1

I2

S1 S0

I4

I5

I7

I6

2→1

2→1

2→1

2→1

2→1

2→1

2→1

I3

Y


1.13.4 Third expansion: An n*( 2k→1) mux The n*(2k→1) mux has 2k inputs, n bits each, i.e., each input represent an n bits binary number, and a single n bits output as shown in Figure 1.37. There are also k select inputs denoted S[k-1:0]=[Sk-1,Sk-2,…,S1,S0]. There are 2k

combinations to the select lines. When S[k-1:0]=i , the i-th input is transferred to the output Y. Since there are 2k inputs we have choose to denote those inputs by I0, I1, …, I2

k-1, sometimes denoted A,B,…,Z.

Similarly to the first expansion, the n*(2k→1) mux is built of n muxes of 2k→1, each of them takes care for one of the n bits. An example of a 12→3 mux, i.e., a 3*(22→1) mux, is given in Figure 1.38 below.

Figure 1.37 – The schematic drawing of an n*(2k→1) multiplexer

I0[n-1:0] (or A[n-1:0])

I2k

-1[n-1:0] (or Z[n-1:0])

Y[n-1:0] n*(2k→1)

Sk-1,…,S0

I1[n-1:0] (or B[n-1:0])

k

n

n

n

n


We can also take apart the 4→1 muxes, which , as we already know, are built of 2→1 muxes:

Figure 1.38 – The inside of a 3*( 22→1) mux

Y0

Y1

Y2

A0

A1

A2

Y0

Y2

B0

B1

B2

C0

C1

C2

D0

D1

D2

B0

A0

D0

C0

B2

A2

D2

C2

B1

A1

D1

C1

S0 S1

Y1


Figure 1.40 below shows the entire muxes family:

Figure 1.39 – The inside of a 3*( 22→1) mux in detail

A0

A1

A2

Y0

Y2

B0

B1

B2

C0

C1

C2

D0

D1

D2

S1 S0

Y1

B0

A0

D0

C0

B2

A2

D2

C2

B1

A1

D1

C1

Y0

Y1

Y2


Figure 1.40 – The entire multiplexers family

I0

I2k

-1

Y2k→1

S[k-1:0]

I1

k

A[n-1:0]

B[n-1:0]

Y[n-1:0] n*(2→1)

S

n

n

n

A (or I0)

B (or I1)

Y 2→1

S

I0[n-1:0] (or A[n-1:0])

I2k

-1[n-1:0] (or Z[n-1:0])

Y[n-1:0] n*(2k→1)

Sk-1,…,S0

I1[n-1:0] (or B[n-1:0])

k

n

n

n

n

First expansion: N bits in parallel

2nd expansion: binary tree for 2k

3rd expansion: 2k inputs of N bits in


We have only one last thing to say about muxes and decoders. They complement each other. A mux is the “inverse” of a decoder. To show that, we will change our interpretation of decoders. Let us look at a 2→4 decoder that has an enable input denoted E. If E=”0” all outputs of the decoder are “0”. If E=”1”, then the output selected by the code, or combination, of the inputs is “1”. So, one can see the decoder as a switch controlled by the inputs that transfers the E data into one of the output as in Figure 1.41. We can use Muxes and Decoders to multiplex multiple data streams on a single line as in Figure 1.42. This is called TDM, Time Division Multiplexing, since when we sequentially change the selection code S[1:0]=0→1→2→3→0→1→… etc., we have a different data stream appearing on the line at different times. Note that the rate of switching the select lines should be 4 times higher than the rate in which the data streams may change. Suggested homework: 1)A “recursive” comparator 2) "ALT" detector 3)A “tree” decoder

E

I0

I1

Y0

Y1

Y2

Y3

2→1 decoder

I[1:0]=[I1,I0]

Y0

Y1

Y2

Y3

E

2

≡

Figure 1.41 – A decoder as a controlled switch

Y0

Y1

Y2

Y3

E

2

I0

I1

I2

I3

Y

2

2

S1,S0

Figure 1.42 – 4 data lines sharing a single line


1.14 Karnaugh maps In the last part of the Boolean Algebra chapter, we demonstrate a simple technique used to simplify Sum Of Products representation of Boolean functions. We first start with functions of 3 variables. 1.14.1 Karnaugh maps of 3 variables Let us look at the following function Y :

CBACBACBAY ⋅⋅+⋅⋅+⋅⋅=1 It is equivalent to the function:

22 CBACBY ⋅⋅+⋅= This is so since CBCBCBAACBACBA ⋅=⋅⋅=⋅⋅+=⋅⋅+⋅⋅ 1)( . Whenever we find two products terms that differ only in an inverted a single component, i.e., an input variable, we can “erase” that variable from the expression and reduce the number of sums by one. It would have been nice if we could spot pairs of product terms that differ only in one variable. In the truth table of Y1, we see that the pair of CBA ⋅⋅ and CBA ⋅⋅ are not “close” to each other:

A B C Y1

0 0 0 0 0 1 0 0 1 1 2 0 1 0 0 3 0 1 1 0 4 1 0 0 0 5 1 0 1 1 6 1 1 0 1 7 1 1 1 0

We numbered the product CBA ⋅⋅ by 5 and the product CBA ⋅⋅ by 1. We see that they are far away from each other. The product numbered 6, which is also one of the products in Y, is “close” in the truth table to the one numbered 5, but these two, CBA ⋅⋅ and CBA ⋅⋅ , have two variables different in polarity, i.e., B and C have both different polarities in these two products. Let us define a measure of “distance” between two products. The Hamming Distance of two strings of bits, or two product terms, is the number of the bits that are different, i.e., the number of


variables in the product terms that have different polarity. Thus, the Hamming distance between product terms #1 and #5 is 1, while the Hamming distance between product terms #5 and #6 is 2. Let us now try to build another representation, instead of the truth table, similar to the truth table, but with a Hamming distance between its location. We draw the following two dimensional map, where the top row has all combinations in which A=”0” and the bottom row has all combinations in which A=”1” (this makes sure that the Hamming distance between 2 vertical locations is 1): We now have to select a way to fill the map with combinations according to their Hamming distance. Let us start with the combination 000, which represents CBA ⋅⋅ . We choose this combination to be at the top left square of the map.

AB,C

0

1

Figure 1.43 – Starting to fill the map

AB,C

0

1

Figure 1.44 – The next step of filling the

00

000


The square to the right of that one, should differ from that combination only in one bit. So the possible combinations, taking into account in the top row A is ”0”, are 001 or 010. We choose 001, i.e., the BC combination is 01 as in figure 1.45: This choice, automatically determines the next two squares of the top line, since the one close to it can only be 11 (only one bit is allowed to change, and we already have the combination 00, so we can only change from 01 to 11), and the last one can only be 10 (again, only one bit is allowed to change). So eventually we get the following map, which is called a Karnaugh map: Let us now fill the Karnaugh map with “1”s and “0”s according to the functionY1, similarly to the way we fill a truth-table:

Figure 1.46 – A Karnaugh map of 3 variables

AB,C

0

1

00

000

01 11 10

001

100 101 111 110

010011

4 5 6

3 210

7

AB,C

0

1

Figure 1.45 – The next step of filling the map

00

000

01

001


Since we built the map in such a way that two adjacent squares have a hamming distance of 1, we can unite any two adjacent “1”s, i.e., any two “adjacent” product terms, into a single product term having 1 less variables in it. We should “erase” the variable that is different between the two product terms represented by the “1”s. In our case, we have ones in product terms 1 and 5, marked by the blue loop in Figure 1.47 above. Since we see that the bit that is different between these two locations is A, while B and C stay the same, we conclude that the blue loop is represented by the product term of CB ⋅ . The red circle, means that the product term numbered 6 stays without a change, since we do not have any other product term which is different only in a single variable. If we had such a product term, it would have been adjacent to that “1”. We can use this method to simplify SOPs. Since when we move to the right, or to the left or up or down, only 1 bit is changing, then any two adjacent “1”s in these directions (not diagonally!) can be united. Let us see some examples: The Karnaugh map of another function CBACBACBAY ⋅⋅+⋅⋅+⋅⋅=3 is:

Figure 1.47 – A Karnaugh map of the function Y1

AB,C

0

1

00

0

01 11 10

1

0 1 0 1

0 0

4 5 6

3 210

7

Figure 1.48 – A Karnaugh map of another function

AB,C

0

1

00

1

01 11 10

1

0 1 0 0

0 0

4 5 6

3 210

7


We can cover all the “1”s in the map in a very similar manner to the previous example: Which results with CBCBAY ⋅+⋅⋅=3 . However, there is a better way, depicted in Figure 1.50 below: According to our rules the blue loop stands for the product term CB ⋅ , while the red one stands for the product term BA ⋅ since in these two locations in the map, only C is changing and A and B are “0”s. So, in this example we have: CBBAY ⋅+⋅=3 . Our conclusion is therefore, that we should cover all the “1”s in the map using as large loops as possible, since a larger loop means less variables in the product term representing the loop.

Figure 1.49 – The Karnaugh map of Y3

AB,C

0

1

00

1

01 11 10

1

0 1 0 0

0 0

4 5 6

3 210

7

Figure 1.50 – A better choice of loops for Y3

AB,C

0

1

00

1

01 11 10

1

0 1 0 0

0 0

4 5 6

3 210

7


Note that we could have find that using the Boolean Algebra rules, but we had to invest some effort, while using the Karnaugh Map, the chore is much simpler:

CBBACBBACBAACCBACBACBACBACBA

CBACBACBACBACBACBACBAY

⋅+⋅=⋅⋅+⋅⋅=

=⋅⋅+++⋅⋅=⋅⋅+⋅⋅+⋅⋅+⋅⋅=

=⋅⋅+⋅⋅+⋅⋅+⋅⋅=⋅⋅+⋅⋅+⋅⋅=

11

)()(][][3

So the Karnaugh map technique is meant to ease the chore of simplifying SOPs. Let’s look at another example: The blue loop represents the product term of CB ⋅ , the red loop represents BA ⋅ , and the dotted green loop represents the term CA ⋅ . So, we can conclude that

CABACBY ⋅+⋅+⋅=4 . However

BACBBACBABACBACBABACBACB

CBACBABACBCBBABACBCABACBY

⋅+⋅=

=⋅⋅+⋅⋅=+⋅⋅+⋅⋅+=⋅⋅+⋅+⋅⋅+⋅=

=⋅⋅+⋅⋅+⋅+⋅=⋅+⋅+⋅+⋅=⋅+⋅+⋅=

11)1()1(

)(4

A careful look at the map reveals the reason. The blue and red loops cover all the cases in which Y=”1”. Adding more loops, e.g., the green dotted one, means adding more unnecessary, i.e., redundant, product terms. So, from now and on we should try to find the minimal number of loops required to cover all the “1”s in the map.

Figure 1.51 – The map of another function, Y4

AB,C

0

1

00

1

01 11 10

1

0 1 0 0

1 1

4 5 6

3 210

7


Let us consider the following example:

CBACBACBACBAY ⋅⋅+⋅⋅+⋅⋅+⋅⋅=5 It is easy to see that we have all combinations of A and B multiplied by C (i.e., ANDed with C) and so we can write:

CCCAACAA

CBBABBACBABABABAY

=⋅=⋅+=⋅⋅+⋅=

=⋅+⋅++⋅=⋅⋅+⋅+⋅+⋅=

1)()11(

)]()([)(5

Let us look at the map. These 4 locations having all possible combinations of A and B form a square: We conclude from that example, that any rectangle of 2n x 2m “1”s, covering all 2nx2m possible combinations of n+m variables, means that we can erase those n+m variables from the group of product terms in that rectangle, leaving only the rest of the variables. In our example, we have a 21 x 21 rectangle which means that we should erase 1+1=2 variables. We see that A and B are changing, and only C stays the same for all the “1”s in the rectangle. This means that the blue loop represents C and so we have CY =5 . Another example is the following case:

Figure 1.52 – The Karnaugh map of Y5

AB,C

0

1

00

0

01 11 10

1

0 1 1 0

0 1

4 5 6

3 210

7

Figure 1.53 – Periodicity of Karnaugh map

AB,C

0

1

00

1

01 11 10

0

0 0 0 0

1 0

4 5 6

3 210

7


If we look carefully at the map, we see the Hamming distance of a square at the right hand side column from a suaqre in the left hand side column, in the same row, is also 1. So, we these two squares are adjacent and we can unite them in case both have “1”s. It is as if the map is “folded” or periodic. The same exact thing happens with more than 1 row: So here are the final rules: Cover all of the “1”s in the map, with the minimal number of rectangle loops which will be as large as possible. The reasons are simple: • Al the “1”s – Otherwise we won’t get the same function! • Minimal number of loops- So we’ll have the minimal number of product terms. • As large as possible rectangle loops- The larger the rectangle, more variables are “erased”

from the product term. 1.14.2 Karnaugh maps of 4 variables Let us now deal with the case of 4 variables. It is very similar to the 3 variables case. We start with a map having 4x4 squares forming the required 16 combinations of 4 variables (16=24). Since now we have 4 rows, each row here is identified by two variables. Let us discuss the case where ),,,( DCBAfY = . We arbitrary choose A and B to identify the rows. Again we choose A٠B to be 00 along the first row. The combination of the 2nd row, as in the three variables map, should differ by one bit only from the first row, so it could be either 01 or 10. We chose it to be

Figure 1.54 – Periodicity of a column in Karnaugh map

AB,C

0

1

00

1

01 11 10

0

1 0 0 1

1 0

4 5 6

3 210

7


AB=01 arbitrarily. The next two rows automatically should get the combinations of 11 and 10. In a similar manner to that and to the way we chose the combination of the columns in the three variables map, we assign combinations to the columns, each differs from the previous one by one bit. Eventually we get the following map: Note that if we had chosen a different assignment of the variables to the map locations, the result of the simplification will still be the same. This is so since when two product terms are different in a single variable, they will still be adjacent in the new arrangement and therefore, the simplification, which unites these two adjacent “1”s will give the same result.

Figure 1.55 – A Karnaugh map of 4 variables

AB CD

00

01

00

0000

01 11 10

0001

0100 0101 0111 0110

00100011

4 5 6

3 210

7

11

10

1100 1101

1000 1001 1011 1010

11101111

8 9 10

15 141312

11


Let us give a single example:

CBADCBADCBADCACBACBADCAY ⋅⋅+⋅⋅⋅+⋅⋅⋅+⋅⋅+⋅⋅+⋅⋅+⋅⋅= Which, according to the loops is equal to:

CBADCACAY ⋅⋅+⋅⋅+⋅= Note: In 4 variables, there are cases in which several solutions are possible. We’ll see that in the coming section. 1.14.3 Don’t care cases in Karnaugh map Let us build a “BCD to 7 Segments” decoder. A 7 segment display, is a display device having 7 light emitting segments that is capable of displaying the digits 0 – 9 by lighting some of the segments according to the required digit. Figure 1.57 below demonstrates the seven segments and the 10 digits that can be displayed.

Figure 1.56 – A Karnaugh map of 4 variables function

AB CD

00

01

00

1

01 11 10

1

1 1 0 0

0 0

4 5 6

3 210

7

11

10

0 0

0 0 1 1

0 1

8 9 10

15 141312

11

Figure 1.57 – Forming the digits 0-9 using a seven segments display device


Let us now look at the decoder that translated a 4 digits code, representing a binary number, into the seven segments. This decoder is called a BCD to Seven Segments decoder, since we use Binary Coded Decimal digit as the input for the decoder: The decoder’s truth-table is:

The digit I3 I2 I1 I0 S1 S2 S3 S4 S5 S6 S7 0 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 2 0 0 1 0 1 0 1 1 1 0 1 3 0 0 1 1 1 0 1 1 0 1 1 4 0 1 0 0 0 1 1 1 0 1 0 5 0 1 0 1 1 1 0 1 0 1 1 6 0 1 1 0 0 1 0 1 1 1 1 7 0 1 1 1 1 0 1 0 0 1 0 8 1 0 0 0 1 1 1 1 1 1 1 9 1 0 0 1 1 1 1 1 0 1 0 10 1 0 1 0 0 0 0 0 0 0 0 11 1 0 1 1 0 0 0 0 0 0 0 12 1 1 0 0 0 0 0 0 0 0 0 13 1 1 0 1 0 0 0 0 0 0 0 14 1 1 1 0 0 0 0 0 0 0 0 15 1 1 1 1 0 0 0 0 0 0 0

Figure 1.58 – The connections of a BCD to 7 Segments decoder

S1

S2 S3

S4

S5 S6

S7

I0

I1

I2

I3

BCD to 7-Seg. decodrer


The truth-table was filled as in the following example: In the 2nd line of the table, [I3,I2,I1,I0]=0001, which means the digit 1 should be displayed. And so, only S3 and S6 should be on, i.e., 1s thus forming the digit 1 as in Figure 1.57. We apply the technique of Karnaugh map to find the simplified equation of S1: which results with: 1230231230231 IIIIIIIIIIIIS ⋅⋅+⋅⋅+⋅⋅+⋅⋅= There are more possible solutions with identical number of product terms of identical sizes:

Figure 1.59 – The Karnaugh map of S1

I1I0

01

00

1

01 11 10

0

0 1 1 0

1 1

4 5 6

3 210

7

11

10

0 0

1 1 0 0

0 0

8 9 10

15 141312

11

00

I3I2

Figure 1.60 – The Karnaugh map of S1, another possibility of loops

I1I0

01

00

1

01 11 10

0

0 1 1 0

1 1

4 5 6

3 210

7

11

10

0 0

1 1 0 0

0 0

8 9 10

15 141312

11

00

I3I2


which results with: 1230230130231 IIIIIIIIIIIIS ⋅⋅+⋅⋅+⋅⋅+⋅⋅= or which results with: 1230231230121 IIIIIIIIIIIIS ⋅⋅+⋅⋅+⋅⋅+⋅⋅= These solutions are not the optimal solution for the BCD to 7 segments decoder. The reason for that is that we can do better if we take into account the fact that the combinations of [I3I2I1I0]=10, 11, 12, 13 ,14 or 15 will never happen! Thus, we actually do not care what is the result of S1 for these input combinations. In such a combination, we can choose S1 to be either “0” or “1” (but we have to choose one of them). We call such cases “Don’t care” cases and denote them in the truth table or the Karnaugh map by Ф, which stands for 0 or 1. So, the truth-table is now:

Figure 1.61 – The Karnaugh map of S1, a third possibility of loops

01

1

11 10

0

0 1 1 0

1 1

4 5 6

3 210

7

11

10

0 0

1 1 0 0

0 0

8 9 10

15 141312

11

00

I3I2 I1I0

00 01


The digit I3 I2 I1 I0 S1 S2 S3 S4 S5 S6 S7 0 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 2 0 0 1 0 1 0 1 1 1 0 1 3 0 0 1 1 1 0 1 1 0 1 1 4 0 1 0 0 0 1 1 1 0 1 0 5 0 1 0 1 1 1 0 1 0 1 1 6 0 1 1 0 0 1 0 1 1 1 1 7 0 1 1 1 1 0 1 0 0 1 0 8 1 0 0 0 1 1 1 1 1 1 1 9 1 0 0 1 1 1 1 1 0 1 0 10 1 0 1 0 Ф Ф Ф Ф Ф Ф Ф 11 1 0 1 1 Ф Ф Ф Ф Ф Ф Ф 12 1 1 0 0 Ф Ф Ф Ф Ф Ф Ф 13 1 1 0 1 Ф Ф Ф Ф Ф Ф Ф 14 1 1 1 0 Ф Ф Ф Ф Ф Ф Ф 15 1 1 1 1 Ф Ф Ф Ф Ф Ф Ф

and the Karnaugh map of S1 is therefore

Figure 1.62 – The Karnaugh map of S1 with “Don’t Care” cases

01

1

01 11 10

0

0 1 1 0

1 1

4 5 6

3 210

7

11

10

Ф Ф

1 1 Ф Ф

Ф Ф

8 9 10

15 141312

11

00

I3I2 I1I0

00


We can set any of the don’t care cases to be “0” or “1” as we please, and then draw the loops. It seems that we can reduce the product terms to a minimum if we choose all of the don’t care cases to be used as “1”s. So we have: which results with: 01302021 IIIIIIIS ⋅++⋅+⋅= . This is definitely simpler to implement, i.e., less gates, compared to the previous results. Again, there may be more possibilities. In our specific case, we have another solution depicted in Figure 1.64 below.

Figure 1.63 – The Karnaugh map of S1, using the Don’t Cares as “1”s

01

1

01 11 10

0

0 1 1 0

1 1

4 5 6

3 210

7

11

10

Ф Ф

1 1 Ф Ф

Ф Ф

8 9 10

15 141312

11

00

00 I3I2 I1I0

I2I0

I2I0

I3

I1I0


which results with: 12302021 IIIIIIIS ⋅++⋅+⋅= which has the same complexity as the other solution. We can draw Karnaugh maps of 5 and 6 variables. Those are 3 dimensional maps. More variables result with more than 3 dimensions. At this point, we know enough about Boolean Algebra , gates and equations, so we can design all kinds of desired systems. We will use our ability to design arithmetic units after learning about computer arithmetic in the next chapter.

Figure 1.64 – The Karnaugh map of S1, using the Don’t Cares as “1”s

01

1

01 11 10

0

0 1 1 0

1 1

4 5 6

3 210

7

11

10

Ф Ф

1 1 Ф Ф

Ф Ф

8 9 10

15 141312

11

00

00 I3I2 I1I0

1.1) Definition of Boolean Algebra - Tel Aviv Universitymatias/Classes/Computer...

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