11

2

Signal sources (a) Thévenin form, (b) the Norton form.

Figure 1.1

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Figure 1.3 Sine-wave voltage signal of amplitude Va and frequency f = 1/T Hz. The angular frequency v = 2pf rad/s.

EX: 1 Sine-wave signal amplitude Va, frequency f = 1/T Hz.

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Figure 1.4 A symmetrical square-wave signal of amplitude V.

EX 2: A symmetrical square-wave signal of amplitude V.

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Figure 1.5 The frequency spectrum (also known as the line spectrum) of the periodic square wave of Fig. 1.4.

The frequency spectrum of periodic square wave in EX 2 Useful for signal analysis

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Figure 1.2 An arbitrary voltage signal vs(t).

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Figure 1.6 The frequency spectrum of an arbitrary waveform such as that in Fig. 1.2.

Frequency spectrum of arbitrary waveform

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Figure 1.7 Sampling the continuous-time analog signal in (a) results in the discrete-time signal in (b).

Sampling continuous-time analog signal

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Figure 1.8 Variation of a particular binary digital signal with time.

Binary Digital Signals: variations with time.

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Figure 1.9 Block-diagram representation of the analog-to-digital converter (ADC).

Analog-to-digital conversion (ADC) or A/D.

Most signals in real world AnalogNeed A/D to process in digital domain

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Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 m, W = 0.2 to 100 m, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.

NMOS transistor structureSource (S), Drain (D), Gate (G)L channel length, W width of transistor

NMOS transistor cross-section

1212

Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.

CMOS structure, today’s ICsboth NMOS & PMOS transistorsPMOS formed in an n-well

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Figure 10.12 A two-input CMOS ……. gate.

CMOS Logic gate Example 1 ?

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Figure 1.28 A logic inverter operating from a dc supply VDD.

Digital Logic inverter

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Figure 1.29 The VTC is approximated by three straight line segments. Note the four parameters of the VTC (VOH, VOL, VIL, and VIH) and their use in determining the noise margins (NMH and NML).

Inverter Transfer CharacteristicVTC = voltage transfer characteristic

Ideal inverter

Typical inverter

Vol = output low; Voh = output high; Vil = max input interpreted as “0”; Vih = min input interpreted as “1”;

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Figure 1.31 (a) The simplest implementation of a logic inverter using a voltage-controlled switch; (b) equivalent circuit when vI is low; and (c) equivalent circuit when vI is high. Note that the switch is assumed to close when vI is high.

Inverter Circuit Implementation

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Figure 1.32 A more elaborate implementation of the logic inverter utilizing two complementary switches. This is the basis of the CMOS inverter studied in Section 4.10.

CMOS inverter implementationThe most common inverter

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Figure 1.34 Example 1.6: (a) The inverter circuit after the switch opens (i.e., for t 0). (b) Waveforms of vI and vO. Observe that the switch is assumed to operate instantaneously. vO rises exponentially, starting at VOL and heading toward VOH .

Inverter Operation

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Figure 1.35 Definitions of propagation delays and transition times of the logic inverter.

Inverter Propagation delays 10/90 rule

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Figure 1.10 (a) Circuit symbol for amplifier. (b) An amplifier with a common terminal (ground) between the input and output ports.

Amplifier: Circuit symbol

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Figure 1.11 (a) A voltage amplifier fed with a signal vI(t) and connected to a load resistance RL. (b) Transfer characteristic of a linear voltage amplifier with voltage gain Av.

Voltage Amplifier & Transfer characteristic

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Figure 1.12 An amplifier that requires two dc supplies (shown as batteries) for operation.

Some Amplifiers Require 2 suppliesEg 2 supply +ve & -ve swings

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Figure 1.13 An amplifier transfer characteristic that is linear except for output saturation.

Amplifier transfer

characteristics

Amps have limitations .. may saturate ..signal

(2)Amp linearity desiredVout(t) = A * Vin(t)

input

output

How many power supplies ?

L+ >= A*vi

Amplifier Biasing – ensures linearity

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Figure 1.14 (a) An amplifier transfer characteristic that shows considerable nonlinearity. (b) To obtain linear operation the amplifier is biased as shown, and the signal amplitude is kept small. Observe that this amplifier is operated from a single power supply, VDD.

Nonlinear response

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Figure 1.15 A sketch of the transfer characteristic of the amplifier of Example 1.2. Note that this amplifier is inverting (i.e., with a gain that is negative).

Inverting Amplifier Example Top limit = 10v, lower limit = 0.3v

Output 180 degrees out of phase with input

L- = 0.3vVt = 0.690

Vo = 10 - 10EXP(-11) * eEXP(40Vt)

L+ =~ 10v@ Vt = 0

For 5 V bias@ Vo = 5v Vt = 0.673

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Figure 1.17 (a) Circuit model for the voltage amplifier. (b) The voltage amplifier with input signal source and load.

Voltage Amplifier Circuit Model used for simulation, circuit analysis

Gain = Aw; input resistance = Ri, Output resistance = Ro

vo = Aw * vi * RL/(RL + Ro) ; effect of output resistance Ro vo / vi = Aw * RL/(RL + Ro) ; voltage gainvi = vs * Ri / (Ri + Rs) ; effect of Ri

vo / vs = Aw * Ri / (Ri + Rs) * RL/(RL + Ro); overall voltage gain accounting for input / output impedances

27Figure 1.18 Three-stage amplifier for Example 1.3.

More Gain ? Use Cascaded stages Ex 1.3Input stage needs high input impedance

Output stage needs low output impedanceInput resistance of a stage = load resistance of previous stage

Vi1 / Vs = 1 M / ( 1M + 100k) = 0.909 ; effect of 1st RinAv1 = Vi2 / Vi1 = 10 * 100k / (100k + 1k) = 9.9 ; gain 1st stage, A = 10Av2 = Vi3 / Vi2 = 100 * 10k / (10k + 1k) = 90.9 ; gain 2nd stage, A = 100Av3 = VL / Vi3 = 1 * 100 / ( 100 + 10) = 0.909 ; gain 3rd stage, A = 1Av = VL / Vi1 = 9.9 * 90.9 * 0.909 = 818 ; 3 stage gainVL / Vs = 818 * 0.909 = 743.6 ; from source to loadIdeal Gain = 10 * 100 = 1000

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Figure 1.21 Typical magnitude response of an amplifier. |T(v)| is the magnitude of the amplifier transfer function—that is, the ratio of the output Vo(v) to the input Vi(v).

Amplifiers have limited bandwidth frequency response of Amplifiers

Constant gain between w1 & w2 (Bandwidth) ; otherwise lower gain. Amp chosen so its BW coincides with required spectrum to be amplified … otherwise signals distorted

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Figure 1.26 Frequency response for (a) a capacitively coupled amplifier, (b) a direct-coupled amplifier, and (c) a tuned or bandpass amplifier.

Frequency Response Amplifier output coupling

Capacitively coupledAmp ..Eg audio

DC (direct ) coupledGain at low freq & DCUsed in ICa.k.a low-pass amp.

Band pass AmpBandpass Filter Tuned Amps.TV, signal processing..

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Figure 1.27 Use of a capacitor to couple amplifier stages.

Capacitively Coupled Amplifier Stages

An NMOS Common Source Amplifier

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Figure 4.26 (a) Basic structure of the common-source amplifier. (b) Graphical construction to determine the transfer characteristic of the amplifier in (a).

Amp. Circuit Xfer Characteristic

NMOS common source Amp. Cont’d Xfer Characteristic

3232Figure 4.26 (Continued) (c) Transfer characteristic showing operation as an amplifier biased at point Q.

Biased at point Q