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Unit III DIGITAL LOGIC

I) Logic gates:

Apart from the arithmetic operations, there are logical operations involved in the processing.

The logical operations involve some elements. These elements are NOT, OR and AND.NOT

is the opposite of negation or inversion. Negation of True is False. OR is another logical

element which represents either or. AND is another logical element which represents two

together.o following are the !asic logical elements: AND , OR, NOT

"n #$%& 'eorge (oole invented s)m!olic logic. This is *nown toda) as (oolean alge!ra. +ach

varia!le in (oolean alge!ra has either of two values. True or False. The purpose of this two

state alge!ra was to solve logic pro!lems. As we saw !efore the computers thin* in terms of

!inar) -high or low it is appropriate to sa) logic is the core of computers. To implement this

logic circuits are used. "n the logic circuits 'ates are used. A 'ate is a small circuit with one

or more input signals !ut onl) one output signal. 'ates are digital circuits -twostate.

There are several gates such as OR, AND, "nverter, etc. +ach has s)m!ol to represent them.

/et us see them one !) one.

AND GatesThe AND 'ate has two or more input signals !ut onl) one output signal. All the inputs must

!e high to get a high output. "f we have two inputs to this AND gate and !oth the inputs are

high then the output will !e high otherwise the output will !e low. All the possi!le inputs and

outputs are shown in the following ta!le.

Truth Ta!le

Y = A . B

AND Gate symbo

AND !"nction

OR Gates

The OR gates has two or more input signals !ut onl) one output signal. "f an) input signal is

high, the output signal is high. "f we have two inputs to this OR gate and an) of the two inputs

is high then the output will !e high. This can !e shown in a ta!le !elow with all the possi!le

inputs and corresponding outputs.

Truth Ta!le

Y=A+B

OR Gate symbol

OR function

NOT or Inverter:

A /ow input produces a high output, and a high input produces low output. "n !inar) format if

the input is 0 the output will !e # and if the input is # then the output will !e 0. The ta!le

shows the input and output possi!ilities.

Unit III Digital Logic 1age #

A B Y

0 0 0

0 # 0

# 0 0# # #

A B Y

0 0 0

0 # #

0 #

# # #

In#"t O"t#"t

0 #

# 0

A

B

2

A

B

b

b

2

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Y = A

NOT Gate symbol NOT function

NAND Gate

NAND 'ate is a com!ination of an AND gate with an inverter. An AND 'ate followed !) an

inverter.

3hatever the output of the AND gate, it will !e inverted !) the inverter. This is the formation

of NAND gate. The sign and the ta!le is shown !elow. The NAND operation is called 4niversal

Operation or gate.

Y = AB

NAND $ign

NOR Gate

NOR 'ate is a com!ination of an OR gate with an inverter. An NOR 'ate followed !) an

inverter.

The NOR operation is also a 4niversal Operation or 'ate.

Y = A%B

NOR $ign

Exclusive OR Gate

An OR 'ate recogni5es with one or more #s as inputs and gives output as #. The +6clusiveOR

is di7erent8 it recogni5es onl) that have odd num!er of #s. The following ta!le shows di7erent

inputs and outputs.

Y= A &OR B

Y= A B

'(OR sign

Unit III Digital Logic 1age 9

A B Y

0 0 #

0 # #

# 0 #

# # 0

A B Y

0 0 #

0 # 0# 0 0

# # 0

A B Y

0 0 0

0 # #

# 0 ## # 0

A

B

2

A

B

2

A

B

2

A

B

2

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XOR GATE Input Output

Exclusive NOR Gate or XNOR+6clusive NOR 'ate is a!!reviated as NOR. This is logicall) e;uivalent to and OR gate followed

!) an inverter. Following

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The S-R Flip op!

The circuits has two inputs, s-et and R -Reset and two outputs @ and @ and consists of two

NOR gates connected in a feed!ac* arrangement.

First, /et us show that the circuit is !ista!le. Assume that !oth and R are 0 and that @ is 0. The

inputs to the lower NOR gate are @ B 0 and B 0. Thus, the output @ B # means that the inputs

to the upper NOR gate are @B# and RB0, which has the output @ B 0.

Thus, the state of the circuit is internall) consistent and remains sta!le as long as B R B 0. A

similar line of reasoning shows that the state @ B #, @ B 0 is also sta!le for R B B 0.

Thus, this circuit can function as a #!it memor). uppose that changes to the value #. Now the

inputs to the lower NOR gate are B# , @ B0. After some time dela) t, the output of the lower

NOR gate will !e @ B 0.

R characteristic Ta!le

R @nC#

0 # @n

0 # 0

# 0 #

# #

o, at this point in time, the inputs to the upper NOR gate !ecome RB0 , @ B 0. After another

gate dela) of t, the output @ !ecomes #. This is again a sta!le state. The inputs to the lower gateare now B #, @ B#, which maintain the output @B0. As long as B# and R B0, the outputs willremain @ B#, @ B 0. Furthermore, if returns to 0, the outputs will remain unchanged.O!serve that the inputs B #, R B# are not allowed, !ecause these would produce an inconsistentoutput - !oth @ and @ e;ual 0.Cloc"e# S-R Flip-Flop!

The output of the R latch changes, after a !rief time dela), in response to a change in the input.This is referred to as as)nchronous operation. >ore t)picall), events in the digital computer ares)nchroni5ed to a cloc* pulse, so that changes occur onl) when a cloc* pulse occurs. This t)pe ofdevice is referred to as a cloc*ed R ?ip?op. Note that the R and inputs are passed to the NORgates onl) during the cloc* pulse. R

@

=loc*

@

D Flip $ Flop!

One pro!lem with R ?ip ?op is that the condition R B #, B # must !e avoided. One wa) to dothis is to allow ust a single input. The D ?ip ?op accomplishes this. () using an inverter, the twoAND gates are guaranteed to !e the opposite of each other.

Unit III Digital Logic 1age &

@

@

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The D ?ip ?op is sometimes referred to as the data ?ip ?op !ecause it is, in e7ect, storage forone !it of data. the output of the D ?ip ?op is alwa)s e;ual to the most recent value applied tothe input. Eence, it remem!ers and produces the last input. "t is also referred to as the dela) ?ip?op, !ecause it dela)s a 0 or # applied to its input for a single cloc* pulse.

@

D @nC# cl*0 0# #

@ D

%-& Flip-Flop!

/i*e the R ?ip ?op, it has 9 inputs. Eowever, in this case all possi!le com!inations of inputvalues are valid. "n its characteristic ta!le, we can note that the

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Data /ines

D#$ D#I D#K D#% D#& D# D#9 D##

D0$ D0I D0K D0% D0& D0 D09

D0#

Output /ines--8-bit Parallel Register--

Shift Registers:

A hift register accepts and H or transfers information seriall). =onsider, for e6ample, the

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"n s)nchronous counter, all of the ?ip ?ops change state at the same time. This t)pe is muchfaster, it is the *ind used in =14s.Ripple Counter:An as)nchronous counter is also referred to as a ripple counter, !ecause the change that occursto increment the counter starts at one end and ripples through to the other end.

Eigh

=loc*

@0 @# @9 @

---Seuential Circuit----

"n the illustrated implementation, the counter is incremented with each cloc* pulse. The and G

inputs to each ?ip ?op are held at a constant #. This means that, when there is a cloc* pulse, the

output at @ will !e inverted - # to 08 0 to #.Note that the change in state is shown as occurring with the falling edge of the cloc* pulse8 this

is *nown as an edgetriggered ?ip ?op. "f one loo*s at patterns of output for this counter, it can

!e seen that it c)cles through 0000, 000#, ......###0,####,0000 and so on.

)nchronous counters: the ripple counter has the disadvantage of the dela) involved in changing

value. To overcome this disadvantage, =14s ma*e use of s)nchronous counters, in which all of

the ?ip?ops of the counter change at the same time.

Eigh

=loc*--Design of a S!nchronous counter--

For a !it counter, three ?ip ?ops will !e needed. /et us use G ?ip?ops. /a!el the

uncomplemented output of the three ?ip ?ops A, (,= respectivel), with = representing the lease

signiultiple6ersHData selectors

A digital multiple6er has N inputs and onl) one output. () appl)ing control signals an)one inputcan !e made availa!le at the output terminal. "t is also called data selector. The control signalsare applied to the select lines to select the desired input.

+6amples :"= I%0 # of #K Data selectors H>ultiple6ers"= I%9 # of $ Data selectorsH>ultiple6ers

D0

D#

"N14T D9 O4T14T "'NA/

"'NA/ .

.

Unit III Digital Logic 1age I

D"'"TA/

>4/T"1/++

R

@

=/G

G

@

@

=/G

G

@

@

=/G

G

@

@

=/G

G

@

(

=/G

G

(

A

=/G

G

A

=

=/G

G

=

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DN

+/+=T /"N+ "I#: DI#I$%L &UL$IPL'('R

vii Digital Demultiple6ersHDecoders

A digital demultiple6er has # input and N outputs. The meaning of demultiple6er is one into

man). () appl)ing control signals the input signal can !e made availa!le at an)one of outputterminals. "t performs reverse operation of a multiple6er.+6ample : "= I%& is a # to #K demultiple6erH& to #K decoder.

D0

D#

"N14T D9 O4T14T "'NA/

"'NA/ .

. DN

+/+=T /"N+ "I#: DI#I$%L D'&UL$IPL'('R

viii (oolean Alge!ra

(oolean Alge!ra is mathematical s)stem for formulating logical statements with s)m!ols so that

pro!lems can !e solved in a manner to ordinar) alge!ra.

(oolean alge!ra is the mathematics of digital s)stemsA !asic *nowledge in the (oolean alge!ra re;uired to stud) and anal)sis of logic circuits.

"t is a convenient and s)stematic wa) of e6pressing and anal)5ing the operations of logic circuits.

RuleNum!er

(oolean +6pression

# A C 0 B A9 A C # B # A . 0 B 0& A.# BA% A C A B A

K A CB #I A .A B A$ A . =0J

=A#0 A + AB =A## A +AB = A + B#9 (A + B) (A + C) = A + BC

=ommutative /aw : A C ( B ( C A A( B (AAssociative /aw : AC-(C= B -AC(C= A-(= B -A(=

Distri!utive law: A-(C= B A( C A= A C-(= B -AC(. -AC=De morganMs Theorems : A C ( B A . ( A.( B A C (

Unit III Digital Logic 1age $

D"'"TA/

D+>4/T"1/+

+R

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i6 Garnaugh >ap >ethod

The Garnaugh map method is a graphical techni;ue for simplif)ing (oolean functions. "t is a twodimensional of a Truth Ta!le. "t provides a simpler method for minimi5ing logic e6pressions. Themap method is ideall) suited for four or less varia!les.A Garnaugh map for n varia!les is made up of 9ns;uares. +ach s;uare designates a product termof a (oolean e6pression. For product terms which are present in the e6pression, #s are written inthe corresponding s;uares8 0s are written in those s;uares which correspond to product termsnot present in the e6pression.

=onsider a map of two varia!les:

A A 0 #

(

"n the map, 0 represents ,,and # represents A. imilarl), for varia!le (.

For e6ample, for the (oolean functions 2 B C A(

0 #

0

#

+6ample : simplif) 2B C

0 #

0

#

Two adacent s;uares containing # have !een

grouped together. To show the grouping, the) have !een encircled. For simpli

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o the varia!le which is common to adacent s;uares is selected, and the varia!le which is not

common is discarded.

+6ample: simplif) 2B C A( C

0 #

0

#

impli

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A(= 00 0# ## #0

0 A=

# A (

The simplis etc.,

A se;uential circuit consists of a com!inational logic and storage elements. The output of a

se;uential circuit is not onl) a function of a present inputs !ut also of past inputs. The state of the

storage elements depends upon the preceding inputs and the preceding states of the elements.

Therefore, the output of a se;uential circuit !ecomes a function of !oth the present inputs and the

present internal states of the se;uential circuit. To reali5e se;uential circuits in addition to AND,

OR and NOT gates, ?ip?ops are also re;uired.

+6amples of se;uential circuits are: registers, shift registers, counters, etc.,The two maor uses of se;uential circuits in digital s)stems are:# As memories to store information while processing

9 As control circuits to generate control signals which are essential to select and ena!le ase;uence of data transfer or data processing steps in the e6ecution of multistep tas*s.

The se;uential circuits which emplo) cloc* are called s)nchronous se;uential circuits. "n a

s)nchronous se;uential circuit all memor) elements are cloc*ed latches or cloc*ed ?ip ?ops. The

design and operation of se;uential circuits is greatl) simpli

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# # 0 #

"t is concluded that the sum is e;ual to A OR (. "t means that the outputs of an +=/4"+OR

gate will give the sum. The carr) is e;ual to A AND (. The output of an AND gate will give the

carr).

B A ( C A (

B A (

=BA(

"ull %**er

A logic circuit which performs addition of three !inar) !its is called a Fulladder.A full adder can !e !uilt using two half adders and an OR gate.

"nputs OutputsA ( = um =arr) =0 0 0 0 00 0 # # 00 # 0 # 00 # # 0 ## 0 0 # 0# 0 # 0 #

# # 0 0 ## # # # #

A =arr)

=arr)

( um

=arr)

um

=

--"ull %**er+

---------

Unit III Digital Logic 1age #9

=arr)

=

A

B

um

EA/F

ADD+R

A

(

um

=arr)

=

EA/F

ADD+R

EA/F

ADD+R

A

2