104 - Analog Peripherals - RevF

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  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 1

    PSoC 3 / PSoC 5 104:Analog Peripherals

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 2

    Section Objectives

    Objectives, you will be able to: Understand analog in PSoC 3 / PSoC 5 Use and implement analog peripherals in PSoC Creator

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 3

    Analog Subsystem

    RoutingMultiplexersComparatorsOpampsDACs (V & I)DeltaSigma ADCProgrammable Analog PGA

    TIA Mixer

    CapSense Touch SensingDigital Filters

    !"

    !"

    !"

    !"

    # #

    "

    $%

    #!$

    $%

    #!$

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 4

    Analog Matrix

    Analog Globals: 8 internal 16 general purpose to pins 2 multiplex busses to pins 16 direct connections to pins

    More than 320 switches Most are one hot

    Vio0

    SIO

    P12[3]

    SIO

    P12[2]

    GP

    IOP

    15[3]

    GP

    IOP

    15[2]

    SIO

    P12[1]

    SIO

    P12[0]

    GP

    IOP

    3[7]

    GP

    IOP

    3[6]

    Vio3

    Vccd

    Vssd

    Vssio

    Vddd

    GPIOP6[0]

    GPIOP6[3]

    GPIOP6[2]

    GPIOP6[1]

    GPIOP15[4]GPIOP15[5]GPIOP2[0]

    GPIOP2[4]

    GPIOP2[3]

    GPIOP2[2]

    GPIOP2[1]

    Vio2

    GP

    IOP

    2[5]

    GP

    IOP

    2[7]

    GP

    IOP

    2[6]

    SIO

    P12

    [4]

    SIO

    P12

    [5]

    GP

    IOP

    6[4]

    GP

    IOP

    6[5]

    GP

    IOP

    6[6]

    GP

    IOP

    6[7]

    Vio

    1

    SIOP12[6]

    SIOP12[7]

    USB IOP15[6]

    USB IOP15[7]

    Vusb

    Vddd

    Vssd

    Vssio

    Vccd

    GPXTP15[0]

    GPXTP15[1]

    GPIOP3[5]GPIOP3[4]GPIOP3[3]GPIOP3[2]GPIOP3[1]

    AGR[4]

    AGR[7]

    AGR[6]

    AGR[5]

    AGL[0]

    AGL[3]

    AGL[2]

    AGL[1]AGR[0]

    AGR[3]

    AGR[2]AGR[1]

    * * *

    *

    *

    *

    *

    **

    *

    *

    * Pins on all packages

    dsm0

    DSM

    v0

    v2

    v1

    v3

    i1

    i3

    i0

    i2

    VIDAC

    7 6 5 4 3 2 1 0

    7 6 5 4 3 2 1 0

    76543210

    76543210

    comp0

    comp2

    comp1

    comp3

    Comparator+-

    +-

    +-

    +-

    AG

    L[4]

    AG

    L[7]

    AG

    L[6]

    AG

    L[5]

    AG

    L[0]

    AG

    L[3]

    AG

    L[2]

    AG

    L[1] A

    GR

    [0]

    AG

    R[3

    ]A

    GR

    [2]

    AG

    R[1

    ]

    AG

    R[4

    ]

    AG

    R[7

    ]A

    GR

    [6]

    AG

    R[5

    ]

    Notes:

    AM

    UX

    BU

    SR

    AM

    UX

    BU

    SR

    AM

    UX

    BU

    SL

    AM

    UX

    BU

    SL

    i1

    i3i2

    i0

    Vref Bus

    LCD and CapSense signals are not shown. Rev 2801/28/09

    abuf2

    abuf0

    abuf3

    Vdda

    Vssa

    Vsab

    Vssd

    Vcca

    GP

    IOP

    0[0] *

    GP

    IOP

    0[1] *

    GP

    IOP

    0[2] *

    GP

    IOP

    0[3] *

    GPIOP0[4]

    *

    GPIOP0[5]

    *

    GPIOP0[7] *

    GP

    IOP

    1[3]

    GP

    IOP

    1[2]

    GP

    IOP

    1[1]

    GP

    IOP

    1[0]

    * * * *

    GP

    IOP

    1[4]

    *G

    PIO

    P1[

    5]*

    GPIOP1[6]*

    GPIOP1[7]*

    GPIOP5[7]GPIOP5[6]GPIOP5[5]GPIOP5[4]

    GPIOP4[4]

    GPIOP4[7]

    GPIOP4[6]

    GPIOP4[5]

    GP

    IOP

    5[2]

    GP

    IOP

    5[3]

    GP

    IOP

    5[1]

    GP

    IOP

    5[0]

    GPIOP4[3]

    GPIOP4[2]

    abus

    l0

    Vssio

    Vdab

    abuf1

    *

    * * **

    * *

    *

    *

    *

    *

    *

    *

    *

    *

    *

    AGL[4]

    AGL[7]

    AGL[6]

    AGL[5]

    GP

    IOP

    4[0]G

    PIO

    P4[1]

    Vssa

    AMUXBUSL AMUXBUSR

    AMUXBUSL AMUXBUSR

    AMUXBUSL AMUXBUSR

    abus

    l1

    abus

    l2

    abus

    l3

    abus

    r3

    abus

    r2ab

    usr1

    abus

    r0

    ExVrefL

    ExVrefR

    TS ADC

    :

    Ind

    Vba

    t

    Vss

    b

    Vb

    Vss

    io

    XR

    ES

    _N

    Vss

    d

    * * * * *

    VBE

    VSS ref

    ExVrefRExVrefL

    90

    36

    28

    13

    44

    +-

    qtz_ref

    refs

    GPIOP3[0]

    GPIOP0[6] *

    LPFin0

    out0

    in1out1

    5

    refbufl

    AG

    L[0]

    vssa

    refbufr

    AG

    R[0]

    vssa

    sc0 sc1

    sc2 sc3

    VinVrefout

    out

    out

    SC/CT

    out104

    MuxSwitch

    Connection

    Large (lower z)

    Small (higher z)

    #

    266

    93/122

    Size

    Other:DFT 24 SmallLCD 15 Small

    VinVref

    VinVref

    VinVref

    ANALOG ROUTING IS VERY COMPLEX, THEREFORE

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 5

    Analog Matrix

    PSoC Creator enables: Schematic entry Automatic place and route Optimizations for analog and digital

    routing

    Window comparator example

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 6

    Routing with Muxes

    Analog Multiplexer Specs: Bi-directional Either single ended or differential Actual routing hidden from user May have more than one connection at a time Analog routing may be controlled by digital subsystem

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 7

    Analog Peripheral: Comparator

    Specs: Up to four per device Speeds:

    Fast - 30ns/400uAMedium - 100ns/100uASlow - 2us/20nA

    Accuracy:Vioff 3mV Med mode, 4mV fast modeVioff 1mV Med mode, 2mV fast mode (custom trim)Zero-adjust: Internal iDAC

    Hysteresis:10 mV nominalMay be enabled or disabled

    APIs:void Comp_Start( );void Comp_Stop( );void Comp_SetSpeed(speed);uint8 Comp_ZeroCal( );uint8 Comp_GetCompare( );

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 8

    Analog Peripheral: Opamp

    Specs:

    Opamp/25 mA Analog Buffer for:Driving external loadsFilters to 200 kHzPeak detectorSlow comparator

    Up to four Opamps per device

    25 mA Analog Buffer

    Output = 25 mA drive

    Input offset < 2 mV Unity GBW = 3 MHz min

    Slew rate = 3 V/usec

    Similar to LM356

    APIsvoid ABuf_Start( );void ABuf_Stop( );void ABuf_SetPower(power);

    Vin

    Vout

    On-Chip

    Off-Chip

    Low Pass Filter

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 9

    Analog Peripheral: VDAC8 and IDAC8

    Commonalities DAC data source may be data register or DAC Bus

    CPU or DMA may write to data register Data strobe from data register write or Strobe input

    Clock or UDB may be used for Strobe

    IDAC8 and VDAC8 are the same block with V and I outputs

    CPU or DMA

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 10

    Analog Peripheral: IDAC8

    Specs: Source or sink Ranges:

    0 to 31.875 uA (125 nA/bit)

    0 to 255 uA (1 uA/bit)0 to 2.04 mA (8 uA/bit)

    Power (ICC):100uA max slow mode400 uA max fast mode

    Vdd

    Sink Source

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 11

    Analog Peripheral: VDAC8

    Specs: Ranges:

    0 to 1.02 V (4 mV/bit)

    0 to 4.08 V (16mV/bit)

    Output R =~ 40k ohmsMust be buffered for external use

    Some internal loads dont require buffering

    Power (ICC):100uA max slow mode

    400 uA max fast mode

    Speed 1 Msps (1V mode)

    250 ksps (4V mode)

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 12

    Analog Peripheral: Delta Sigma ADC

    Specs: High speed, high resolution ADC Selectable resolutions (8- to 20-bit) Several input ranges High impedance input buffers

    Programmable gain (1,2,4,8)

    Chopper mode for low offset

    May be bypassed

    Single and differential input modes Wide range of sample rates 10 to

    375K Multiple reference sources Drop, connect, and go!

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 13

    Analog Peripheral: Delta Sigma ADC

    Specs (continued): Programmable resolution/rate

    8 bit, 375ksps (Continuous)

    12 bit, 192 ksps (Continuous)16 bit, 48 ksps (Continuous)

    16 bit, 12 ksps (Fast Filter)

    20 bit, 45 sps (Fast Filter)

    Reference: 1.024 V +/- 1.0 mV (0.1%) Scale: +/- 1.0 %

    Gain compensation in decimator

    Offset: +/- 100 uV Chopper stabilized

    LinearityINL 1.0 LSB (for 16 bit)DNL 0.5 LSB

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 14

    Programmable Analog Peripherals

    Specs: Combination of functions from PSoC1 programmable analog catalog

    Switched-Capacitor (SC)-based analog Continuous Time blocks (CT)-based analog

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 15

    Analog Peripheral: PGA

    Specs: Programmable Gain Amplifier Amplify signals without external

    components Gain: 1x to 50x Vin and Vref to any pin Vin and Vref to most references

    Resistance on connection to Vrefaffects gain accuracy

    Accuracy: Gain: +/- 1.5% Vos: 10 mV

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 16

    Analog Peripheral: PGA_Inv

    Specs: Inverting PGA

    Amplify signals without external components

    Gain: -1x to -49x

    Vin and Vref to any pin Vin and Vref to most references

    Resistance on connection to Vref affects gain accuracy

    Differential In --- Differential OutUse for high impedance differential signalsIdeal for bridge applications like strain gaugesNormally routed to differential ADC

    Accuracy: Gain: +/- 1.5% Vos: 10 mV

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 17

    Analog Peripheral: TIA

    Specs: Trans-Impedance Amplifier Conversion gain is a resistor

    Current IN Volts OUT

    Vout = Vref - Iin*RFB

    Adjustable RFB = Programmable gain (20 k to 1 M)Adjustable CFB = Programmable bandwidth (up to 3 pF)

    External resistor connection for greater accuracy

    Calibrated with on-chip IDAC (internal resistors +/- 30%)

    Applicable to current output sensorsGlucose meters

    Photo-diodes - light meters, medium speed IR receiver

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 18

    Analog Peripheral: Mixer

    Specs: LO_Freq = Local Oscillator (not

    Low)

    Mixer Modes: Up-Mixer: Multiplier

    Clock up to 1.0 MHz

    Output at FLO +/- FIN

    Example 200 kHz input clocked at 255 kHz to narrowband filter at 455 kHz

    Down-Mixer: SamplerClock up to 4.0 MHzOutput at FIN - FLO

    Example 455 clocked at 435 kHz to low-pass filter at 25 kHz

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 19

    Analog Peripheral: CapSensefi

    Specs: CapSense peripheral uses configuration of existing system

    resources Two simultaneous CapSense systems possible

    CapSense Configurations:All have similar configuration parameters like buttonsButtons: Basic CapSense sensor with On/Off detection

    Sliders: Linear and radial with interpolated positioning (also supports diplexing to reduce pin count)

    Touch Pads: X, Y interpolated positioning

    Matrix Buttons

    Proximity SensorsGeneric Sensors

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 20

    Analog Peripheral: DFB

    Specs: Digital Filter Block What it does:

    Works on digitized data from ADC or any other source

    Sequentially calculate multiple filters using sum of productsRemoves noise and unwanted frequencies from signals

    Replaces analog filters requiring external components

    Supports zero crossing, full wave detection, squelch, etc

    How it does it:No coding or coefficientshandled by GUI

    24-bit filter co-processor128 pairs of data/coefficients

    What it doesnt do:Control loops

    Analog output --- use a DAC component

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 21

    Analog Peripheral: DFB

    Specs (continued): Coefficients automatically calculated Setting for filters can be made for 2

    channels Select type:

    Low Pass, Band Pass, High Pass, Notch

    Select implementation:FIR or IIR Biquad

    Specify sample rate Specify number of taps Select frequency parameters Select display:

    Spectrum, step (for low pass), tone response ( for band pass), pole-zero plot

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 22

    Review

    Objectives, you should now be able to: Understand analog in PSoC 3 / PSoC 5 Use and implement analog peripherals in PSoC Creator

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 23

    Lab 104:Working Mans O-Scope

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 24

    Lab Objectives

    Objectives: Generate signals with a VDAC Configure and use a DelSig ADC Use of ISRs to capture ADC values Display slow waveforms on a character LCD Experience the PSoC Creator Design Flow

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 25

    Step 1: Open Lab4_Scope.cywrk

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 26

    Step 2: Open TopDesign.cysch

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 27

    Step 3: Add/Configure Components

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 28

    Step 3: Add/Configure Components

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 29

    Step 4: Review Firmware

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 30

    Step 4: Review Firmware

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 31

    Step 4: Review Firmware

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 32

    Step 5: Modify ADC ISR Routine

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 33

    Step 5: Modify ADC ISR Routine

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 34

    Step 6: Configure PSoC I/O

  • Introduction to PSoC 3 / PSoC 5 Workshop Rev *F 35

    Step 7: Build/Program/Run