10/11/20051 Low voltage, scalable nanocrystal FLASH memory fabricated by templated self assembly ...

10/11/200510/11/2005 11

Low voltage, scalable nanocrystal FLASH Low voltage, scalable nanocrystal FLASH memory fabricated by templated self memory fabricated by templated self

assemblyassembly Presented by:Presented by:

Michael LogueMichael Logue Pierre EmeliePierre Emelie Zhuang WuZhuang Wu J.R. EdwardsJ.R. Edwards

10/11/200510/11/2005 22

OutlineOutline

Traditional Flash DevicesTraditional Flash Devices Introduction to Flash memoryIntroduction to Flash memory

Performances, Applications, LimitationsPerformances, Applications, Limitations

How to improve Flash memoryHow to improve Flash memory Nanocrystal Device fabricationNanocrystal Device fabrication Performance of Nanocrystal FLASH memoryPerformance of Nanocrystal FLASH memory

Emerging Nonvolatile Memory TechnologiesEmerging Nonvolatile Memory Technologies CBRAM, FeRAM, MRAM, ORAM, and PCRAMCBRAM, FeRAM, MRAM, ORAM, and PCRAM

Final ConclusionsFinal Conclusions

10/11/200510/11/2005 33

OutlineOutline






10/11/200510/11/2005 44

Introduction to Flash MemoryIntroduction to Flash Memory

Flash memory is a type of EEPROM chipFlash memory is a type of EEPROM chip EEPROM (Electrically Erasable EEPROM (Electrically Erasable

Programmable Read-Only Memory)Programmable Read-Only Memory) Flash memory chips don’t have to be removed Flash memory chips don’t have to be removed

from the circuit board and exposed to UV light to from the circuit board and exposed to UV light to be erasedbe erased

Flash memory is “non-volatile” memoryFlash memory is “non-volatile” memory Meaning that the data stored in memory is Meaning that the data stored in memory is

retained even when it is not being poweredretained even when it is not being powered

10/11/200510/11/2005 55

How Flash Memory WorksHow Flash Memory Works

A Flash chip has a grid of columns and A Flash chip has a grid of columns and rows with a cell that has two transistors rows with a cell that has two transistors at each intersectionat each intersection

The transistors are separated from each The transistors are separated from each other by a thin oxide layer. One is other by a thin oxide layer. One is known as the floating gate and the other known as the floating gate and the other is the control gate. is the control gate.

The floating gates only link to the row, or The floating gates only link to the row, or wordlinewordline, is through the control gate. As , is through the control gate. As long as this link is in place, the cell has long as this link is in place, the cell has a value of 1. To change the value to a 0 a value of 1. To change the value to a 0 requires a curious process called requires a curious process called Fowler-Nordheim tunnelingFowler-Nordheim tunneling..

Tunneling is used to alter the placement Tunneling is used to alter the placement of electrons in the floating gate.of electrons in the floating gate.

10/11/200510/11/2005 66

How Flash Memory WorksHow Flash Memory Works

Tunneling (continued)Tunneling (continued) An electrical charge, usually 10-13 V, is applied to the floating An electrical charge, usually 10-13 V, is applied to the floating

gate. The charge comes from the column, or bitline, enters the gate. The charge comes from the column, or bitline, enters the floating gate and drains to groundfloating gate and drains to ground

This charge causes the floating gate transistor to act like an This charge causes the floating gate transistor to act like an electron gun. The excited electrons are pushed through and electron gun. The excited electrons are pushed through and trapped on other side of the thin oxide layer, giving it a negative trapped on other side of the thin oxide layer, giving it a negative charge. These negatively charged electrons act as a barrier charge. These negatively charged electrons act as a barrier

between the control gate and the floating gate.between the control gate and the floating gate. If the flow through the gate is greater than 50 percent of the If the flow through the gate is greater than 50 percent of the

charge, it has a value of 1. When the charge passing through charge, it has a value of 1. When the charge passing through

drops below the 50-percent threshold, the value changes to 0.drops below the 50-percent threshold, the value changes to 0.

10/11/200510/11/2005 77

How Flash Memory WorksHow Flash Memory Works ErasingErasing

The electrons in the cells can be returned to normal ("1") by The electrons in the cells can be returned to normal ("1") by applying an electric field. Flash memory uses applying an electric field. Flash memory uses in-circuit wiringin-circuit wiring to apply the electric field either to the entire chip or to to apply the electric field either to the entire chip or to predetermined sections known as predetermined sections known as blocksblocks. Flash memory works . Flash memory works much faster than traditional EEPROMs because instead of much faster than traditional EEPROMs because instead of erasing one byte at a time, it erases a block or the entire chip, erasing one byte at a time, it erases a block or the entire chip,

and then rewrites it.and then rewrites it. Flash chips are made on silicon wafers using a process Flash chips are made on silicon wafers using a process

that takes 6-12 weeks and hundreds of manufacturing that takes 6-12 weeks and hundreds of manufacturing steps. The process requires multiple uses of steps. The process requires multiple uses of photolithography, etch, diffusion, thin film deposition, photolithography, etch, diffusion, thin film deposition, planarization, and ion implantation.planarization, and ion implantation. The width of the Control/Floating Gates will average between 12 The width of the Control/Floating Gates will average between 12

and 25nm, depending on the process technology and the density and 25nm, depending on the process technology and the density of the number of cells on a chip (measured in megabytes)of the number of cells on a chip (measured in megabytes)

10/11/200510/11/2005 88

Benefits of Flash MemoryBenefits of Flash Memory

Provides a shock insensitive, non-volatile Provides a shock insensitive, non-volatile form of data storage.form of data storage.

Has miniscule energy requirementsHas miniscule energy requirements Flash is small, light and relatively Flash is small, light and relatively

inexpensiveinexpensive Flash is noiseless, has no moving parts, Flash is noiseless, has no moving parts,

and allows faster access than a hard diskand allows faster access than a hard disk

10/11/200510/11/2005 99

Limitations of Flash memoryLimitations of Flash memory

Cost per megabyte of a hard disk is Cost per megabyte of a hard disk is drastically cheaper and capacity is drastically cheaper and capacity is substantially moresubstantially more

Tolerates a limited number of write cyclesTolerates a limited number of write cycles This is because electrical charges provide This is because electrical charges provide

permanent retention of transistor states. permanent retention of transistor states. These charges are isolated by oxide layers, These charges are isolated by oxide layers, which help maintain consistent state, but also which help maintain consistent state, but also dissipate over time.dissipate over time.

10/11/200510/11/2005 1010

Common Failure MechanismsCommon Failure Mechanisms Improperly specified speed ratings used in flash Improperly specified speed ratings used in flash

cardcard Poor interconnects and construction in cardPoor interconnects and construction in card Flash card connector failureFlash card connector failure Flash card structural failure due to excessive Flash card structural failure due to excessive

stressstress Inserting card and applying a voltage while the Inserting card and applying a voltage while the

card is wetcard is wet Tunnel oxide degradation-ultimate wear out Tunnel oxide degradation-ultimate wear out

mechanismmechanism Package interconnect failurePackage interconnect failure

10/11/200510/11/2005 1111

Types of Flash MemoryTypes of Flash Memory Cell TypesCell Types

The way the cells actually work depend on whether they are The way the cells actually work depend on whether they are NOR or NAND types. NOR flash is linearly addressable using a NOR or NAND types. NOR flash is linearly addressable using a conventional processor, and thus also works for delivering conventional processor, and thus also works for delivering executable code. However it’s slower than NAND, and requires executable code. However it’s slower than NAND, and requires more energy to read and write. It’s used primarily for burning more energy to read and write. It’s used primarily for burning and accessing programs in firmware. and accessing programs in firmware.

NAND also scales better than NOR, allowing for 4 and 8 GB NAND also scales better than NOR, allowing for 4 and 8 GB products, and works from a command-based bus interface. products, and works from a command-based bus interface. However memory controller overhead is higher and more However memory controller overhead is higher and more complex, and conventional processors require translation complex, and conventional processors require translation routines to enable them to read and write to NAND flash memoryroutines to enable them to read and write to NAND flash memory

Chip TypesChip Types Computers BIOS chip, SmartMedia, CompactFlash, Memory Computers BIOS chip, SmartMedia, CompactFlash, Memory

Stick, PCMCIA Type I and II, memory cards for video game Stick, PCMCIA Type I and II, memory cards for video game consolesconsoles

10/11/200510/11/2005 1212

ApplicationsApplications

Computer BIOS ChipComputer BIOS Chip Digital CamerasDigital Cameras AppliancesAppliances Video and stereo Video and stereo

equipmentequipment AutomobilesAutomobiles

10/11/200510/11/2005 1313

OutlineOutline






10/11/200510/11/2005 1414

Device Fabrication of Scalable Device Fabrication of Scalable Nanocrystal Flash MemoryNanocrystal Flash Memory

Silicon nanocrystals were defined using diblock Silicon nanocrystals were defined using diblock copolymer thin film self assemblycopolymer thin film self assembly Process involves spin-coating a dilute polymer Process involves spin-coating a dilute polymer

solution and annealing to promote phase separation solution and annealing to promote phase separation into nanometer-scale polymer domainsinto nanometer-scale polymer domains

The diblock copolymer was composed of polystyrene The diblock copolymer was composed of polystyrene (PS) and poly(methyl methacrylate) (PMMA). Their (PS) and poly(methyl methacrylate) (PMMA). Their molecular weight ratio produces hexagonally-closed-molecular weight ratio produces hexagonally-closed-packed PMMA cylinders in a PS matrix.packed PMMA cylinders in a PS matrix.

The PMMA is removed with an organic solvent, The PMMA is removed with an organic solvent, leaving a porous PS film. This film is used as a leaving a porous PS film. This film is used as a sacrificial layer to define nanocrystals at sub-sacrificial layer to define nanocrystals at sub-lithographic dimensions.lithographic dimensions.

10/11/200510/11/2005 1515


Fig 1-(a )form porous PS film on Fig 1-(a )form porous PS film on thermal oxide hardmask; (b) etch PS thermal oxide hardmask; (b) etch PS pattern onto oxide; (c) grow program pattern onto oxide; (c) grow program oxide (2-3nm) and conformally deposit oxide (2-3nm) and conformally deposit a:Si; (d) etch a:Si using an anisotropic a:Si; (d) etch a:Si using an anisotropic RIE processRIE process

The nanocrystals’ dimensions are the The nanocrystals’ dimensions are the same as the original polymer film, same as the original polymer film, 20nm(+/-10%), and a center-center 20nm(+/-10%), and a center-center spacing of 40nmspacing of 40nm

The nanocrystal density was found to The nanocrystal density was found to be 6.5*10be 6.5*101010/cm/cm22. Using polymers with . Using polymers with lower molecular weight can produce lower molecular weight can produce smaller dimensionssmaller dimensions

10/11/200510/11/2005 1616


The devices are The devices are completed by depositing completed by depositing a control oxide (7-12nm) a control oxide (7-12nm) on top of the nanocrystal on top of the nanocrystal array, then depositing, array, then depositing, doping and patterning the doping and patterning the polysilicon gate. A single polysilicon gate. A single metal layer is used to metal layer is used to contact the gate.contact the gate.

10/11/200510/11/2005 1717


10/11/200510/11/2005 1818

OutlineOutline






10/11/200510/11/2005 1919

Performance of Nanocrystal Performance of Nanocrystal FLASH memoryFLASH memory

““Writing”:Writing”: injection of charges into injection of charges into the nanocrystalsthe nanocrystals

““Erasing”:Erasing”: expelling charge from expelling charge from the nanocrystalsthe nanocrystals

High frequency CV measurements High frequency CV measurements are shown for device Eare shown for device E

Stored charge shifts the device flat Stored charge shifts the device flat band voltage Vband voltage VFBFB

VVW W = -4 V → = -4 V → ΔΔVVFB FB > 0.5 V> 0.5 V

Potentially low voltage operationPotentially low voltage operation

10/11/200510/11/2005 2020


Larger VLarger VFBFB shifts are achieved using shifts are achieved using

larger Vlarger VWW (read voltage -2 V and (read voltage -2 V and

write time of 20 s)write time of 20 s)

Magnitude and slope of Magnitude and slope of ΔΔVVFB FB

depend on:depend on:- program oxide thickness - program oxide thickness

ttprogprog - control oxide thickness t- control oxide thickness tctrlctrl

Control of the fabrication leads to Control of the fabrication leads to control of device performancecontrol of device performance

Control device F (with no Control device F (with no nanoctrystals) show no nanoctrystals) show no ΔΔVVFB FB at |Vat |VWW| |

< 9 V < 9 V

10/11/200510/11/2005 2121


At high |VAt high |VWW|, charge begins to leak |, charge begins to leak

through the control oxidethrough the control oxide

ΔΔVVFB FB saturates saturates

• Device breakdown is set by the Device breakdown is set by the control oxide thickness tcontrol oxide thickness tctrlctrl

Again, control of the fabrication Again, control of the fabrication leads to control of device leads to control of device performanceperformance

10/11/200510/11/2005 2222


Effect of the program oxide Effect of the program oxide thickness tthickness tprog prog (for fixed t(for fixed tctrlctrl) is shown ) is shown

on this figureon this figure

Devices with tDevices with tprogprog = 3 nm (C and D) = 3 nm (C and D)

show larger show larger ΔΔVVFB FB than tthan tprogprog = 2 nm = 2 nm

(A and B)(A and B) Due to the larger voltage on the Due to the larger voltage on the

floating gate for the same Vfloating gate for the same VWW

• ΔΔVVFB FB increases with write time for a increases with write time for a

fixed Vfixed VWW

• Write time of 50 µs → Write time of 50 µs → ΔΔVVFB FB ~ 0.2 V~ 0.2 V

• Devices are fully erased with a 100 Devices are fully erased with a 100 µs erase voltage pulse of +4 Vµs erase voltage pulse of +4 V

10/11/200510/11/2005 2323


Stability of the written and erased Stability of the written and erased memory states is measured on this memory states is measured on this figure (Vfigure (VWW = -6 V and V = -6 V and VEE = +4 V) = +4 V)

Small signal capacitance at -2 V is Small signal capacitance at -2 V is measured as a function of time and measured as a function of time and converted to converted to ΔΔVVFB FB by tracking along by tracking along

a CV curvea CV curve

Up to 500 s, Up to 500 s, ΔΔVVFB FB remained larger remained larger

for tfor tprogprog = 3nm (C and D) than for = 3nm (C and D) than for

ttprogprog = 2 nm (A and B) = 2 nm (A and B)

Logarithmic fit for A and B devices Logarithmic fit for A and B devices projects retention time > 10projects retention time > 1066 s s

10/11/200510/11/2005 2424


Device endurance is measured Device endurance is measured using (Vusing (VWW = -6 V, 50 µs) and = -6 V, 50 µs) and

(V(VEE = +4 V, 50 µs) = +4 V, 50 µs)

Read voltage of -2 VRead voltage of -2 V Write/erase window remains Write/erase window remains

unchanged out to unchanged out to 101099 cycles cycles

10/11/200510/11/2005 2525

Performance of Nanocrystal Performance of Nanocrystal FLASH memory - ConclusionFLASH memory - Conclusion

Charge is stored in small islands of Si rather than in a Charge is stored in small islands of Si rather than in a continuous floating gatecontinuous floating gate

Precise control of nanocrystal size and position can be Precise control of nanocrystal size and position can be achievedachieved

Control of the device fabrication (especially the dielectric Control of the device fabrication (especially the dielectric thickness) makes things easier in terms of thickness) makes things easier in terms of manufacturability, scalability and control of the device manufacturability, scalability and control of the device performanceperformance

Devices exhibit low voltage memory operation with Devices exhibit low voltage memory operation with promising retention and endurance propertiespromising retention and endurance properties

=> Nanocrystal FLASH memory may improve => Nanocrystal FLASH memory may improve reliabilityreliability in in FLASH devicesFLASH devices

10/11/200510/11/2005 2626

Performance of Nanocrystal Performance of Nanocrystal FLASH memory - LimitationsFLASH memory - Limitations

Nanocrystal storage does not change the transistor Nanocrystal storage does not change the transistor physics: it’s the same mechanism for read and writephysics: it’s the same mechanism for read and write

It does not solve all the problems associated with FLASH It does not solve all the problems associated with FLASH devices mentioned earlierdevices mentioned earlier

• It will probably not help FLASH memory scale to smaller It will probably not help FLASH memory scale to smaller geometriesgeometries

• It will probably never be used for FLASH memory It will probably never be used for FLASH memory devices but it shows a novel fabrication technique with devices but it shows a novel fabrication technique with promising applicationspromising applications

• FLASH memory will probably be replaced in the next ten FLASH memory will probably be replaced in the next ten years by other emerging non-volatile memory years by other emerging non-volatile memory technologiestechnologies

10/11/200510/11/2005 2727

OutlineOutline






10/11/200510/11/2005 2828

CBRAMCBRAMConductive Bridging RAMConductive Bridging RAM

10/11/200510/11/2005 2929

Basic principlesBasic principles

On/off states correspond to presence or On/off states correspond to presence or lack of a conductive bridge between lack of a conductive bridge between electrodes. electrodes.

Writing/erasing follows the formation and Writing/erasing follows the formation and removal of the bridge; removal of the bridge;

Reading is done by measuring resistance Reading is done by measuring resistance between electrodes.between electrodes.

10/11/200510/11/2005 3030

How to achieve the bridgesHow to achieve the bridges

a redox reaction drives metal ions in the a redox reaction drives metal ions in the chalcogenide glass forming metal-rich clusters chalcogenide glass forming metal-rich clusters that lead to a conductive bridge between the that lead to a conductive bridge between the electrodes. electrodes.

Writing voltage Writing voltage 250mV, writing current 250mV, writing current 2µA2µA

10/11/200510/11/2005 3131

How to remove a bridgeHow to remove a bridge

The memory element can be switched The memory element can be switched back to the OFF-state by applying a back to the OFF-state by applying a reverse bias voltage. In this case metal reverse bias voltage. In this case metal ions are removed and due to that size and ions are removed and due to that size and number of metal-rich clusters are reduced number of metal-rich clusters are reduced resulting in an erased conductive bridgeresulting in an erased conductive bridge

Here, the erasing voltage is -80mVHere, the erasing voltage is -80mV

10/11/200510/11/2005 3232

CBRAM cell resistance and threshold CBRAM cell resistance and threshold voltage as a function of storagevoltage as a function of storage

material area.material area.

10/11/200510/11/2005 3333

CBRAM data retention measured at CBRAM data retention measured at elevated temperatures.elevated temperatures.

10/11/200510/11/2005 3434

The Ferro-electric RAMThe Ferro-electric RAM

FRAM is an array of ferroelectric FRAM is an array of ferroelectric capacitors, with a thin ferroelectric film in capacitors, with a thin ferroelectric film in between, which is typically made of lead between, which is typically made of lead zirconate titanate (PZT). zirconate titanate (PZT).

10/11/200510/11/2005 3535

The bit is read by applying an electric field The bit is read by applying an electric field on the memory capacitor. The amount of on the memory capacitor. The amount of charge needed to flip the memory cell to charge needed to flip the memory cell to the opposite state is measured and the the opposite state is measured and the previous state of the cell is revealed. previous state of the cell is revealed.

10/11/200510/11/2005 3636

Re-write Re-write

The read operation destroys the memory The read operation destroys the memory cell state, and has to be followed by a cell state, and has to be followed by a corresponding write operation, in order to corresponding write operation, in order to write the bit back. write the bit back.

10/11/200510/11/2005 3737

Magneto-resistive RAMMagneto-resistive RAM

A cell is made up of three major partsA cell is made up of three major parts One of the two plates is a permanent magnet set One of the two plates is a permanent magnet set

to a particular polarity, the other's field will to a particular polarity, the other's field will change to match that of an external field change to match that of an external field

10/11/200510/11/2005 3838

Data is written to the cells by creating an Data is written to the cells by creating an induced magnetic field in a grid of write lines induced magnetic field in a grid of write lines above and below the cells above and below the cells

current creates an induced magnetic field, which current creates an induced magnetic field, which flips the polarity of the "writable" plate to match flips the polarity of the "writable" plate to match the induced field the induced field

if the two plates have the same polarity this is if the two plates have the same polarity this is considered to mean "0", while if the two plates considered to mean "0", while if the two plates are of opposite polarity the resistance will be are of opposite polarity the resistance will be higher and this means "1". higher and this means "1".

10/11/200510/11/2005 3939

By measuring the resistance along the By measuring the resistance along the read lines, the state (field) of any particular read lines, the state (field) of any particular cell can be determined cell can be determined

10/11/200510/11/2005 4040

OutlineOutline




Emerging Nonvolatile Memory TechnologiesEmerging Nonvolatile Memory Technologies CBRAM, FeRAM, MRAM, CBRAM, FeRAM, MRAM, ORAMORAM, and PCRAM, and PCRAM


10/11/200510/11/2005 4141

ORAMORAM

Organic Random Access MemoryOrganic Random Access Memory Reversible resistive operation by voltage applicationReversible resistive operation by voltage application

Requires boosted voltage for WRITE operationRequires boosted voltage for WRITE operation

10/11/200510/11/2005 4242

ORAM ScalingORAM Scaling

Resistance ratio Resistance ratio decrease with device decrease with device areaarea

Extrapolation indicates a Extrapolation indicates a resistance ratio of >10 at resistance ratio of >10 at 20x20nm20x20nm22

Switching voltages are Switching voltages are independent of device independent of device areaarea

10/11/200510/11/2005 4343

ORAM PerformanceORAM Performance

Promising distribution Promising distribution functions for threshold functions for threshold voltagevoltage

10/11/200510/11/2005 4444

OutlineOutline




Emerging Nonvolatile Memory TechnologiesEmerging Nonvolatile Memory Technologies CBRAM, FeRAM, MRAM, ORAM, and CBRAM, FeRAM, MRAM, ORAM, and PCRAMPCRAM


10/11/200510/11/2005 4545

PCRAMPCRAM

Phase Change Random Access Memory Phase Change Random Access Memory Chalcogenide glass (GeChalcogenide glass (GexxSbSbyyTeTezz))

Same material family as used in rewritable Same material family as used in rewritable CD/DVD disksCD/DVD disks

Rather than laser beam, uses current to heat Rather than laser beam, uses current to heat materialmaterial

10/11/200510/11/2005 4646

Basic PCRAM StructureBasic PCRAM Structure

10/11/200510/11/2005 4747

PCRAM CharacteristicsPCRAM Characteristics

Short, high current pulse Short, high current pulse to make amorphous state to make amorphous state (high resistance RESET (high resistance RESET state)state)

Longer, medium current Longer, medium current pulse to make pulse to make polycrystalline state (low polycrystalline state (low resistance SET state)resistance SET state)

Low current pulse to Low current pulse to differentiate state (READ differentiate state (READ state)state)

10/11/200510/11/2005 4848

PCRAM RESET PulsePCRAM RESET Pulse

Temperature of Temperature of programmed volume of programmed volume of phase-change material phase-change material exceeds the melting pointexceeds the melting point

Eliminates the Eliminates the polycrystalline orderingpolycrystalline ordering

Device quenches to Device quenches to “freeze in” the disordered “freeze in” the disordered structural statestructural state

Cho et al., http://www.epcos.org/pdf_2004/17paper_cho.pdf

10/11/200510/11/2005 4949

PCRAM SET PulsePCRAM SET Pulse

Temperature of Temperature of programmed volume programmed volume of phase-change of phase-change material maintained in material maintained in rapid crystallization rapid crystallization rangerange

Maintained for a Maintained for a sufficient time for sufficient time for crystal orderingcrystal ordering

10/11/200510/11/2005 5050

PCRAM READ PulsePCRAM READ Pulse

Low current pulse, Low current pulse, with essentially no with essentially no joule heatingjoule heating

Current used to sense Current used to sense resistanceresistance

10/11/200510/11/2005 5151

PCRAM ScalingPCRAM Scaling

10/11/200510/11/2005 5252

PCRAM ScalingPCRAM Scaling

Normalized radial Normalized radial temperature temperature distributiondistribution

Heat plume scaled Heat plume scaled down with device down with device diameterdiameter

10/11/200510/11/2005 5353

OutlineOutline






10/11/200510/11/2005 5454

ConclusionConclusion

10/11/20051 Low voltage, scalable nanocrystal FLASH memory fabricated by templated self assembly ...

Documents

Transcript of 10/11/20051 Low voltage, scalable nanocrystal FLASH memory fabricated by templated self assembly ...