1 Wire Command Set

7/30/2019 1 Wire Command Set

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1-Wire Command Set for iButton

1.0 iButton with ROM

1.1 DS1904

1.1.1 READ CLOCK [66h]The read clock command is used to read the device control byte and the contents of the real-time clockcounter. After having received the most significant bit of the command code the device copies theactual contents of the real-time clock counter to the read/write buffer. Now the bus master reads databeginning with the device control byte followed by the least significant byte through the most significantbyte of the real-time clock. After this the bus master may continue reading from the DS1904. The datareceived will be the same as in the first pass through the command flow. The read clock command canbe ended at any point by issuing a Reset Pulse.

1.1.2 WRITE CLOCK [99h]The write clock command is used to set the real-time clock counter and to write the device control byte.After issuing the command, the bus master writes first the device control byte, which becomesimmediately effective. After this the bus master sends the least significant byte through the most

significant byte to be written to the real-time clock counter. The new time data is copied from theread/write buffer to the real-time clock counter and becomes effective as the bus master generates areset pulse. If the oscillator is intentionally stopped, the real-time clock counter behaves as a four-bytenon-volatile memory.

1.1.3 Read ROM [33h]This command allows the bus master to read the DS1904s 8-bit family code, unique 48-bit serialnumber, and 8-bit CRC. This command should only be used if there is a single slave on the bus. If morethan one slave is present on the bus, a data collision will occur when all slaves try to transmit at thesame time (open drain will produce a wired-AND result). The resultant family code and 48-bit serialnumber read by the master will be invalid.

1.1.4 Match ROM [55h]

The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address aspecific DS1904 on a multidrop bus. Only the DS1904 that exactly matches the 64-bit ROM sequencewill respond to the following clock function command. All slaves that do not match the 64-bit ROMsequence will wait for a reset pulse. This command can be used with a single or multiple devices on thebus.

1.1.5 SEARCH ROM [F0h]When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use aprocess of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The searchROM process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit,then write the desired value of that bit. The bus master performs this 3-step routine on each bit of theROM. After one complete pass, the bus master knows the 64-bit ROM code of one device. Additional

passes will identify the ROM codes of the remaining devices. See Chapter 5 of the Book of DS19xxiButton Standards for a comprehensive discussion of a search ROM, including an actual example.

1.1.6 Skip ROM [CCh]This command can save time in a single drop bus system by allowing the bus master to access theclock functions without providing the 64-bit ROM code. If more than one slave is present on the busand, for example, a read command is issued following the Skip ROM command, data collision will occuron the bus as multiple slaves transmit simultaneously (open drain pull-downs will produce a wired-ANDresult).

1.1.7 Transaction SequenceThe protocol for accessing the DS1904 via the 1-Wire port is as follows:_ Initialization

_ ROM Function Command_ Clock Function Command


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1.2 DS1990

1.2.1 Read ROM [33h] or [0Fh]This command allows the bus master to read the DS1990As 8-bit family code, unique 48-bit serialnumber, and 8-bit CRC. This command can only be used if there is a single DS1990A on the bus. If

more than one slave is present on the bus, a data collision will occur when all slaves try to transmit atthe same time (open drain will produce a wired-AND result). The DS1990A Read ROM function willoccur with a command byte of either 33h or 0Fh in order to ensure compatibility with the DS1990, whichwill only respond to a 0Fh command word with its 64-bit ROM data.

1.2.2 Match ROM [55h] / Skip ROM [CCh]The complete 1-Wire protocol for all Dallas Semiconductor iButtons contains a Match ROM and a SkipROM command. (See the Book of DS19xx iButton Standards.) Since the DS1990A contains only the64- bit ROM with no additional data fields, the Match ROM and Skip ROM are not applicable and willcause no further activity on the 1-Wire bus if executed. The DS1990A does not interfere with other 1-Wire parts on a multidrop bus that do respond to a Match ROM or Skip ROM (example DS1990A andDS1994 on the same bus).

1.2.3 Search ROM [F0h]When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use aprocess of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROMsearch process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit,then write the desired value of that bit. The bus master performs this simple 3-step routine on each bitof the ROM. After one complete pass, the bus master knows the contents of the ROM in one device.The remaining number of devices and their ROM codes may be identified by additional passes. SeeChapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a ROM search,including an actual example.

1.2.4 TRANSACTION SEQUENCEThe sequence for accessing the DS1990A via the 1-Wire port is as follows:

_ Initialization_ ROM Function Command_ Read Data


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2.0 iButton with EROM

2.1 DS1982

2.1.1 READ MEMORY [F0h]The Read Memory command is used to read data from the 1024-bit EPROM data field. The bus master

follows the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a startingbyte location within the data field. An 8bit CRC of the command byte and address bytes is computedby the DS1982 and read back by the bus master to confirm that the correct command word and startingaddress were received. If the CRC read by the bus master is incorrect, a Reset Pulse must be issuedand the entire sequence must be repeated. If the CRC received by the bus master is correct, the busmaster issues read time slots and receives data from the DS1982 starting at the initial address andcontinuing until the end of the 1024-bit data field is reached or until a Reset Pulse is issued. If readingoccurs through the end of memory space, the bus master may issue eight additional read time slots andthe DS1982 will respond with an 8-bit CRC of all data bytes read from the initial starting byte throughthe last byte of memory. After the CRC is received by the bus master, any subsequent read time slotswill appear as logical 1s until a Reset Pulse is issued. Any reads ended by a Reset Pulse prior toreaching the end of memory will not have the 8-bit CRC available. Typically a 16-bit CRC would bestored with each page of data to ensure rapid, error-free data transfers that eliminate having to read a

page multiple times to determine if the received data is correct or not. (See Book of DS19xx iButtonStandards, Chapter 7 for the recommended file structure to be used with the 1-Wire environment.) IfCRC values are imbedded within the data, a Reset Pulse may be issued at the end of memory spaceduring a Read Memory command.

2.1.2 READ STATUS [AAh]The Read Status command is used to read data from the EPROM Status data field. The bus masterfollows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates astarting byte location within the data field. An 8bit CRC of the command byte and address bytes iscomputed by the DS1982 and read back by the bus master to confirm that the correct command wordand starting address were received. If the CRC read by the bus master is incorrect, a Reset Pulse mustbe issued and the entire sequence must be repeated. If the CRC received by the bus master is correct,the bus master issues read time slots and receives data from the DS1982 starting at the supplied

address and continuing until the end of the EPROM Status data field is reached. At that point the busmaster will receive an 8-bit CRC that is the result of shifting into the CRC generator all of the data bytesfrom the initial starting byte through the final factory-programmed byte that contains the 00h value.This feature is provided since the EPROM Status information may change over time making itimpossible to program the data once and include an accompanying CRC that will always be valid.Therefore, the Read Status command supplies an 8-bit CRC that is based on and always is consistentwith the current data stored in the EPROM Status data field. After the 8-bit CRC is read, the bus masterwill receive logical 1s from the DS1982 until a Reset Pulse is issued. The Read Status commandsequence can be exited at any point by issuing a Reset Pulse.

2.1.3 READ DATA/GENERATE 8-BIT CRC [C3h]The Read Data/Generate 8-bit CRC command is used to read data from the 1024-bit EPROM memoryfield. The bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8))

that indicates a starting byte location within the data field. An 8-bit CRC of the command byte andaddress bytes is computed by the DS1982 and read back by the bus master to confirm that the correctcommand word and starting address were received. If the CRC read by the bus master is incorrect, aReset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the busmaster is correct, the bus master issues read time slots and receives data from the DS1982 starting atthe initial address and continuing until the end of a 32-byte page is reached. At that point the busmaster will send eight additional read time slots and receive an 8-bit CRC that is the result of shiftinginto the CRC generator all of the data bytes from the initial starting byte to the last byte of the currentpage. Once the 8-bit CRC has been received, data is again read from the 1024-bit EPROM data fieldstarting at the next page. This sequence will continue until the final page and its accompanying CRCare read by the bus master. Thus each page of data can be considered to be 33 bytes long, the 32bytes of user-programmed EPROM data and an 8-bit CRC that gets generated automatically at the endof each page. This type of read differs from the Read Memory command which simply reads each page

until the end of address space is reached. The Read Memory command only generates an 8-bit CRC atthe end of memory space that often might be ignored, since in many applications the user would store a16-bit CRC with the data itself in each page of the 1024-bit EPROM data field at the time the page was


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programmed. The Read Data/Generate 8-bit CRC command provides an alternate read capability forapplications that are bit-oriented rather than page-oriented where the 1024-bit EPROM informationmay change over time within a page boundary, making it impossible to program the page once andinclude an accompanying CRC that will always be valid. Therefore, the Read Data/Generate 8-Bit CRCcommand concludes each page with the DS1982 generating and supplying an 8-bit CRC that is basedon and therefore is always consistent with the current data stored in each page of the 1024-bit EPROM

data field. After the 8-bit CRC of the last page is read, the bus master will receive logical 1s from theDS1982 until a Reset Pulse is issued. The Read Data/Generate 8-Bit CRC command sequence can beexited at any point by issuing a Reset Pulse.

2.1.4 WRITE MEMORY [0Fh]The Write Memory command is used to program the 1024bit EPROM data field. The bus master willfollow the command byte with a two byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte ofdata (D7:D0). An 8-bit CRC of the command byte, address bytes, and data byte is computed by theDS1982 and read back by the bus master to confirm that the correct command word, starting address,and data byte were received. The highest starting address within the DS1982 is 007FH. If the busmaster sends a starting address higher than this, the nine most significant address bits are set to 0 bythe internal circuitry of the chip. This will result in a mismatch between the CRC calculated by theDS1982 and the CRC calculated by the bus master, indicating an error condition. If the CRC read by

the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. Ifthe CRC received by the bus master is correct, a programming pulse (12 volts on the 1- Wire bus for480 s) is issued by the bus master. Prior to programming, the entire unprogrammed 1024-bit EPROMdata field will appear as logical 1s. For each bit in the data byte provided by the bus master that is set toa logical 0, the corresponding bit in the selected byte of the 1024bit EPROM will be programmed to alogical 0 after the programming pulse has been applied at that byte location. After the 480 sprogramming pulse is applied and the data line returns to a 5-volt level, the bus master issues eightread time slots to verify that the appropriate bits have been programmed. The DS1982 responds withthe data from the selected EPROM address sent least significant bit first. This byte contains the logicalAND of all bytes written to this EPROM data address. If the EPROM data byte contains 1s in bitpositions where the byte issued by the master contains 0s, a Reset Pulse should be issued and thecurrent byte address should be programmed again. If the DS1982 EPROM data byte contains 0s in thesame bit positions as the data byte, the programming was successful and the DS1982 will automatically

increment its address counter to select the next byte in the 1024-bit EPROM data field. The leastsignificant byte of the new 2-byte address will also be loaded into the 8-bit CRC generator as a startingvalue. The bus master will issue the next byte of data using eight write time slots. As the DS1982receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that hasbeen preloaded with the LSB of the current address, and the result is an 8-bit CRC of the new data byteand the LSB of the new address. After supplying the data byte, the bus master will read this 8-bit CRCfrom the DS1982 with eight read time slots to confirm that the address incremented properly and thedata byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the WriteMemory command sequence must be restarted. If the CRC is correct, the bus master will issue aprogramming pulse and the selected byte in memory will be programmed. Note that the initial passthrough the Write Memory flow chart will generate an 8-bit CRC value that is the result of shifting thecommand byte into the CRC generator, followed by the 2 address bytes, and finally the data byte.Subsequent passes through the Write Memory flow chart due to the DS1982 automatically incrementing

its address counter will generate an 8-bit CRC that is the result of loading (not shifting) the LSB of thenew (incremented) address into the CRC generator and then shifting in the new data byte. For both ofthese cases, the decision to continue (to apply a program pulse to the DS1982) is made entirely by thebus master, since the DS1982 will not be able to determine if the 8-bit CRC calculated by the busmaster agrees with the 8-bit CRC calculated by the DS1982. If an incorrect CRC is ignored and aprogram pulse is applied by the bus master, incorrect programming could occur within the DS1982.Also note that the DS1982 will always increment its internal address counter after the receipt of theeight read time slots used to confirm the programming of the selected EPROM byte. The decision tocontinue is again made entirely by the bus master; therefore if the EPROM data byte does not matchthe supplied data byte but the master continues with the Write Memory command, incorrectprogramming could occur within the DS1982. The Write Memory command sequence can be exited atany point by issuing a Reset Pulse.


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2.1.5 WRITE STATUS [55h]The Write Status command is used to program the EPROM Status data field. The bus master will followthe command byte with a 2-byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of statusdata (D7:D0). An 8-bit CRC of the command byte, address bytes, and data byte is computed by theDS1982 and read back by the bus master to confirm that the correct command word, starting address,

and data byte were received. If the CRC read by the bus master is incorrect, a Reset Pulse must beissued and the entire sequence must be repeated. If the CRC received by the bus master is correct, aprogramming pulse (12 volts on the 1-Wire bus for 480 s) is issued by the bus master. Prior toprogramming, the first 7 bytes of the EPROM Status data field will appear as logical 1s. For each bit inthe data byte provided by the bus master that is set to a logical 0, the corresponding bit in the selectedbyte of the EPROM Status data field will be programmed to a logical 0 after the programming pulse hasbeen applied at that byte location. The 8 th byte of the EPROM status byte data field is factory-programmed to contain 00h. After the 480 s programming pulse is applied and the data line returns toa 5-volt level, the bus master issues eight read time slots to verify that the appropriate bits have beenprogrammed. The DS1982 responds with the data from the selected EPROM Status address sent leastsignificant bit first. This byte contains the logical AND of all bytes written to this EPROM Status Byteaddress. If the EPROM Status Byte contains 1s in bit positions where the byte issued by the mastercontained 0s, a Reset Pulse should be issued and the current byte address should be programmed

again. If the DS1982 EPROM Status Byte contains 0s in the same bit positions as the data byte, theprogramming was successful and the DS1982 will automatically increment its address counter to selectthe next byte in the EPROM Status data field. The least significant byte of the new 2-byte address willalso be loaded into the 8-bit CRC generator as a starting value. The bus master will issue the next byteof data using eight write time slots. As the DS1982 receives this byte of data into the scratchpad, it alsoshifts the data into the CRC generator that has been preloaded with the LSB of the current address andthe result is an 8-bit CRC of the new data byte and the LSB of the new address. After supplying thedata byte, the bus master will read this 8-bit CRC from the DS1982 with eight read time slots to confirmthat the address incremented properly and the data byte was received correctly. If the CRC is incorrect,a Reset Pulse must be issued and the Write Status command sequence must be restarted. If the CRCis correct, the bus master will issue a programming pulse and the selected byte in memory will beprogrammed. Note that the initial pass through the Write Status flow chart will generate an 8-bit CRCvalue that is the result of shifting the command byte into the CRC generator, followed by the 2 address

bytes, and finally the data byte. Subsequent passes through the Write Status flow chart due to theDS1982 automatically incrementing its address counter will generate an 8-bit CRC that is the result ofloading (not shifting) the LSB of the new (incremented) address into the CRC generator and thenshifting in the new data byte. For both of these cases, the decision to continue (to apply a programpulse to the DS1982) is made entirely by the bus master, since the DS1982 will not be able todetermine if the 8-bit CRC calculated by the bus master agrees with the 8-bit CRC calculated by theDS1982. If an incorrect CRC is ignored and a program pulse is applied by the bus master, incorrectprogramming could occur within the DS1982. Also note that the DS1982 will always increment itsinternal address counter after the receipt of the eight read time slots used to confirm the programmingof the selected EPROM byte. The decision to continue is again made entirely by the bus master,therefore if the EPROM data byte does not match the supplied data byte but the master continues withthe Write Status command, incorrect programming could occur within the DS1982. The Write Statuscommand sequence can be ended at any point by issuing a Reset Pulse.

2.1.6 Read ROM [33h]This command allows the bus master to read the DS1982s 8-bit family code, unique 48-bit serialnumber, and 8-bit CRC. This command can be used only if there is a single DS1982 on the bus. If morethan one slave is present on the bus, a data collision will occur when all slaves try to transmit at thesame time (open drain will produce a wired-AND result).

2.1.7 Match ROM [55h]The match ROM command, followed by a 64bit ROM sequence, allows the bus master to address aspecific DS1982 on a multidrop bus. Only the DS1982 that exactly matches the 64-bit ROM sequencewill respond to the subsequent memory function command. All slaves that do not match the 64-bit ROMsequence will wait for a Reset Pulse. This command can be used with a single or multiple devices onthe bus.


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2.1.8 Skip ROM [CCh]This command can save time in a single-drop bus system by allowing the bus master to access thememory functions without providing the 64-bit ROM code. If more than one slave is present on the busand a read command is issued following the Skip ROM command, data collision will occur on the busas multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result).

2.1.9 Search ROM [F0h]When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use aprocess of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROMsearch process is the repetition of a simple, three-step routine: read a bit, read the complement of thebit, then write the desired value of that bit. The bus master performs this simple, three-step routine oneach bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in onedevice. The remaining number of devices and their ROM codes may be identified by additional passes.See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a ROMsearch, including an actual example.

2.1.10 TRANSACTION SEQUENCEThe sequence for accessing the DS1982 via the 1-Wire port is as follows:

_ Initialization_ ROM Function Command_ Memory Function Command_ Read/Write Memory/Status

2.2 DS1985

2.2.1 READ MEMORY [F0H]The Read Memory command is used to read data from the 16384-bits EPROM data field. The busmaster follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicatesa starting byte location within the data field. With every subsequent read data time slot the bus masterreceives data from the DS1985 starting at the initial address and continuing until the end of the 16384-

bits data field is reached or until a Reset Pulse is issued. If reading occurs through the end of memoryspace, the bus master may issue sixteen additional read time slots and the DS1985 will respond with a16-bit CRC of the command, address bytes and all data bytes read from the initial starting byte throughthe last byte of memory. This CRC is the result of clearing the CRC generator and then shifting in thecommand byte followed by the two address bytes and the data bytes beginning at the first addressedmemory location and continuing through to the last byte of the EPROM data memory. After the CRC isreceived by the bus master, any subsequent read time slots will appear as logical 1s until a Reset Pulseis issued. Any reads ended by a Reset Pulse prior to reaching the end of memory will not have the 16-bit CRC available. Typically a 16-bit CRC would be stored with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received datais correct or not. (See Book of DS19xx iButton Standards, Chapter 7 for the recommended file structureto be used with the 1-Wire environment.) If CRC values are imbedded within the data, a Reset Pulsemay be issued at the end of memory space during a Read Memory command.

2.2.2 READ STATUS [AAH]The Read Status command is used to read data from the EPROM Status data field. The bus masterfollows the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a startingbyte location within the data field. With every subsequent read data time slot the bus master receivesdata from the DS1985 starting at the supplied address and continuing until the end of an 8-byte page ofthe EPROM Status data field is reached. At that point the bus master will receive a 16-bit CRC of thecommand byte, address bytes and status data bytes. This CRC is computed by the DS1985 and readback by the bus master to check if the command word, starting address and data were receivedcorrectly. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entiresequence must be repeated. Note that the initial pass through the Read Status flow chart will generatea 16-bit CRC value that is the result of clearing the CRC generator and then shifting in the command

byte followed by the two address bytes, and finally the data bytes beginning at the first addressedmemory location and continuing through to the last byte of the addressed EPROM Status data page.The last byte of a Status data page always has an ending address of xx7 or xxFH. Subsequent passes


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through the Read Status flow chart will generate a 16-bit CRC that is the result of clearing the CRCgenerator and then shifting in the new data bytes starting at the first byte of the next page of theEPROM Status data field. This feature is provided since the EPROM Status information may changeover time making it impossible to program the data once and include an accompanying CRC that willalways be valid. Therefore, the Read Status command supplies a 16-bit CRC that is based on andalways is consistent with the current data stored in the EPROM Status data field. After the 16-bit CRC

of the last EPROM Status data page is read, the bus master will receive logical 1s from the DS1985until a Reset Pulse is issued. The Read Status command sequence can be ended at any point byissuing a Reset Pulse.

2.2.3 EXTENDED READ MEMORY [A5H]The Extended Read Memory command supports page redirection when reading data from the 16384-bitEPROM data field. One major difference between the Extended Read Memory and the basic ReadMemory command is that the bus master receives the Redirection Byte first before investing time inreading data from the addressed memory location. This allows the bus master to quickly decidewhether to continue and access the data at the selected starting page or to terminate and restart thereading process at the redirected page address. A non-redirected page is identified by a RedirectionByte with a value of FFH (see description of EPROM Status Bytes). If the Redirection Byte is differentthan this, the master has to complement it to obtain the new page number. Multiplying the page number

by 32 (20H) results in the new address the master has to send to the DS1985 to read the updated datareplacing the old data. There is no logical limitation in the number of redirections of any page. The onlylimit is the number of available memory pages within the DS1985. In addition to page redirection, theExtended Read Memory command also supports bit-oriented applications where the user cannot storea 16-bit CRC with the data itself. With bit-oriented applications the EPROM information may changeover time within a page boundary making it impossible to include an accompanying CRC that willalways be valid. Therefore, the Extended Read Memory command concludes each page with theDS1985 generating and supplying a 16-bit CRC that is based on and therefore always consistent withthe current data stored in each page of the 16384-bit EPROM data field. After having sent thecommand code of the Extended Read Memory command, the bus master follows the command bytewith a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within thedata field. By sending eight read data time slots, the master receives the Redirection Byte associatedwith the page given by the starting address. With the next sixteen read data time slots, the bus master

receives a 16-bit CRC of the command byte, address bytes and the Redirection Byte. This CRC iscomputed by the DS1985 and read back by the bus master to check if the command word, startingaddress and Redirection Byte were received correctly. If the CRC read by the bus master is incorrect, aReset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the busmaster is correct, the bus master issues read time slots and receives data from the DS1985 starting atthe initial address and continuing until the end of a 32-byte page is reached. At that point the busmaster will send 16 additional read time slots and receive a 16-bit CRC that is the result of shifting intothe CRC generator all of the data bytes from the initial starting byte to the last byte of the current page.With the next 24 read data time slots the master will receive the Redirection Byte of the next pagefollowed by a 16-bit CRC of the Redirection Byte. After this, data is again read from the 16384-bitEPROM data field starting at the beginning of the new page. This sequence will continue until the finalpage and its accompanying CRC are read by the bus master. The Extended Read Memory commandprovides a 16-bit CRC at two locations within the transaction flow chart: 1) after the Redirection Byte

and 2) at the end of each memory page. The CRC at the end of the memory page is always the resultof clearing the CRC generator and shifting in the data bytes beginning at the first addressed memorylocation of the EPROM data page until the last byte of this page. The CRC received by the bus masterdirectly following the Redirection Byte, is calculated in two different ways. With the initial pass throughthe Extended Read Memory flow chart the 16-bit CRC value is the result of shifting the command byteinto the cleared CRC generator, followed by the two address bytes and the Redirection Byte.Subsequent passes through the Extended Read Memory flow chart will generate a 16-bit CRC that isthe result of clearing the CRC generator and then shifting in the Redirection Byte only.

2.2.4 WRITE MEMORY [0FH]The Write Memory command is used to program the 16384bit EPROM data field. The bus master willfollow the command byte with a two byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte ofdata (D7:D0). A 16-bit CRC of the command byte, address bytes, and data byte is computed by the

DS1985 and read back by the bus master to confirm that the correct command word, starting address,and data byte were received. The highest starting address within the DS1985 is 07FFH. If the busmaster sends a starting address higher than this, the five most significant address bits are set to 0 by


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the internal circuitry of the chip. This will result in a mismatch between the CRC calculated by theDS1985 and the CRC calculated by the bus master, indicating an error condition. If the CRC read bythe bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. Ifthe CRC received by the bus master is correct, a programming pulse (12 volts on the 1-Wire bus for480 ms) is issued by the bus master. Prior to programming, the entire unprogrammed 16384-bitEPROM data field will appear as logical 1s. For each bit in the data byte provided by the bus master

that is set to a logical 0, the corresponding bit in the selected byte of the 16384-bit EPROM will beprogrammed to a logical 0 after the programming pulse has been applied at that byte location. After the480 ms programming pulse is applied and the data line returns to the idle level, the bus master issueseight read time slots to verify that the appropriate bits have been programmed. The DS1985 respondswith the data from the selected EPROM address sent least significant bit first. This byte contains thelogical AND of all bytes written to this EPROM data address. If the EPROM data byte contains 1s inbit positions where the byte issued by the master contained 0s, a Reset Pulse should be issued and thecurrent byte address should be programmed again. If the DS1985 EPROM data byte contains 0s in thesame bit positions as the data byte, the programming was successful and the DS1985 will automaticallyincrement its address counter to select the next byte in the 16384-bit EPROM data field. The new 2-byte address will also be loaded into the 16-bit CRC generator as a starting value. The bus master willissue the next byte of data using eight write time slots. As the DS1985 receives this byte of data into thescratchpad, it also shifts the data into the CRC generator that has been preloaded with the current

address and the result is a 16-bit CRC of the new data byte and the new address. After supplying thedata byte, the bus master will read this 16-bit CRC from the DS1985 with 16 read time slots to confirmthat the address incremented properly and the data byte was received correctly. If the CRC is incorrect,a Reset Pulse must be issued and the Write Memory command sequence must be restarted. If the CRCis correct, the bus master will issue a programming pulse and the selected byte in memory will beprogrammed. Note that the initial pass through the Write Memory flow chart will generate a 16-bit CRCvalue that is the result of shifting the command byte into the CRC generator, followed by the twoaddress bytes, and finally the data byte. Subsequent passes through the Write Memory flow chart dueto the DS1985 automatically incrementing its address counter will generate a 16-bit CRC that is theresult of loading (not shifting) the new (incremented) address into the CRC generator and then shiftingin the new data byte. For both of these cases, the decision to continue (to apply a Program Pulse to theDS1985) is made entirely by the bus master, since the DS1985 will not be able to determine if the 16-bitCRC calculated by the bus master agrees with the 16-bit CRC calculated by the DS1985. If an incorrect

CRC is ignored and a Program Pulse is applied by the bus master, incorrect programming could occurwithin the DS1985. Also note that the DS1985 will always increment its internal address counter afterthe receipt of the eight read time slots used to confirm the programming of the selected EPROM byte.The decision to continue is again made entirely by the bus master, therefore if the EPROM data bytedoes not match the supplied data byte but the master continues with the Write Memory command,incorrect programming could occur within the DS1985. The Write Memory command sequence can beended at any point by issuing a Reset Pulse. To save time when writing more than one consecutivebyte of the DS1985s data memory it is possible to omit reading the 16-bit CRC, which allowsverification of data and address before the data is copied to the EPROM memory. This saves 16 timeslots or 976 ms for every byte to be programmed. This speedprogramming mode is accessed with thecommand code F3H instead of 0FH. It follows basically the same flow chart as the Write Memorycommand, but skips sending the CRC immediately preceding the Program Pulse. This commandshould only be used if the electrical contact between bus master and the DS1985 is firm since a poor

contact may result in corrupted data inside the EPROM memory.

2.2.5 WRITE STATUS [55H]The Write Status command is used to program the EPROM Status data field. The bus master will followthe command byte with a 2-byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of statusdata (D7:D0). A 16-bit CRC of the command byte, address bytes, and data byte is computed by theDS1985 and read back by the bus master to confirm that the correct command word, starting address,and data byte were received. If the CRC read by the bus master is incorrect, a Reset Pulse must beissued and the entire sequence must be repeated. If the CRC received by the bus master is correct, aprogramming pulse (12 volts on the 1-Wire bus for 480 ms) is issued by the bus master. Prior toprogramming, the EPROM Status data field will appear as logical 1s. For each bit in the data byteprovided by the bus master that is set to a logical 0, the corresponding bit in the selected byte of theEPROM Status data field will be programmed to a logical 0 after the programming pulse has been

applied at that byte location. After the 480ms programming pulse is applied and the data line returns tothe idle level, the bus master issues eight read time slots to verify that the appropriate bits have beenprogrammed. The DS1985 responds with the data from the selected EPROM Status address sent least


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significant bit first. This byte contains the logical AND of all bytes written to this EPROM Status Byteaddress. If the EPROM Status Byte contains 1s in bit positions where the byte issued by the mastercontained 0s, a Reset Pulse should be issued and the current byte address should be programmedagain. If the DS1985 EPROM Status byte contains 0s in the same bit positions as the data byte, theprogramming was successful and the DS1985 will automatically increment its address counter to selectthe next byte in the EPROM Status data field. The new two-byte address will also be loaded into the 16-

bit CRC generator as a starting value. The bus master will issue the next byte of data using eight writetime slots. As the DS1985 receives this byte of data into the scratchpad, it also shifts the data into theCRC generator that has been preloaded with the current address, and the result is a 16-bit CRC of thenew data byte and the new address. After supplying the data byte, the bus master will read this 16-bitCRC from the DS1985 with 16 read time slots to confirm that the address incremented properly and thedata byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the WriteStatus command sequence must be restarted. If the CRC is correct, the bus master will issue aprogramming pulse and the selected byte in memory will be programmed. Note that the initial passthrough the Write Status flow chart will generate a 16-bit CRC value that is the result of shifting thecommand byte into the CRC generator, followed by the 2 address bytes, and finally the data byte.Subsequent passes through the Write Status flow chart due to the DS1985 automatically incrementingits address counter will generate a 16-bit CRC that is the result of loading (not shifting) the new(incremented) address into the CRC generator and then shifting in the new data byte. For both of these

cases, the decision to continue (to apply a Program Pulse to the DS1985) is made entirely by the busmaster, since the DS1985 will not be able to determine if the 16-bit CRC calculated by the bus masteragrees with the 16-bit CRC calculated by the DS1985. If an incorrect CRC is ignored and a ProgramPulse is applied by the bus master, incorrect programming could occur within the DS1985. Also notethat the DS1985 will always increment its internal address counter after the receipt of the eight readtime slots used to confirm the programming of the selected EPROM byte. The decision to continue isagain made entirely by the bus master, therefore if the EPROM data byte does not match the supplieddata byte but the master continues with the Write Status command, incorrect programming could occurwithin the DS1985. The Write Status command sequence can be ended at any point by issuing a ResetPulse. To save time when writing more than one consecutive byte of the DS1985s status memory it ispossible to omit reading the 16-bit CRC which allows verification of data and address before the data iscopied to the EPROM memory. This saves 16 time slots or 976 ms for every byte to be programmed.This speedprogramming mode is accessed with the command code F5H instead of 55H. It follows

basically the same flow chart as the Write Status command, but skips sending the CRC immediatelypreceding the Program Pulse. This command should only be used if the electrical contact between busmaster and the DS1985 is firm since a poor contact may result in corrupted data inside the EPROMstatus memory.

2.2.6 Read ROM [33H]This command allows the bus master to read the DS1985s 8-bit family code, unique 48-bit serialnumber, and 8-bit CRC. This command can be used only if there is a single DS1985 on the bus. If morethan one slave is present on the bus, a data collision will occur when all slaves try to transmit at thesame time (open drain will produce a wired-AND result).

2.2.7 Match ROM [55H]The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a

specific DS1985 on a multidrop bus. Only the DS1985 that exactly matches the 64-bit ROM sequencewill respond to the subsequent memory function command. All slaves that do not match the 64-bit ROMsequence will wait for a Reset Pulse. This command can be used with a single or multiple devices onthe bus.

2.2.8 Skip ROM [CCH]This command can save time in a single drop bus system by allowing the bus master to access thememory functions without providing the 64-bit ROM code. If more than one slave is present on the busand a read command is issued following the Skip ROM command, data collision will occur on the busas multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result).

2.2.9 Search ROM [F0H]When a system is initially brought up, the bus master might not know the number of devices on the 1-

Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use aprocess of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROMsearch process is the repetition of a simple three-step routine: read a bit, read the complement of the


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bit, then write the desired value of that bit. The bus master performs this simple, three-step routine oneach bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in onedevice. The remaining number of devices and their ROM codes may be identified by additional passes.See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a ROMsearch, including an actual example.

2.2.10 Transaction SequenceThe sequence for accessing the DS1985 via the 1-Wire port is as follows:_ Initialization_ ROM Function Command_ Memory Function Command_ Read/Write Memory/Status

2.3 DS1986

2.3.1 READ MEMORY [F0H]The Read Memory command is used to read data from the 65536-bits EPROM data field. The busmaster follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates

a starting byte location within the data field. With every subsequent read data time slot the bus masterreceives data from the DS1986 starting at the initial address and continuing until the end of the 65536-bits data field is reached or until a Reset Pulse is issued. If reading occurs through the end of memoryspace, the bus master may issue sixteen additional read time slots and the DS1986 will respond with a16-bit CRC of the command, address bytes and all data bytes read from the initial starting byte throughthe last byte of memory. This CRC is the result of clearing the CRC generator and then shifting in thecommand byte followed by the two address bytes and the data bytes beginning at the first addressedmemory location and continuing through to the last byte of the EPROM data memory. After the CRC isreceived by the bus master, any subsequent read time slots will appear as logical 1s until a Reset Pulseis issued. Any reads ended by a Reset Pulse prior to reaching the end of memory will not have the 16-bit CRC available. Typically a 16-bit CRC would be stored with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received datais correct or not. (See Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure

to be used with the 1-Wire environment.) If CRC values are imbedded within the data, a Reset Pulsemay be issued at the end of memory space during a Read Memory command.

2.3.2 READ STATUS [AAH]The Read Status command is used to read data from the EPROM Status data field. The bus masterfollows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates astarting byte location within the data field. With every subsequent read data time slot the bus masterreceives data from the DS1986 starting at the supplied address and continuing until the end of aneightbyte page of the EPROM Status data field is reached. At that point the bus master will receive a16-bit CRC of the command byte, address bytes and status data bytes. This CRC is computed by theDS1986 and read back by the bus master to check if the command word, starting address and datawere received correctly. If the CRC read by the bus master is incorrect, a Reset Pulse must be issuedand the entire sequence must be repeated. Note that the initial pass through the Read Status flow chart

will generate a 16-bit CRC value that is the result of clearing the CRC generator and then shifting in thecommand byte followed by the two address bytes, and finally the data bytes beginning at the firstaddressed memory location and continuing through to the last byte of the addressed EPROM Statusdata page. The last byte of a Status data page always has an ending address of xx7 or xxFH.Subsequent passes through the Read Status flow chart will generate a 16-bit CRC that is the result ofclearing the CRC generator and then shifting in the new data bytes starting at the first byte of the nextpage of the EPROM Status data field. This feature is provided since the EPROM Status informationmay change over time making it impossible to program the data once and include an accompanyingCRC that will always be valid. Therefore, the Read Status command supplies a 16-bit CRC that isbased on and always is consistent with the current data stored in the EPROM Status data field. Afterthe 16-bit CRC of the last EPROM Status data page is read, the bus master will receive logical 1sfrom the DS1986 until a Reset Pulse is issued. The Read Status command sequence can be ended atany point by issuing a Reset Pulse.


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2.2.3 EXTENDED READ MEMORY [A5H]The Extended Read Memory command supports page redirection when reading data from the 65536-bitEPROM data field. One major difference between the Extended Read Memory and the basic ReadMemory command is that the bus master receives the Redirection Byte first before investing time inreading data from the addressed memory location. This allows the bus master to quickly decidewhether to continue and access the data at the selected starting page or to terminate and restart the

reading process at the redirected page address. A non-redirected page is identified by a RedirectionByte with a value of FFH (see description of EPROM Status Bytes). If the Redirection Byte is differentthan this, the master has to complement it to obtain the new page number. Multiplying the page numberby 32 (20H) results in the new address the master has to send to the DS1986 to read the updated datareplacing the old data. There is no logical limitation in the number of redirections of any page. The onlylimit is the number of available memory pages within the DS1986. In addition to page redirection, theExtended Read Memory command also supports bit-oriented applications where the user cannot storea 16-bit CRC with the data itself. With bit-oriented applications the EPROM information may changeover time within a page boundary making it impossible to include an accompanying CRC that willalways be valid. Therefore, the Extended Read Memory command concludes each page with theDS1986 generating and supplying a 16-bit CRC that is based on and therefore always consistent withthe current data stored in each page of the 65536-bit EPROM data field. After having sent thecommand code of the Extended Read Memory command, the bus master follows the command byte

with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within thedata field. By sending eight read data time slots, the master receives the Redirection Byte associatedwith the page given by the starting address. With the next sixteen read data time slots, the bus masterreceives a 16-bit CRC of the command byte, address bytes and the Redirection Byte. This CRC iscomputed by the DS1986 and read back by the bus master to check if the command word, startingaddress and Redirection Byte were received correctly. If the CRC read by the bus master is incorrect, aReset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the busmaster is correct, the bus master issues read time slots and receives data from the DS1986 starting atthe initial address and continuing until the end of a 32-byte page is reached. At that point the busmaster will send sixteen additional read time slots and receive a 16- bit CRC that is the result of shiftinginto the CRC generator all of the data bytes from the initial starting byte to the last byte of the currentpage. With the next 24 read data time slots the master will receive the Redirection Byte of the next pagefollowed by a 16-bit CRC of the Redirection Byte. After this, data is again read from the 65536-bit

EPROM data field starting at the beginning of the new page. This sequence will continue until the finalpage and its accompanying CRC are read by the bus master. The Extended Read Memory commandprovides a 16-bit CRC at two locations within the transaction flow chart: 1) after the Redirection Byteand 2) at the end of each memory page. The CRC at the end of the memory page is always the resultof clearing the CRC generator and shifting in the data bytes beginning at the first addressed memorylocation of the EPROM data page until the last byte of this page. With the initial pass through theExtended Read Memory flow chart the 16-bit CRC value is the result of shifting the command byte intothe cleared CRC generator, followed by the two address bytes and the Redirection Byte. Subsequentpasses through the Extended Read Memory flow chart will generate a 16-bit CRC that is the result ofclearing the CRC generator and then shifting in the Redirection Byte only. fter the 16-bit CRC of the lastpage is read, the bus master will receive logical 1s from the DS1986 until a Reset Pulse is issued. TheExtended Read Memory command sequence can be exited at any point by issuing a Reset Pulse.

2.2.4 WRITE MEMORY [0FH]/SPEED WRITE MEMORY [F3H]The Write Memory command is used to program the 65536-bit EPROM data field. The details of thefunctional flow chart are described in the section WRITING EPROM MEMORY. The data memoryaddress range is 0000H to 1FFFH. If the bus master sends a starting address higher thanthis, the three most significant address bits are set to zeros by the internal circuitry of the chip. This willresult in a mismatch between the CRC calculated by the DS1986 and the CRC calculated by the busmaster, indicating an error condition. To save time when writing more than one consecutive byte of theDS1986s data memory it is possible to omit reading the 16-bit CRC which allows verification of dataand address before the data is copied to the EPROM memory. At regular speed this saves 16 time slotsor 976 s for every byte to be programmed. This speed programming mode is accessed with thecommand code F3H instead of 0FH. It follows basically the same flow chart as the Write Memorycommand, but skips sending the CRC immediately preceding the program pulse. This command shouldonly be used if the electrical contact between bus master and the DS1986 is firm since a poor contact

may result in corrupted data inside the EPROM memory.


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2.2.5 WRITE STATUS [55H]/ SPEED WRITE STATUS [F5H]The Write Status command is used to program the 2816-bit EPROM Status Memory field. The details ofthe functional flow chart are described in the section WRITING EPROM MEMORY. The StatusMemory address range is 0000H to 01FFH. Attempts to write to the not implemented status memorylocations will be ignored. If the bus master sends a starting address higher than 1FFFH, the three mostsignificant address bits are set to zeros by the internal circuitry of the chip. This will result in a mismatch

between the CRC calculated by the DS1986 and the CRC calculated by the bus master, indicating anerror condition. To save time when writing more than one consecutive byte of the DS1986s statusmemory it is possible to omit reading the 16-bit CRC which allows verification of data and addressbefore the data is copied to the EPROM memory. At regular speed this saves 16 time slots or 976 sfor every byte to be programmed. This speed-programming mode is accessed with the command codeF5H instead of 55H. It follows basically the same flow chart as the Write Status command, but skipssending the CRC immediately preceding the program pulse. This command should only be used if theelectrical contact between bus master and the DS1986 is firm since a poor contact may result incorrupted data inside the EPROM status memory.

2.2.6 Read ROM [33H]This command allows the bus master to read the DS1986s 8-bit family code, unique 48-bit serialnumber, and 8-bit CRC. This command can be used only if there is a single DS1986 on the bus. If more

than one slave is present on the bus, a data collision will occur when all slaves try to transmit at thesame time (open drain will produce a wired-AND result). The resultant family code and 48-bit serialnumber will usually result in a mismatch of the CRC.

2.2.8 Match ROM [55H]The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address aspecific DS1986 on a multidrop bus. Only the DS1986 that exactly matches the 64-bit ROM sequencewill respond to the subsequent memory function command. All slaves that do not match the 64-bit ROMsequence will wait for a reset pulse. This command can be used with a single or multiple devices on thebus.

2.2.9 Skip ROM [CCH]This command can save time in a single drop bus system by allowing the bus master to access the

memory functions without providing the 64-bit ROM code. If more than one slave is present on the busand a read command is issued following the Skip ROM command, data collision will occur on the busas multiple slaves transmit simultaneously (open drain pull-downs will produce a wired-AND result).

2.2.10 Search ROM [F0H]When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use aprocess of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROMsearch process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit,then write the desired value of that bit. The bus master performs this simple, 3-step routine on each bitof the ROM. After one complete pass, the bus master knows the contents of the ROM in one device.The remaining number of devices and their ROM codes may be identified by additional passes. SeeChapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a ROM search,

including an actual example.

2.2.11 Overdrive Skip ROM [3CH]On a single-drop bus this command can save time by allowing the bus master to access the memoryfunctions without providing the 64-bit ROM code. Unlike the normal Skip ROM command the OverdriveSkip ROM sets the DS1986 in the Overdrive Mode (OD=1). All communication following this commandhas to occur at Overdrive Speed until a reset pulse of minimum 480 s duration resets all devices onthe bus to regular speed (OD=0). When issued on a multidrop bus this command will set all Overdrive-capable devices into Overdrive mode. To subsequently address a specific Overdrive-capable device, areset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM commandsequence. This will shorten the time for the search process. If more than one slave supportingOverdrive is present on the bus and the overdrive Skip ROM command is followed by a read command,data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pull-downs

will produce a wired-AND result).


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2.2.12 Overdrive Match ROM [69H]The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at OverdriveSpeed, allows the bus master to address a specific DS1986 on a multidrop bus and to simultaneouslyset it in Overdrive Mode. Only the DS1986 that exactly matches the 64-bit ROM sequence will respondto the subsequent memory function command. Slaves already in Overdrive mode from a previousOverdrive Skip or Match command will remain in Overdrive mode. All other slaves that do not match the

64-bit ROM sequence or do not support Overdrive will return to or remain at regular speed and wait fora reset pulse of minimum 480 s duration. The Overdrive Match ROM command can be used with asingle or multiple devices on the bus.

2.2.13 Transaction SequenceThe sequence for accessing the DS1986 via the 1-Wire port is as follows:_ Initialization_ ROM Function Command_ Memory Function Command_ Read/Write Memory/Status

3.0 iButton with EEROM

3.1 DS1920

3.1.1 Read ROM [33h]This command allows the bus master to read the DS1920s 8-bit family code, unique 48-bit serialnumber, and 8-bit CRC. This command can only be used if there is a single DS1920 on the bus. If morethan one slave is present on the bus, a data collision will occur when all slaves try to transmit at thesame time (open drain will produce a wired AND result).

3.1.2 Match ROM [55h]The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address aspecific DS1920 on a multidrop bus. Only the DS1920 that exactly matches the 64-bit ROM sequencewill respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM

sequence will wait for a reset pulse. This command can be used with a single or multiple devices on thebus.

3.1.3 Skip ROM [CCh]This command can save time in a single drop bus system by allowing the bus master to access thememory functions without providing the 64-bit ROM code. If more than one slave is present on the busand a read command is issued following the Skip ROM command, data collision will occur on the busas multiple slaves transmit simultaneously (open drain pulldowns will produce a wired AND result). TheSkip ROM command is useful to address all DS1920s on the bus to do a temperature conversion. Sincethe DS1920 uses a special command set, other device types will not respond to these commands.

3.1.4 Search ROM [F0h]When a system is initially brought up, the bus master might not know the number of devices on the 1-

Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use aprocess of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROMsearch process is the repetition of a simple, three-step routine: read a bit, read the complement of thebit, then write the desired value of that bit. The bus master performs this simple, three-step routine oneach bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in onedevice. The remaining number of devices and their ROM codes may be identified by additional passes.See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a ROMSearch, including an actual example.

3.1.5 Alarm Search [ECh]The flowchart of this command is identical to the Search ROM command; however, the DS1920 willrespond to this command only if an alarm condition has been encountered at the last temperaturemeasurement. An alarm condition is defined as a temperature higher than TH or lower than TL. The

alarm condition remains set as long as the DS1920 is powered up or until another temperature


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measurement reveals a non-alarming value. For alarming, the trigger values stored in EEPROM aretaken into account. If an alarm condition exists and the TH or TL settings are changed, anothertemperature conversion should be done to validate any alarm conditions.

3.1.6 Write Scratchpad [4Eh]This command writes to the scratchpad of the DS1920, starting at address 2. The next 2 bytes written

will be saved in scratchpad memory, at address locations 2 and 3. Writing may be terminated at anypoint by issuing a reset. However, if a reset occurs before both bytes have been completely sent, thecontents of these bytes will be indeterminate. Bytes 2 and 3 can be read and written; all other bytes areread only.

3.1.7 Read Scratchpad [BEh]This command reads the complete scratchpad. After the last byte of the scratchpad is read, the busmaster will receive an 8-bit CRC of all scratchpad bytes. If not all locations are to be read, the mastermay issue a reset to terminate reading at any time.

3.1.8 Copy Scratchpad [48h]This command copies from the scratchpad into the EEPROM of the DS1920, storing the temperaturetrigger bytes in nonvolatile memory. The bus master has to enable a strong pullup for at least 10 ms

immediately after issuing this command.

3.1.9 Convert Temperature [44h]This command begins a temperature conversion. No further data is required. The bus master has toenable a strong pullup for 0.5 seconds immediately after issuing this command.

3.1.10 Recall [B8h]This command recalls the temperature trigger values stored in EEPROM to the scratchpad. This recalloperation happens automatically upon power-up to the DS1920 as well, so valid data is available in thescratchpad as soon as the device has power applied.

3.1.11 TRANSACTION SEQUENCEThe protocol for accessing the DS1920 via the 1-Wire port is as follows:

_ Initialization_ ROM Function Command_ Memory/Control Function Command_ Transaction/Data

3.2 DS1961

3.2.1 Write Scratchpad [0Fh]The write scratchpad command applies to the data memory, the secret and the writeable addresses inthe register page. If the bus master sends a target address higher than 90h, the command is notexecuted. After issuing the write scratchpad command, the master must first provide the 2-byte targetaddress, followed by the data to be written to the scratchpad. The data is written to the scratchpad

starting at the beginning of the scratchpad. Note that the ending offset is always 111b regardless of thenumber of bytes that the master has transmitted. For this reason the master should always send eightbytes, especially if the data is to be loaded as a secret. If the master sends less than eight data bytesand does not read back the scratchpad for verification, parts of the new secret can be random data thatis unknown to the master. Only full data bytes are accepted. If the last data byte is incomplete itscontent is ignored and the partial byte flag (PF) is set. When executing the write scratchpad commandthe CRC generator inside the DS1961S (see Figure 12) calculates a CRC of the entire data stream,starting at the command code and ending at the last data byte as sent by the master. This CRC isgenerated using the CRC16 polynomial by first clearing the CRC generator and then shifting in thecommand code (0Fh) of the write scratchpad command, the target addresses (TA1 and TA2), and allthe data bytes. Note that the CRC16 calculation is performed with the actual TA1 sent by the mastereven though the DS1961S sets TA1 bits T2..T0 to 000b for the actual write scratchpad command. Themaster can end the write scratchpad command at any time. However, if the scratchpad is filled to its

capacity, the master can send 16 read-time slots and receives the CRC generated by the DS1961S. Ifthe master continues reading after the CRC all data is be FFh. After receiving the target addresses(TA1 and TA2), the DS1961S clears the EN_LFS flag. If EPROM mode is active and a write scratchpad


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is attempted within page 1 (0020h003Fh), the scratchpad is loaded with the logical AND of thescratchpad data sent by the master and the current content of the target memory location. If a writescratchpad is attempted to the register page (0088h008Fh), any bytes that are write-protectedoverwrite the corresponding scratchpad data byte sent by the master with the existing value. In all othercases, the data sent by the master is written to the scratchpad unaltered.

3.2.2 Read Scratchpad [AAh]The read scratchpad command allows verifying the target address and the integrity of the scratchpaddata. After issuing the command code, the master begins reading. The first two bytes is the targetaddress with T2 to T0 = 0. The next byte is the ending offset/data status byte (E/S) followed by thescratchpad data, which may be different from what the master has originally sent. This is of particularimportance if the target address is the secret, the register page, page 1 (in EPROM mode), or if refreshwas used to load the scratchpad. In these cases, the scratchpad can contain data other than that whichwas sent during either the write scratchpad or refresh scratchpad commands. The master should readthrough the end of the scratchpad after which it receives the inverted CRC that is computed with thedata as sent by the DS1961S. If the master continues reading after the CRC all data is FFh. Thescratchpad can be loaded using the write scratchpad or refresh scratchpad command. The data foundin the scratchpad depends on the command used, the target address, and whether or not EPROMmode is active. See the descriptions of write scratchpad and refresh scratchpad for clarification.

3.2.3 Load First Secret [5Ah]The load first secret command has two modes of operation, which are controlled by the EN_LFS flag.With EN_LFS = 0, the command replaces the devices current secret with the contents of thescratchpad, provided that the secret is not write-protected. With EN_LFS = 1, the command allows torewrite memory data (addresses 0000h to 007Fh), bypassing the SHA-1 computation that is requiredwhen doing the same through the copy scratchpad command. The EN_LFS flag is 0 unless it has beenset to 1 by executing the refresh scratchpad command prior to load first secret.

3.2.3.1 Case EN_LFS = 0Before the load first secret command can be used in this mode, the master must have written the newsecret to the scratchpad using the starting address of the secret (0080h). After issuing the load firstsecret command, the master must provide a 3-byte authorization pattern (TA1, TA2, E/S, in that order),

that should have been obtained by an immediately preceding read scratchpad command. This 3-bytepattern must exactly match the data contained in the three address registers (see Figure 6). If thepattern matches and the secret is not write-protected, the AA flag is set and the copy begins. All eightbytes of scratchpad contents are copied to the secrets memory location.

3.2.3.2 Case EN_LFS = 1To use the load first secret command in this mode, the refresh scratchpad command must have beenexecuted to load eight bytes of memory data (address range 0000h to 007Fh) into the scratchpad,which sets the EN_LFS flag to 1. After issuing the load first secret command, the master must provide a3-byte authorization pattern (TA1, TA2, E/S, in that order), that can be obtained by an immediatelypreceding read scratchpad command without affecting the EN_LFS flag. This 3-byte pattern mustexactly match the data contained in the three address registers (see Figure 6). If the pattern matchesand the memory is not write-protected, the AA flag is set and the copy begins. All eight bytes of

scratchpad contents are copied to the memory location. Regardless of the mode used, the duration ofthe copy operation is tPROG during which the voltage on the 1-Wire bus must not fall below 2.8V. Themaster should read at least one byte at the conclusion of the copy delay. Reading AAh indicates thatthe copy was successful, while reading FFh indicates that the copy was not successful. Instead of usingload first secret with EN_LFS = 0, a new secret can alternatively be loaded with the copy scratchpadcommand. However, this approach requires the knowledge of the current secret and the computation ofa 160-bit MAC.

3.2.4 Compute Next Secret [33h]Some applications may require a higher level of security than can be achieved by a single, directlywritten secret. For additional security the DS1961S can compute a new secret based on the currentsecret, the contents of a selected memory page, and a partial secret that consists of all data in thescratchpad. To install a computed secret the master issues the compute next secret command, which

activates the 512-bit SHA-1 engine, provided that the secret is not write-protected. Table 1 shows howthe various data components involved enter the SHA engine and how a portion of the SHA result isloaded into the secret's memory location. The SHA computation algorithm itself is explained later in this


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document. The compute next secret command can be applied as often as desired to increase the levelof security. The bus master does not need to know the devices current secret in order to successfullycompute a new one and then overwrite the existing secret. After issuing the compute next secretcommand the master must provide a 2-byte target address to select the memory page that contributes256 bits of the SHA input data. After receiving the target addresses (TA1 and TA2), the DS1961S clearsthe EN_LFS flag. The lower five bits of the target address TA1 are ignored because only the page

number is relevant. If the target address as sent by the master is valid (i.e., in the range of 0000h and007Fh), and the secret is not write-protected, the SHA engine starts. The master must wait for tCSHAduring which the new secret is computed. Immediately following the SHA delay, the master must waitfor tPROG during which the new secret is copied to the secret register. During the tCSHA and tPROGthe voltage on the 1-Wire bus must not fall below 2.8V. The DS1961S fills the scratchpad with AAh ifthe copy was successful, but does not modify the scratchpad if the SHA engine did not start because ofan incorrect address or because of write protection. The master should read at least one byte at theconclusion of the copy delay. Reading AAh indicates that the copy was successful. Reading FFhindicates that the copy was not successful because of an incorrect address or because of writeprotection. Since the content of the scratchpad is used as a partial secret, the master must fill thescratchpad with a known 8-byte data pattern using the write scratchpad command before it issues thecompute next secret command. Otherwise the new secret depends on data that was unintentionally leftin the scratchpad from previous commands.

3.2.5 Copy Scratchpad [55h]The data memory of the DS1961S can be read without any restrictions. Executing the copy scratchpadcommand to write new data to the memory or register page, however, requires the knowledge of thedevices secret and the ability to perform an SHA-1 computation to generate the 160-bit MAC to startthe data transfer from the scratchpad to the memory. The master can perform the MAC computation insoftware or use a DS1963S as a coprocessor. The coprocessor approach has the benefit that thesecret remains hidden in the coprocessor iButton. The sequence in which the resulting MAC needs tobe sent to the DS1961S is shown in Table 2. Tables 3A and 3B show how the various data componentsare entered into the SHA engine. The SHA computation algorithm is explained later in this document.After issuing the copy scratchpad command, the master must provide a 3-byte authorization pattern,which should have been obtained by an immediately preceding read scratchpad command. This 3-bytepattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that

order). If the authorization code matches and the target memory is not write-protected, the DS1961Sstarts its SHA engine to compute a 160-bit MAC that is based on the current secret, all of thescratchpad data, the first 28 bytes of the addressed memory page, and the first seven bytes of theidentity register (the byte at address 0097h is not used; see Table 3A). The duration of this computationis tCSHA, during which the voltage on the 1-Wire line must not drop below 2.8V. Simultaneously themaster computes a MAC from the same data and, after tCSHA is expired, sends it to the DS1961S asevidence that it is authorized to write to the EEPROM. Now the master waits for tPROG during whichthe voltage on the 1-Wire bus must not fall below 2.8V. If the MAC generated by the DS1961S matchesthe MAC that the master computed, the DS1961S sets its AA flag, and copy the entire scratchpadcontents to the data EEPROM. The master should read at least one byte at the conclusion of the copydelay. Reading AAh indicates that the copy was successful. Reading 00h indicates that the copy wasnot successful because the computed MAC did not match the MAC sent by the master. Reading FFhindicates that the copy was not successful because of write protection or because of an incorrect

authorization pattern. Special attention is required when copying data to the register page. In order toprevent unintentional locking of a special function register or user byte it is recommended to first readthe register page and then write it with all intended modifications to the scratchpad. When copying datato the register page (or the secret using copy scratchpad), the input data for M1 to M7 of the SHAengine is the current secret (M1, M2), the current content of the register page (M3, M4), the full contentof the identity register (M5, M6), and 4 bytes FFh (M7), as shown in Table 3B. As a consequence, whenusing a DS1963S as coprocessor to compute the MAC to transfer data from the scratchpad to theregister page, the secret must be used as page data. This precludes the use of partial (computed)secrets if writing to the register page is required. For practical use of the DS1961S as a monetary token,partial secrets are more critical than being able to write-protect the secret or other areas of the device.

3.2.6 Read Authenticated Page [A5h]The read authenticated page command provides the master with the data of a full or partial memory

page plus a MAC. The MAC allows the master to determine whether the secret stored in the DS1961Sis valid within the application. The DS1961S computes the MAC from its secret, all the data of theselected memory page, the first seven bytes of the identity register and a 3-byte challenge, which the


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master should write to the scratchpad prior to issuing the read authenticated page command. To dothis, the master can use the write scratchpad command with any target address within the datamemory. Therelevant portions of the challenge are the 5th, 6th, and 7th bytes. Alternatively, the master can acceptthe data that happens to reside in the scratchpad from a previous command as a challenge. The 160-bitMAC is transmitted in the same way as with the copy scratchpad command, Table 2, but the data flows

from the DS1961S to the master. The data input to the SHA engine as it applies to the readauthenticated page command is shown in Table 4. After the master has issued the command code andspecified the target addresses (TA1 and TA2), the DS1961S first clears the EN_LFS flag. If the targetaddress is valid (< 0080h), the master receives the page data beginning at the target address throughthe end of the data page, one byte FFh and the inverted CRC of the command code, target address,transmitted page data and FFh byte. If the target address is invalid (_ 0080h), the master receives FFhbytes rather than page data. Immediately after the CRC is received, the master waits for tCSHA duringwhich the voltage on the 1-Wire bus must not fall below 2.8V. During this time the SHA engine of theDS1961S computes the message authentication code over the secret, all 32 data bytes of the selectedpage, the devices registration number (without the CRC) and the 3-byte challenge. Now the masterreads the 160-bit MAC, which is followed by an inverted CRC as a means to safeguard the datatransfer. If the master continues reading after the CRC it receives AAh.

3.2.7 Refresh Scratchpad [A3h]Refresh scratchpad loads memory data to the scratchpad and sets the EN_LFS flag, which enables theuse of the load first secret command to re-write the data that was just read from the memory, bypassingthe MAC computation of copy scratchpad. The command flow chart of refresh scratchpad is very similarto write scratchpad. If the target address is between 0000h007Fh, there are two primary differences.1) The data bytes that the master transmits following the target address are discarded; instead, thescratchpad is loaded with the unaltered memory data located at the target address, even if the memorypage is in EPROM mode. 2) After the master has transmitted the eight dummy bytes, the EN_LFS flagis set to 1. The EN_LFS flag is cleared to 0 after receiving TA1 and TA2 during a write scratchpad,compute next secret, read authenticated page, refresh scratch, read memory, or by a power-on reset,because these commands can change the target address and/or the data in the scratchpad. Whenapplied to addresses 0080h008Fh, the refresh scratchpad command behaves the same way aswrite scratchpad. This protects the secret from being exposed by a subsequent read scratchpad

command.

3.2.8 Read Memory [F0h]The read memory command can be used to read all memory except for the secret. Attempting to readthe secret results in FFh bytes instead of the actual secret. After the master has issued the commandcode and specified the target addresses (TA1 and TA2), the DS1961S first clears the EN_LFS flag. Ifthe target address is valid, the master reads data beginning from the target address and can continueuntil address 0097h. If the master continues reading, the result is logic 1s. It is important to realize thatthe target address registers point to the last byte read. The ending offset/data status byte and thescratchpad are unaffected. The hardware of the DS1961S provides a means to accomplish error-freewriting to the memory section. To safeguard reading data in the 1-Wire environment and tosimultaneously speed up data transfers, it is recommended to packetize data into data packets of thesize of one memory page each. Such a packet typically stores a master-calculated 16-bit CRC with

each page of data to ensure rapid, error-free data transfers that eliminate having to read a pagemultiple times to determine if the received data is correct or not. (Refer to Application Note 114 for therecommended file structure, which is also referred to as TMEX Format.)

3.2.9 Read ROM [33h]This command allows the bus master to read the DS1961Ss 8-bit family code, unique 48-bit serialnumber, and 8-bit CRC. This command should only be used if there is a single slave on the bus. If morethan one slave is present on the bus, a data collision occurs when all slaves try to transmit at the sametime (open drain produces a wired-AND result). The resultant family code and 48-bit serial number readby the master are invalid.

3.2.10 Match ROM [55h]The match ROM command, followed by a 64-bit registration number, allows the bus master to address

a specific DS1961S on a multidrop bus. Only the DS1961S that exactly matches the 64-bit registrationnumber responds to the following memory function command. All other slaves wait for a reset pulse.This command can be used with single or multiple devices on the bus.


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3.2.11 Search ROM [F0h]When a system is initially brought up, the bus master may not know the number of devices on the 1-Wire bus or their 64-bit registration numbers. The search ROM command allows the bus master to usea process of elimination to identify the 64-bit numbers of all slave devices on the bus. The search ROMprocess is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write

the desired value of that bit. The bus master performs this 3-step routine on each bit of the registrationnumber. After one complete pass, the bus master knows the 64-bit number of one device. Additionalpasses will identify the registration numbers of the remaining devices. Refer to Chapter 5 of The Bookof DS19xx iButton Standards for a detailed discussion of a search ROM, including an actual example.

3.2.12 Skip ROM [CCh]This command can save time in a single drop bus system by allowing the bus master to access thememory and SHA functions without providing the 64-bit registration number. If more than one slave ispresent on the bus and, for example, a read command is issued following the skip ROM command, datacollision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce awired-AND result).

3.2.13 Resume Command [A5h]In a typical application the DS1961S needs to be accessed several times to write a full 32-byte page. Ina multidrop environment this means that the 64-bit registration number of a match ROM command hasto be repeated for every access. To maximize the data throughput in a multidrop environment theresume command function was implemented. This function checks the status of the RC bit and, if it isset, directly transfers control to the memory and SHA functions, similar to a skip ROM command. Theonly way to set the RC bit is through successfully executing the match ROM, search ROM, or overdrivematch ROM command. Once the RC bit is set, the device can repeatedly be accessed through theresume command function. Accessing another device on the bus clears the RC bit, preventing two ormore devices from simultaneously responding to the resume command function.

3.2.14 Overdrive Skip ROM [3Ch]On a single-drop bus this command can save time by allowing the bus master to access the memory

and SHA functions without providing the 64-bit registration number. Unlike the normal skip ROMcommand the overdrive skip ROM sets the DS1961S in the overdrive mode (OD = 1). Allcommunication following this command code has to occur at overdrive speed until a reset pulse ofminimum 480s duration resets all devices on the bus to regular speed (OD = 0). When issued on amultidrop bus this command sets all overdrive-supporting devices into overdrive mode. To subsequentlyaddress a specific overdrivesupporting device, a reset pulse at overdrive speed has to be issuedfollowed by a match ROM or search ROM command sequence. This speeds up the search process. Ifmore than one slave supporting overdrive is present on the bus and the overdrive skip ROM commandis followed by a read command, data collision occurs on the bus as multiple slaves transmitsimultaneously (open-drain pulldowns produce a wired-AND result).

3.2.15 Overdrive Match ROM [69h]The overdrive match ROM command, followed by a 64-bit registration number transmitted at overdrive

speed, allows the bus master to address a specific DS1961S on a multidrop bus and to simultaneouslyset it in overdrive mode. Only the DS1961S that exactly matches the 64-bit number responds to thesubsequent memory or SHA function command. Slaves already in overdrive mode from a previousoverdrive skip or a successful overdrive match command will remain in overdrive mode. Alloverdrivecapable slaves return to regular speed at the next reset pulse of minimum 480s duration. Theoverdrive match ROM command can be used with single or multiple devices on the bus.

3.2.16 TRANSACTION SEQUENCEThe protocol for accessing the DS1961S through the 1-Wire port is as follows:_ Initialization_ ROM Function Command_ Memory or SHA Function Command_ Transaction/Data


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3.3 DS1971

3.3.1 WRITE SCRATCHPAD [0Fh]After issuing the Write Scratchpad command, the master must first provide a 1-byte address, followedby the data to be written to the scratchpad for the data memory. The DS1971A will automatically

increment the address after every byte it received. After having received a data byte for address 1Fh,the address counter will wrap around to 00h for the next byte and writing continues until the mastersends a Reset Pulse.

3.3.2 READ SCRATCHPAD [AAh]This command is used to verify data previously written to the scratchpad before it is copied into the finalstorage EEPROM memory. After issuing the Read Scratchpad command, the master must provide the1-byte starting address from where data is to be read. The DS1971A will automatically increment theaddress after every byte read by the master. After the data of address 1Fh has been read, the addresscounter will wrap around to 00h for the next byte and reading continues until the master sends a ResetPulse.

3.3.3 COPY SCRATCHPAD [55h]

After the data stored in the scratchpad has been verified the master may send the Copy Scratchpadcommand followed by a validation key of A5h to transfer data from the scratchpad to the EEPROMmemory. This command will always copy the data of the entire scratchpad. Therefore, if one desires tochange only a few bytes of the EEPROM data, the scratchpad should contain a copy of the latestEEPROM data before the Write Scratchpad and Copy Scratchpad commands are issued. After thiscommand is issued, the data line must be held at logic high level for at least 10ms.

3.3.4 READ MEMORY [F0h]The Read Memory command is used to read a portion or all of the EEPROM data memory and to copythe entire data memory into the scratchpad to prepare for changing a few bytes. To copy data from thedata memory to the scratchpad and to read it, the master must issue the read memory commandfollowed by the 1-byte starting address from where data is to be read from the scratchpad. The DS1971will automatically increment the address after every byte read by the master. After the data of address

1Fh has been read, the address counter will wrap around to 00h for the next byte and reading continuesuntil the master sends a Reset Pulse. If one intends to copy the entire data memory to the scratchpadwithout reading data, a starting address is not required; the master may send a Reset Pulseimmediately following the command code.

3.3.5 WRITE APPLICATION REGISTER [99h]This command is essentially the same as the Write Scratchpad command, but it addresses the 64-bitregister scratchpad. After issuing the command code, the master must provide a 1-byte address,followed by the data to be written. The DS1971 will automatically increment the address after every byteit received. After having received a data byte for address 07h, the address counter will wrap around to00h for the next byte and writing continues until the master sends a Reset Pulse. The Write ApplicationRegister command can be used as long as the application register has not yet been locked. If issued fora device with the application register locked, the data written to the register scratchpad will be lost.

3.3.6 READ STATUS REGISTER [66h]The status register is a means for the master to find out if the application register has beenprogrammed and locked. After issuing the read status register command, the master must provide thevalidation key 00h before receiving status information. The two least significant bits of the 8-bit statusregister will be 0 if the application register was programmed and locked; all other bits will always read 1.The master may finish the read status command by sending a Reset Pulse at any time.

3.3.7 READ APPLICATION REGISTER [C3h]This command is used to

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