1

Understanding Operational Amplifier Limitations

and Long-Term Stability

By Marek LisSr Application Engineer

Texas Instruments -Tucson

2

Summary of Topics

• Review of Op-Amp Input Topologies– Common Mode limits

• Causes of Op-Amp Output Phase Inversion – Bipolar vs. JFET input effects caused by exceeding the Vcm

• Review of Op-Amp Output Topologies– Output Swing limits

• Long-Term Stability Spec– for specs centered around a fixed value– for parameters specified as an absolute value

3

4

REAL WORLD Vcm Input Range

V+ V+

V+V+

5

OP AMP OPERATION vs SUPPLY VOLTAGE

V3 36

Vout2V+

Vos

V1 18

Vout1V+

Vos

Vin 18

-

+ +

U1 OPA140

-

+ +

U2 OPA140

V7 18

V2 136

Vout4V+

Vos

V4 31

Vout3V+

Vos

V5 118

-

+ +

U3 OPA140

-

+ +

U4 OPA140

V6 5

Vin 13

V8 100

30.6uV13V

30.6uV118V

30.6uV30.6uV

30.6uV18V

Note: A single-supply optimized op amp is not the same as a single supply op amp.

Each amplifier has 36V supplies!

The common mode in each case is the supply midpoint.

All amps can act as “single supply”

6

MOSFET Simple Input (Vcm to negative rail)

+

-V+

V-

5V

OPA336

-0.2V< Vin- < 4V

-0.2V< Vin+ < 4V +

-V+

V-

+2.5V

OPA336

-2.7V< Vin- < 1.5V

-2.5V

-2.7V< Vin- < 1.5V

7

Simplified schematic of OPA336 input stage(Swing to Positive Rail)

Q4Q3

IS1

Q1Q2

-Vs-0.2V < VINcm < +Vs-1V

-Vsupply

+Vsupply

VIN+

VIN-

to second stage

Vgs=0.9V

Vsat=0.1V

Vin swing to positive rail:Vsat+Vgs=.1V+.9V=1.0V

Q4 is Cuttoff!

8

Simplified schematic of OPA336 input stage (Swing to Negative Rail)

Q4Q3

IS1

Q1Q2

-Vs-0.2V < VINcm < +Vs-1V

-Vsupply

+Vsupply

VIN+

VIN-

to second stageVCE =0.6V

Vsat=0.1V

Vgs=0.9V

Vin swing to negative rail:VCE+Vsat-Vgs=.6V+.1V-.9V=-0.2V

Q4 is saturated!

9

+

-V+

V-

+12V

-5V

OPA827

-2V< Vin- < 9V

-2V< Vin+ < 9V

Typical Bipolar or JFET Input (not rail-to-rail)

10

Simplified schematic of OPA827 input stageSwing to Negative Rail

IS1

IN-IN+

R1 R2

IS2

Cc

D1

D2

R3

to output stage

Vpos

Vneg

(V-)+3V < VINcm < (V+)-3V

VR2Vbe

Vbe

Vsat

Vgs

Swing to negative RailVin > Vneg + VR2 + 2VBE + Vsat - Vgs

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MOSFET Complementary N-P-FET (rail-to-rail)

+

-V+

V-

5V

OPA703

-0.3V< Vin- < 5.3V

-0.3V< Vin+ < 5.3V +

-V+

V-

+2.5V

OPA703

-2.8V< Vin- < 2.8V

-2.5V

-2.8V< Vin- < 2.8V

12

Simplified schematic of OPA703 input stage

NCH3

PCH2

PCH1

VCM_Iswitch

IS2

IS1

T8

NCH4

T2

PCH input pair active for:-Vs-0.3V< Vcm < +Vs-2V

-Vsupply

+Vsupply

VIN+

VIN-

2V

NCH input pair active for:+Vs-2V < Vcm < +Vs+0.3V

Turns on when +Vs-2V < Vcm < +Vs+0.3V

Steals current from PCH

13

OPA703 Complementary CMOS (rail-to-rail)

0. 0 1. 0 2. 0 3. 0 4. 0 5.0Common Mode Voltage

Inpu

t O

ffse

t V

olta

ge (u

V)

200

100

0

-100

-200

-300

14

MOSFET Charge Pump (rail-to-rail)

+

-V+

V-

5V

OPA365

-0.1V< Vin- < 5.1V

-0.1V< Vin+ < 5.1V

+

-V+

V-

+2.5V

OPA365

-2.6V< Vin- < 2.6V

-2.5V

-2.6V< Vin- < 2.6V

15

Remember from Earlier in the presentation…

Q4Q3

IS1

Q1Q2

-Vs-0.2V < VINcm < +Vs-1V

-Vsupply

+Vsupply

VIN+

VIN-

to second stage

Vgs=0.9V

Vsat=0.1V

Vin swing to positive rail:Vsat+Vgs=.1V+.9V=1.0V

Q4 is Cuttoff!

The limit is based on the positive supply minus saturation voltage and Vgs.

16

MOSFET Charge Pump OPA363 (rail-to-rail)

• Supplies a small current to input

• GBW = 50MHz, Charge Pump Freq=10MHz

17

MOSFET Zero Drift (rail-to-rail)

+

-V+

V-

5V

OPA333

-0.1V< Vin- < 5.1V

-0.1V< Vin+ < 5.1V+

-V+

V-

+2.5V

OPA333

-2.6V< Vin- < 2.6V

-2.5V

-2.6V< Vin- < 2.6V

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MOSFET Zero Drift (rail-to-rail)

0.0 1.0 2.0 3.0 4.0 5.0Common Mode Voltage

Inpu

t Offs

et V

olta

ge (

uV)

200

100

0

-100

-200

-300

0.0 1.0 2.0 3.0 4.0 5.0Common Mode Voltage

Inpu

t Offs

et V

olta

ge (

uV)

200

100

0

-100

-200

-300

With Offset Correction

No Offset Correction

VIN-

VIN+

+VSUPPLY

-VSUPPLY

Q1 Q2

Q3 Q4 To Offset Correction

Circuits

19

Zero Drift Chopper Topology

20

Zero Drift Auto-Zero Topology

21

Input Bias Current in Chopper Op Amps

22

23

Typical Case of Op Amp Phase Inversion due to exceeding Vcm

24

Phase inversion on a single transistor

T1 !PNP

+

Vin

R1

5k

V1 6

Vc

R3

1k

V+

Vce

V +

Vcb

T

Time (s)

0.00 500.00u 1.00m

Vc

81.72m

977.85m

Vcb

-4.92

675.13m

Vce

15.54m

5.51

Vin

0.00

5.00

25

PNP Bipolar Input Op Amp Low Common-Mode LimitationNormal Operation – No Phase Inversion

26

PNP Bipolar Input Op Amp Low Common-Mode LimitationPhase Inversion Issue!

27

An Example of IC Circuit used to Prevent a Phase Inversion

PCH2PCH1

VCM_Isw itch

IS1

T8 Noname

T2 Noname

T1 T3

IS2

IS3 IS4

IS5 IS6

T4T5

T6 T7

-Vsupply

+Vsupply

VIN+

VIN-

2V

To Output Stage

N-channel Anti-PhaseReversal Differential Pair

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Summary of Output Phase Inversion

What causes a phase reversal? Exceeding the input common-mode voltage range may cause a phase reversal.

How can it be prevented? Staying with op amp specified Vcm linear region

Using op amp with a built-in anti-phase reversal circuitryUtilizing external circuitry to prevent a phase inversion

Is it process dependent? Some built-in anti-phase reversal circuitry might be process dependent depending on topology used

Most modern op amps use a robust topologies assuring no phase reversal

How can a customer be confidant of no phase reversal?

(if it is not explicitly stated in the data sheet) Apply a slow triangular waveform in a buffer configuration 1V beyond rails

to test for phase inversion - you must limit the input current to less than 10mA to prevent damaging IC

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30

Op Amp Input Common-Mode Below Negative Rail

T1 !NPNT2 !NPN

T5

T6T7

Cc

T8 !NPN

T3T4

T9 T10

D1 D2

D3 D4

Iref

Vss

VIN+

VIN-

-> to output stage

Vin < 0V results in forward biasing low-side ESD protection diode, D4

31

Op Amp Input Common-Mode Above Positive Rail

T1 !NPNT2 !NPN

T5

T6T7

Cc

T8 !NPN

T3T4

T9 T10

D1 D2

D3 D4

Iref

Vss

VIN+

VIN-

-> to output stage

Vin > Vss results in forward biasing high-side ESD protection diode, D2

32

JFET Input Op Amp High Common-Mode Limitationto positive rail looks like “dc rail to rail”to negative rail shows phase inversion.

T11

T4

D5

T10 2N2608T9 2N2608

Iref

D4D3

D2D1 T3

T8 !NPN

Cc

T7 T6

T5

T2 !NPN T1 !NPN

Vdc=Vss-0.6V

Vdc=Vss-1.2VVss > Vin > Vss-0.3V may result in a lower BW and SR while higher noise and THD

Vgs=0.6V-> to output stage

VIN-

VIN+

Vss

Vsat=0.3V

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34

REAL WORLD Outputs

V+

V+ V+

35

Classic Output Stage

• Common-emitter output• Current source driver• Headroom set by

VBE+VCESAT

• Unity Gain

Q 1

Q 2

V O UTVBE

VSAT

36

OPA827 – Classic Output

OPA827

OPA827Short Circuit Limit

Output Saturated

37

OPA827

OPA827 – Classic Output

The Table Output Swing is defined at:

Vout swing = 18V – 3V = ±15V

Iout = 15V/1k = 15mA

For Aol > 120dB

As you approach the limit or increase ILOAD, Aol will decrease.

38

R-to-R Output Stage

• Common Collector or Common Drain

• Headroom set by VDSsat or VCEsat

• On bipolar sat is approximately 0.2V– After sat Beta drops dramatically

• On FET sat is limited by output transistor scaling – Can achieve very low sat values (e.g. mV)

+V s

R LO AD R LO AD

+V s

-Vs-Vs

Vsat = 0.2VVsat = 50mV to ≈ 1mV

39

R-to-R Output Stage

• Value of RLOAD affects AOL and Output Swing

– the gain in the last stage is set by rout / gm

– rout decreases with loading

+V s

R LO AD R LO AD

+V s

-Vs-Vs

40

Why can’t we get Rail-to-Rail on CMOS?MOSFET Characteristic Curves

• Some minimum drain to source voltage is required.

• Increasing current requires more Vgs.

41

Typical Rail-to-Rail Input/Output Topology

42

OPA211 – rail-to-rail Out (Bipolar)

Loading limits output swing and reduces Aol.

43

Achieving Output Swing to the Negative Rail

5V

RLOAD

-5V

Cut off

Q1

Q2

44

SS Pull Down Cheat Sheet

Part # Resistor Value for -5V Supply

OPA335 40 kΩ

OPA340 7.5 kΩ

OPA343 7.5 kΩ

OPA348 250 kΩ

OPA350 2 kΩ

OPA353 2 kΩ

OPA333 20 kΩ

Selected to sink quiescent current in output stage. Approximately ½ Iq.

45

Common Questions: Op Amp Output Range Consideration

V3 5

Vout2-

+ +

U2 OPA140

VF2

V1 5

Vout1-

+ +

U1 OPA140

Vos

RF 1kRIN 1k

V2 -2.5

A Valid Op Amp Configuration (Input and Output within the linear range)

An Invalid Op Amp Configuration (Output outside of the linear range)

26.7uV2.5V 171.4mV

171.4mV

-

+ +

U1 OPA140

V1 2.5

V2 2.5

VF1

What causes the problem here?

-260.570012mV

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47

Gaussian (or Normal) Distribution

0%

2%

4%

6%

8%

10%

12%

14%

16%

18%

65 70 75 80 85 90 95 100

105

110

115

120

125

130

135

140

145

±1 St Dev±3 St Dev

68% within 68% within ±±1 standard deviation1 standard deviation

99.7% within 99.7% within ±±3 standard deviations3 standard deviations

48

Understanding Statistical Distributions(specs centered around a mean value)

49

Long-Term (10 year) Shift for Gaussian Distributions (Centered around a Mean Value)

Initial PDS Distribution (blue) vs Long-Term Parametric Shift (green)

For 10 year life of a product.

50

Life-Time Vos and Vos Temp Drift Shift

Life-Time Max Shift (ten-year) = Max Initial Value

Long-Term Max Spec = 2 * Initial Spec

Max LT Vos = 240uV Max LT Vos Drift = 2.0uV/C

51

Life-Time Output Voltage Initial Accuracy Shift (specs centered around a fixed value)

Max LT Vref = +/-0.1%

52

Long-Term Vref Shift

The initial shift (first few months) makes up the majority of change. Self curing of molding compound.

53

Single Ended Limit

Iq 25C, OPA827

0 0 0 0 2 4 2889

217

612

806

1192

911

717

269

126

24 6 0 1 0 00

200

400

600

800

1000

1200

1400

<4.

00

<4.

08

<4.

15

<4.

23

<4.

30

<4.

38

<4.

45

<4.

53

<4.

60

<4.

68

<4.

75

<4.

83

<4.

90

<4.

98

<5.

05

<5.

13

<5.

20

<5.

28

<5.

35

<5.

43

<5.

50

>5.

50

[V]

Co

un

t

Mean = 4.80

Std. dev. = 0.13

Num = 5004

+3σ-3σ

99.7% of all Measurements

Mean = 4.8uA Max = 5.2uANo Min Spec

A typical MIN and MAX range is at least +/-3σ:

Mean = Typical

MAX = Mean + 3σ (or greater)

MIN = Mean - 3σ (or greater)

54

Long-Term Shift for Single-ended Specs

+10%

-10%

+/- 1dB = +/-10%

55

Reading Between the Lines(estimating max spec based on a typical value)

Numb Standard Deviations

% chance of Pass

Percent Chance of Fail

1 68.2689491 31.73105087

2 95.449973 4.550027049

3 99.7300204 0.269979613

4 99.9936658 0.006334248

5 99.9999427 5.73303E-05

6 99.9999998 1.97318E-07

3 sigma 0.27% failures

56

Life-Time Shift Rule Summary

You may estimate the maximum expected parametric shift over any given period of time by using:

– 100% of the max (min) PDS guaranteed value in the case of

specs centered around a mean value (Vos, Vref, Vos Drift, etc). – 10% of the max (min) guaranteed value for parameters

specified as a fixed positive value (IQ, AOL, PSRR, CMRR, etc).

and pro-rate them based on the expected ten-year life of the product.

You need to keep in mind that the long-term shift is not exactly a linear function of time - it is steeper (shifts faster) in the first year and slows down in the later years. It also usually excludes the first 30 days due to continuing self-curing of the molding compound used for packaging of IC. 

57

Acknowledgments

Contributed to this presentation:

Art Kay & Todd Toporski

Thank youfor

your interest

58

59

HTOL (High Temperature Operating Life)

• HTOL is used to measure the constant failure rate region in the bottom of the bathtub curve as well as assess the wear-out phase of the curve for some use conditions.

• Smaller sample sizes than EFR but are run for a much longer duration

• Jedec and QSS default are Ta=125C for 1000 hours

• Q100 is 1000 hours at max temperature for the device’s grade

• Most modern IC’s undergo HTOL at Ta=150C for 300 hours

• But how much is this simulating in the field?

60

The Arrhenius Equation

Process Rate = Ae-(Ea/kT)

A = A constant

Ea = Thermal activation energy in electron volts (eV)

k = Boltzman’s constant, 8.62 x 10-5 eV/K

T = Absolute temperature in degrees Kelvin (degrees C + 273.15)

61

Acceleration Factors

Acceleration Factors are the ratio of the Process Rate at two temperatures.

AF(T1 to T2) = e(Ea/k)(1/T2 - 1/T1)

A = A constant (has canceled out of the formula)

Ea = Thermal activation energy in electron volts (eV)

k = Boltzman’s constant, 8.62 x 10-5 eV/K

T = Absolute temperature in degrees Kelvin (degrees C + 273.15)

62

Acceleration Factors (Example)

Calculate the thermal acceleration factor (AF) between the stress test

temperature and the product use temperature:

T (life-test stress) =150C->423K

T (application) =65C->338K

Ea=0.7eV

AF(150 to 65) = e(0.7eV/k)(1/328 - 1/398) = 125

This means every hour of stress at 150C is equivalent to 125 hours of use in the application at 65C.

Thus, for example, 300 hour life-test at 150C would cause similar shift as 37,500 hours (125*300hrs), or about 4 years, in the field at 65C.

63

Questions ???

Comments, Questions, Technical Discussions Welcome:

Marek Lis (520)-750-2162 lis_marek@ti.com