1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat...

46
1 State Encoding of State Encoding of Large Asynchronous Large Asynchronous Controllers Controllers Josep Carmona and Jordi Josep Carmona and Jordi Cortadella Cortadella Universitat Politècnica de Universitat Politècnica de Catalunya Catalunya Barcelona, Spain Barcelona, Spain
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Transcript of 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat...

Page 1: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

11

State Encoding of Large State Encoding of Large Asynchronous Asynchronous

ControllersControllersJosep Carmona and Jordi Josep Carmona and Jordi

CortadellaCortadella

Universitat Politegravecnica de Universitat Politegravecnica de CatalunyaCatalunya

Barcelona SpainBarcelona Spain

2

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

3

This work

Synthesis of Async Synthesis of Async ControllersControllers

HDL

Graph Model

Logic

Gates

Physical

Implementation

CSP Tangram Balsa Veriloghellip

Petri nets Automata hellip

Complex gates

two-level hellip

CMOS FPGAs hellip

4

Synthesis of Async Synthesis of Async ControllersControllers

a

b

xy

c

y-

a+ b+

x+ y+

c+

c-

a-

b-

x-

x+ y-

y+x-

synthesis

Signal Transition Graph

y-

a+ b+

x+ y+

c+

c-

a-

b-

x-

x+ y-

y+x-

5

DeviceLDS

LDTACK

D

DSr

DSw

DTACK

VME BusController

DataTransceiver

BusDSr

LDS

LDTACK

D

DTACK

Read Cycle

6

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

7

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

Specification

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

Implementation

8

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph (read cycle)

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

0100000000

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

9

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

10000

10010

10110

1011111111

01111

0111010110

01000

The encoding problemThe encoding problem00000

LDS-

LDTACK-LDS+

LDTACK+

10

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

01000DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

11

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

Boolean equationsBoolean equations

LDS = D cscDTACK = DD = LDTACK csc = DSr

Logic asynchronous circuit

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

12

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph

XX 22XX

1010 10241024

2020 10485761048576

3030 10737418241073741824

4040 10995116277761099511627776

5050 11258999068426112589990684262424

State space explosion problem

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

13

Event-based vs State-based Event-based vs State-based modelmodel

Petri Net

State Graph

14

Our approach to state Our approach to state encodingencoding

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

csc -

csc +DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

csc+ csc+

csc-

15

OutlineOutlineSynthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers

(overview)(overview)Structural approach for state encodingStructural approach for state encoding

Detection of conflicting statesDetection of conflicting states Disambiguation by consistent signal Disambiguation by consistent signal

insertioninsertion Main algorithm for conflict resolutionMain algorithm for conflict resolution MILP model to insert consistent signalsMILP model to insert consistent signals

Experimental resultsExperimental resultsConclusionsConclusions

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 2: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

2

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

3

This work

Synthesis of Async Synthesis of Async ControllersControllers

HDL

Graph Model

Logic

Gates

Physical

Implementation

CSP Tangram Balsa Veriloghellip

Petri nets Automata hellip

Complex gates

two-level hellip

CMOS FPGAs hellip

4

Synthesis of Async Synthesis of Async ControllersControllers

a

b

xy

c

y-

a+ b+

x+ y+

c+

c-

a-

b-

x-

x+ y-

y+x-

synthesis

Signal Transition Graph

y-

a+ b+

x+ y+

c+

c-

a-

b-

x-

x+ y-

y+x-

5

DeviceLDS

LDTACK

D

DSr

DSw

DTACK

VME BusController

DataTransceiver

BusDSr

LDS

LDTACK

D

DTACK

Read Cycle

6

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

7

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

Specification

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

Implementation

8

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph (read cycle)

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

0100000000

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

9

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

10000

10010

10110

1011111111

01111

0111010110

01000

The encoding problemThe encoding problem00000

LDS-

LDTACK-LDS+

LDTACK+

10

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

01000DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

11

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

Boolean equationsBoolean equations

LDS = D cscDTACK = DD = LDTACK csc = DSr

Logic asynchronous circuit

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

12

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph

XX 22XX

1010 10241024

2020 10485761048576

3030 10737418241073741824

4040 10995116277761099511627776

5050 11258999068426112589990684262424

State space explosion problem

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

13

Event-based vs State-based Event-based vs State-based modelmodel

Petri Net

State Graph

14

Our approach to state Our approach to state encodingencoding

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

csc -

csc +DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

csc+ csc+

csc-

15

OutlineOutlineSynthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers

(overview)(overview)Structural approach for state encodingStructural approach for state encoding

Detection of conflicting statesDetection of conflicting states Disambiguation by consistent signal Disambiguation by consistent signal

insertioninsertion Main algorithm for conflict resolutionMain algorithm for conflict resolution MILP model to insert consistent signalsMILP model to insert consistent signals

Experimental resultsExperimental resultsConclusionsConclusions

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 3: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

3

This work

Synthesis of Async Synthesis of Async ControllersControllers

HDL

Graph Model

Logic

Gates

Physical

Implementation

CSP Tangram Balsa Veriloghellip

Petri nets Automata hellip

Complex gates

two-level hellip

CMOS FPGAs hellip

4

Synthesis of Async Synthesis of Async ControllersControllers

a

b

xy

c

y-

a+ b+

x+ y+

c+

c-

a-

b-

x-

x+ y-

y+x-

synthesis

Signal Transition Graph

y-

a+ b+

x+ y+

c+

c-

a-

b-

x-

x+ y-

y+x-

5

DeviceLDS

LDTACK

D

DSr

DSw

DTACK

VME BusController

DataTransceiver

BusDSr

LDS

LDTACK

D

DTACK

Read Cycle

6

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

7

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

Specification

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

Implementation

8

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph (read cycle)

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

0100000000

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

9

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

10000

10010

10110

1011111111

01111

0111010110

01000

The encoding problemThe encoding problem00000

LDS-

LDTACK-LDS+

LDTACK+

10

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

01000DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

11

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

Boolean equationsBoolean equations

LDS = D cscDTACK = DD = LDTACK csc = DSr

Logic asynchronous circuit

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

12

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph

XX 22XX

1010 10241024

2020 10485761048576

3030 10737418241073741824

4040 10995116277761099511627776

5050 11258999068426112589990684262424

State space explosion problem

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

13

Event-based vs State-based Event-based vs State-based modelmodel

Petri Net

State Graph

14

Our approach to state Our approach to state encodingencoding

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

csc -

csc +DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

csc+ csc+

csc-

15

OutlineOutlineSynthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers

(overview)(overview)Structural approach for state encodingStructural approach for state encoding

Detection of conflicting statesDetection of conflicting states Disambiguation by consistent signal Disambiguation by consistent signal

insertioninsertion Main algorithm for conflict resolutionMain algorithm for conflict resolution MILP model to insert consistent signalsMILP model to insert consistent signals

Experimental resultsExperimental resultsConclusionsConclusions

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 4: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

4

Synthesis of Async Synthesis of Async ControllersControllers

a

b

xy

c

y-

a+ b+

x+ y+

c+

c-

a-

b-

x-

x+ y-

y+x-

synthesis

Signal Transition Graph

y-

a+ b+

x+ y+

c+

c-

a-

b-

x-

x+ y-

y+x-

5

DeviceLDS

LDTACK

D

DSr

DSw

DTACK

VME BusController

DataTransceiver

BusDSr

LDS

LDTACK

D

DTACK

Read Cycle

6

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

7

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

Specification

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

Implementation

8

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph (read cycle)

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

0100000000

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

9

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

10000

10010

10110

1011111111

01111

0111010110

01000

The encoding problemThe encoding problem00000

LDS-

LDTACK-LDS+

LDTACK+

10

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

01000DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

11

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

Boolean equationsBoolean equations

LDS = D cscDTACK = DD = LDTACK csc = DSr

Logic asynchronous circuit

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

12

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph

XX 22XX

1010 10241024

2020 10485761048576

3030 10737418241073741824

4040 10995116277761099511627776

5050 11258999068426112589990684262424

State space explosion problem

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

13

Event-based vs State-based Event-based vs State-based modelmodel

Petri Net

State Graph

14

Our approach to state Our approach to state encodingencoding

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

csc -

csc +DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

csc+ csc+

csc-

15

OutlineOutlineSynthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers

(overview)(overview)Structural approach for state encodingStructural approach for state encoding

Detection of conflicting statesDetection of conflicting states Disambiguation by consistent signal Disambiguation by consistent signal

insertioninsertion Main algorithm for conflict resolutionMain algorithm for conflict resolution MILP model to insert consistent signalsMILP model to insert consistent signals

Experimental resultsExperimental resultsConclusionsConclusions

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 5: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

5

DeviceLDS

LDTACK

D

DSr

DSw

DTACK

VME BusController

DataTransceiver

BusDSr

LDS

LDTACK

D

DTACK

Read Cycle

6

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

7

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

Specification

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

Implementation

8

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph (read cycle)

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

0100000000

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

9

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

10000

10010

10110

1011111111

01111

0111010110

01000

The encoding problemThe encoding problem00000

LDS-

LDTACK-LDS+

LDTACK+

10

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

01000DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

11

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

Boolean equationsBoolean equations

LDS = D cscDTACK = DD = LDTACK csc = DSr

Logic asynchronous circuit

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

12

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph

XX 22XX

1010 10241024

2020 10485761048576

3030 10737418241073741824

4040 10995116277761099511627776

5050 11258999068426112589990684262424

State space explosion problem

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

13

Event-based vs State-based Event-based vs State-based modelmodel

Petri Net

State Graph

14

Our approach to state Our approach to state encodingencoding

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

csc -

csc +DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

csc+ csc+

csc-

15

OutlineOutlineSynthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers

(overview)(overview)Structural approach for state encodingStructural approach for state encoding

Detection of conflicting statesDetection of conflicting states Disambiguation by consistent signal Disambiguation by consistent signal

insertioninsertion Main algorithm for conflict resolutionMain algorithm for conflict resolution MILP model to insert consistent signalsMILP model to insert consistent signals

Experimental resultsExperimental resultsConclusionsConclusions

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 6: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

6

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

7

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

Specification

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

Implementation

8

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph (read cycle)

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

0100000000

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

9

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

10000

10010

10110

1011111111

01111

0111010110

01000

The encoding problemThe encoding problem00000

LDS-

LDTACK-LDS+

LDTACK+

10

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

01000DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

11

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

Boolean equationsBoolean equations

LDS = D cscDTACK = DD = LDTACK csc = DSr

Logic asynchronous circuit

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

12

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph

XX 22XX

1010 10241024

2020 10485761048576

3030 10737418241073741824

4040 10995116277761099511627776

5050 11258999068426112589990684262424

State space explosion problem

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

13

Event-based vs State-based Event-based vs State-based modelmodel

Petri Net

State Graph

14

Our approach to state Our approach to state encodingencoding

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

csc -

csc +DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

csc+ csc+

csc-

15

OutlineOutlineSynthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers

(overview)(overview)Structural approach for state encodingStructural approach for state encoding

Detection of conflicting statesDetection of conflicting states Disambiguation by consistent signal Disambiguation by consistent signal

insertioninsertion Main algorithm for conflict resolutionMain algorithm for conflict resolution MILP model to insert consistent signalsMILP model to insert consistent signals

Experimental resultsExperimental resultsConclusionsConclusions

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 7: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

7

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

Specification

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

Implementation

8

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph (read cycle)

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

0100000000

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

9

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

10000

10010

10110

1011111111

01111

0111010110

01000

The encoding problemThe encoding problem00000

LDS-

LDTACK-LDS+

LDTACK+

10

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

01000DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

11

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

Boolean equationsBoolean equations

LDS = D cscDTACK = DD = LDTACK csc = DSr

Logic asynchronous circuit

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

12

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph

XX 22XX

1010 10241024

2020 10485761048576

3030 10737418241073741824

4040 10995116277761099511627776

5050 11258999068426112589990684262424

State space explosion problem

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

13

Event-based vs State-based Event-based vs State-based modelmodel

Petri Net

State Graph

14

Our approach to state Our approach to state encodingencoding

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

csc -

csc +DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

csc+ csc+

csc-

15

OutlineOutlineSynthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers

(overview)(overview)Structural approach for state encodingStructural approach for state encoding

Detection of conflicting statesDetection of conflicting states Disambiguation by consistent signal Disambiguation by consistent signal

insertioninsertion Main algorithm for conflict resolutionMain algorithm for conflict resolution MILP model to insert consistent signalsMILP model to insert consistent signals

Experimental resultsExperimental resultsConclusionsConclusions

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 8: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

8

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph (read cycle)

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

0100000000

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

9

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

10000

10010

10110

1011111111

01111

0111010110

01000

The encoding problemThe encoding problem00000

LDS-

LDTACK-LDS+

LDTACK+

10

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

01000DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

11

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

Boolean equationsBoolean equations

LDS = D cscDTACK = DD = LDTACK csc = DSr

Logic asynchronous circuit

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

12

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph

XX 22XX

1010 10241024

2020 10485761048576

3030 10737418241073741824

4040 10995116277761099511627776

5050 11258999068426112589990684262424

State space explosion problem

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

13

Event-based vs State-based Event-based vs State-based modelmodel

Petri Net

State Graph

14

Our approach to state Our approach to state encodingencoding

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

csc -

csc +DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

csc+ csc+

csc-

15

OutlineOutlineSynthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers

(overview)(overview)Structural approach for state encodingStructural approach for state encoding

Detection of conflicting statesDetection of conflicting states Disambiguation by consistent signal Disambiguation by consistent signal

insertioninsertion Main algorithm for conflict resolutionMain algorithm for conflict resolution MILP model to insert consistent signalsMILP model to insert consistent signals

Experimental resultsExperimental resultsConclusionsConclusions

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 9: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

9

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

10000

10010

10110

1011111111

01111

0111010110

01000

The encoding problemThe encoding problem00000

LDS-

LDTACK-LDS+

LDTACK+

10

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

01000DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

11

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

Boolean equationsBoolean equations

LDS = D cscDTACK = DD = LDTACK csc = DSr

Logic asynchronous circuit

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

12

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph

XX 22XX

1010 10241024

2020 10485761048576

3030 10737418241073741824

4040 10995116277761099511627776

5050 11258999068426112589990684262424

State space explosion problem

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

13

Event-based vs State-based Event-based vs State-based modelmodel

Petri Net

State Graph

14

Our approach to state Our approach to state encodingencoding

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

csc -

csc +DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

csc+ csc+

csc-

15

OutlineOutlineSynthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers

(overview)(overview)Structural approach for state encodingStructural approach for state encoding

Detection of conflicting statesDetection of conflicting states Disambiguation by consistent signal Disambiguation by consistent signal

insertioninsertion Main algorithm for conflict resolutionMain algorithm for conflict resolution MILP model to insert consistent signalsMILP model to insert consistent signals

Experimental resultsExperimental resultsConclusionsConclusions

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 10: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

10

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Encoded State Graph

10000

10010

10110

1011111111

01111

0111010110

01000DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

11

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

Boolean equationsBoolean equations

LDS = D cscDTACK = DD = LDTACK csc = DSr

Logic asynchronous circuit

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

12

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph

XX 22XX

1010 10241024

2020 10485761048576

3030 10737418241073741824

4040 10995116277761099511627776

5050 11258999068426112589990684262424

State space explosion problem

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

13

Event-based vs State-based Event-based vs State-based modelmodel

Petri Net

State Graph

14

Our approach to state Our approach to state encodingencoding

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

csc -

csc +DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

csc+ csc+

csc-

15

OutlineOutlineSynthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers

(overview)(overview)Structural approach for state encodingStructural approach for state encoding

Detection of conflicting statesDetection of conflicting states Disambiguation by consistent signal Disambiguation by consistent signal

insertioninsertion Main algorithm for conflict resolutionMain algorithm for conflict resolution MILP model to insert consistent signalsMILP model to insert consistent signals

Experimental resultsExperimental resultsConclusionsConclusions

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 11: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

11

DTACK

D

DSr

LDS

LDTACK

csc

synthesis

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

Complete State Coding (CSC)

csc -

csc +

Boolean equationsBoolean equations

LDS = D cscDTACK = DD = LDTACK csc = DSr

Logic asynchronous circuit

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

12

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph

XX 22XX

1010 10241024

2020 10485761048576

3030 10737418241073741824

4040 10995116277761099511627776

5050 11258999068426112589990684262424

State space explosion problem

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

13

Event-based vs State-based Event-based vs State-based modelmodel

Petri Net

State Graph

14

Our approach to state Our approach to state encodingencoding

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

csc -

csc +DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

csc+ csc+

csc-

15

OutlineOutlineSynthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers

(overview)(overview)Structural approach for state encodingStructural approach for state encoding

Detection of conflicting statesDetection of conflicting states Disambiguation by consistent signal Disambiguation by consistent signal

insertioninsertion Main algorithm for conflict resolutionMain algorithm for conflict resolution MILP model to insert consistent signalsMILP model to insert consistent signals

Experimental resultsExperimental resultsConclusionsConclusions

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 12: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

12

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

State Graph

XX 22XX

1010 10241024

2020 10485761048576

3030 10737418241073741824

4040 10995116277761099511627776

5050 11258999068426112589990684262424

State space explosion problem

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

13

Event-based vs State-based Event-based vs State-based modelmodel

Petri Net

State Graph

14

Our approach to state Our approach to state encodingencoding

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

csc -

csc +DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

csc+ csc+

csc-

15

OutlineOutlineSynthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers

(overview)(overview)Structural approach for state encodingStructural approach for state encoding

Detection of conflicting statesDetection of conflicting states Disambiguation by consistent signal Disambiguation by consistent signal

insertioninsertion Main algorithm for conflict resolutionMain algorithm for conflict resolution MILP model to insert consistent signalsMILP model to insert consistent signals

Experimental resultsExperimental resultsConclusionsConclusions

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 13: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

13

Event-based vs State-based Event-based vs State-based modelmodel

Petri Net

State Graph

14

Our approach to state Our approach to state encodingencoding

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

csc -

csc +DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

csc+ csc+

csc-

15

OutlineOutlineSynthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers

(overview)(overview)Structural approach for state encodingStructural approach for state encoding

Detection of conflicting statesDetection of conflicting states Disambiguation by consistent signal Disambiguation by consistent signal

insertioninsertion Main algorithm for conflict resolutionMain algorithm for conflict resolution MILP model to insert consistent signalsMILP model to insert consistent signals

Experimental resultsExperimental resultsConclusionsConclusions

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 14: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

14

Our approach to state Our approach to state encodingencoding

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

csc -

csc +DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

DTACK-DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

csc+ csc+

csc-

15

OutlineOutlineSynthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers

(overview)(overview)Structural approach for state encodingStructural approach for state encoding

Detection of conflicting statesDetection of conflicting states Disambiguation by consistent signal Disambiguation by consistent signal

insertioninsertion Main algorithm for conflict resolutionMain algorithm for conflict resolution MILP model to insert consistent signalsMILP model to insert consistent signals

Experimental resultsExperimental resultsConclusionsConclusions

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 15: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

15

OutlineOutlineSynthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers

(overview)(overview)Structural approach for state encodingStructural approach for state encoding

Detection of conflicting statesDetection of conflicting states Disambiguation by consistent signal Disambiguation by consistent signal

insertioninsertion Main algorithm for conflict resolutionMain algorithm for conflict resolution MILP model to insert consistent signalsMILP model to insert consistent signals

Experimental resultsExperimental resultsConclusionsConclusions

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 16: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

16

Detection of conflicting Detection of conflicting statesstates

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+

bull ILP [Carmona amp Cortadella ICCADrsquo03]

bull SAT-UNFOLD [Khomenko et al Fund Informaticae]

LDS-

LDTACK-DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 17: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

17

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

STG Insertion of signal s must1 Solve conflict2 Preserve consistency3 Preserve persistency

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

10000

10010

10110

10111 01111

01110

10110

11111

10100DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

(CSC + consistency + persistency = SI-circuit)

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 18: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

18

Implicit placeImplicit place

a+ b+

x-

a-

y+

x+ y-

b-

DEF1 (Behavior) The behavior of the net does not depend on the place DEF2 (Petri net) it never disables the firing of a transition

y+

a-

x-

a+

b+

x+ x+

y-

y-

b-

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 19: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

19

ConsistencyConsistency

y- b+

x-

y+

x+ x-

b-

Consecutive firings of a signal must alternate

y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+ y+ x- y- b+ x- x+ b- y+

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 20: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

20

Implicit Places amp ConsistencyImplicit Places amp Consistency

y- b+

x-

y+

x+ x-

b-

y=1

y=0

Theorem (Colom et al)Places y=0 and y=1 are implicitif and only if signal y is consistent

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 21: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

21

Disambiguation by consistent signal Disambiguation by consistent signal insertioninsertion

DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

Disambiguate the conflicting statesby introducing a new signal s

s+

s-

Insertion of s into the STGbull s- will precede LDS+bull s+ will precede DTACK-

LDS+s- LDS+

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 22: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

22

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

LDS+

DTACK-

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 23: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

23

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 24: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

24

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 25: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

25

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 26: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

26

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 27: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

27

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 28: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

28

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 29: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

29

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is not implicit

s is not consistent

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 30: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

30

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

read cycle write cycle

s=0s=1

s=0 is implicit

s=1 is implicit

s is consistent

s-D-

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 31: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

31

s+DTACK-DSr+

s-LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-D-

DTACK+

read cycle write cycle

s=0s=1

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 32: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

32

s+DSr+

s-

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw-

DSw+

D+

LDS+

LDTACK+

s-

DTACK+

read cycle write cycle

LDS+

DTACK-

D-

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 33: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

33

Main algorithm for solving CSC Main algorithm for solving CSC conflictsconflicts

while CSC conflits exist do (σ1σ2)= Find traces connecting conflict (s=0s=1)= Find implicit places

to break conflict Insert s+s- transitions connected to (s=0) or (s=1)endwhile

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 34: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

34

Goal avoid state enumeration to Goal avoid state enumeration to check implicitness of a placecheck implicitness of a place

Classical methods to avoid the Classical methods to avoid the explicit state space enumerationexplicit state space enumeration Linear Algebra (LPMILP)Linear Algebra (LPMILP) Graph TheoryGraph Theory Symbolic representation (BDDs)Symbolic representation (BDDs) Partiar order (Unfoldings)Partiar order (Unfoldings)

State space explosion State space explosion problemproblem

Structural methods

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 35: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

35

Marking equationMarking equation

a+

a-

b-

b+

c+

c- b+

p1

p2 p3 p4 p5

p6 p7

a+ a- b+ b+ b- c+ c-p1 -1 0 0 0 1 -1 0p2 1 0 -1 0 0 0 0p3 1 -1 0 0 0 0 0p4 0 0 0 0 0 1 -1p5 0 0 0 -1 0 1 0p6 0 0 1 0 -1 0 1p7 0 1 0 1 -1 0 0

Incidence matrix

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 36: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

36

1 0 0 0 0 0 0

Marking equationMarking equation

Mrsquo = M + Ax

=

Necessary reachability condition but not sufficient

0 0 0 0 0 1 1

a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0

+

1 1 1 0 0 0 0

p1

p2

p3

p4

p5

p6

p7

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 37: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

37

LP model to check place LP model to check place implicitnessimplicitness

LP formulation M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0

M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

M0 M

M

P ndash pp

x

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 38: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

38

LP model to check place LP model to check place implicitnessimplicitness

LP formulation

M0 + Ax = M

M[Prsquo] ndash F[Prsquopbull]middots 0M[p] ndash F[ppbull]middots lt 0

s1 = 1x M s 0

A place p is implicit if the following LP model is infeasiblewhere Prsquo = P ndash p

[Silva et al]

LP formulation

min ymiddot M0

ymiddotA[PrsquoT] le A[pT]ymiddot F[Prsquo pbull] ge F[p pbull]

yge 0

DUAL

A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP where Prsquo = P ndash p

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 39: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

39

MILP model to insert a implicit MILP model to insert a implicit place place

A

p

Arsquo

MILP variables y p

MILP formulation

min ymiddot M0

ymiddotArsquo[PrsquoT] le Arsquo[pT] ymiddot Frsquo[Prsquo pbull] ge F[p

pbull]yge 0

np 101

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 40: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

40

MILP model to find insertion MILP model to find insertion points that disambiguate the points that disambiguate the

conflict conflict

MILP formulationMILP ldquos=0 implicitrdquo

MILP ldquos=1 implicitrdquo (σ1s+) = (σ1s-) + 1(σ2s-) = (σ2s+) + 1

M0[s=0] + M0[s=1] = 1 DSr+ DTACK-

D-

DSr-DTACK+

D+

LDS+

LDTACK+ LDS-

LDTACK-

If there is a solution rows in Arsquo for s=0 and s=1 describe the insertion points (arcs in the net)

σ1σ2

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 41: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

41

OutlineOutline

Synthesis of Asynchronous Controllers Synthesis of Asynchronous Controllers (overview)(overview)

Structural approach for state encodingStructural approach for state encodingExperimental resultsExperimental resultsConclusionsConclusions

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 42: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

42

Number of inserted encoding Number of inserted encoding signalssignals

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

1

2

3

4

5

6

7petrify (state-based)MILP (structural)

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 43: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

43

Number of literals (area)Number of literals (area)

Benchmarks from [Cortadella et al IEEE TCADrsquo97]

0

5

10

15

20

25

30

35

40

45

50 petrify (state-based)MILP (structural)

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 44: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

44

Experimental results large Experimental results large controllerscontrollers

example Places Trans Signals CPU(min) sig Lits HDLArt(109) 216 198 99 36 28 305 ---

Art(209) 436 398 199 730 57 629 ---

PpWk(312) 142 74 37 10 3 190 ---

PpArb(312) 164 90 43 115 2 206 ---

Var(95) 302 338 150 64 24 613 ---

Var(121) 368 394 183 127 27 445 ---

Par(12) 63 52 52 02 12 101 253SeqPar(2110) 160 128 64 22 23 269 398SPM(71618) 192 394 60 118 17 237 640

Synthesis with structural methods from[Carmona amp Cortadella ICCADrsquo03]

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 45: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

45

It doesnrsquot always work It doesnrsquot always work

Behaviorally equivalentBehaviorally equivalent

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs

Page 46: 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

46

ConclusionsConclusions

First structural approach to state encodingFirst structural approach to state encodingfor for generalgeneral STGs STGs

Solutions comparable to state-based Solutions comparable to state-based methodsmethods

Structural approach Structural approach can handle large can handle large controllers (few thousands of signals)controllers (few thousands of signals)

May benefit from the well-structured May benefit from the well-structured specs obtained from HDLsspecs obtained from HDLs